30results about How to "Correction of phase difference" patented technology

In a delay locked loop and a semiconductor memory device having the same, the delay locked loop includes a phase detecting and control signal generator for detecting a phase difference between a clock signal and a feedback clock signal and generating a plural-bit delay control signal which varies according to the phase difference; a first delay having a predetermined number of first delay cells which are cascade-connected for delaying the clock signal to generate a plurality of output clock signals and the feedback clock signal in response to the plural-bit delay control signal; a second delay having a predetermined number of second delay cells which are cascade-connected for delaying an inverted clock signal to generate a plurality of inverted output clock signals in response to the plural-bit delay control signal; and a phase mixer for phase-mixing corresponding clock signals among the plurality of output clock signals and the plurality of inverted output clock signals to output a plurality of corrected output clock signals.

An oscillating circuit includes N nodes outputting oscillating signals, a main loop circuit including N inverting circuits, and a plurality of auxiliary loop circuits. Each inverting circuit in the auxiliary loop circuits is connected in parallel with even numbers of inverting circuits cascaded in the main loop circuit. The circuits for feeding back signals from outputs to inputs of the respective inverters of the main loop circuit have circuit configurations equivalent to each other. Each inverting circuit in the main loop circuit and the auxiliary loop circuits drives an output line such that a phase of an output signal is inverted with respect to a phase of an input signal and has driving power that becomes lower when the phases of the output signal and the input signal are inverted with respect to each other than when the output signal and the input signal are in phase with each other.

A clock phase correction circuit includes: a first variable delay circuit suitable for delaying a second source clock to generate a third clock; a first pulse generation circuit suitable for generating a first pulse signal that is activated from an edge of a first clock to an edge of the third clock and generating a second pulse signal that is activated from the edge of the third clock to the edge of the first clock; and a first delay value adjustment circuit suitable for detecting whether a ratio of a pulse width of the first pulse signal to a pulse width of the second pulse signal is greater or less than 1:3 to produce a detection result and adjusting a delay value of the first variable delay circuit based on the detection result.

A master unit and a plurality of slave units are connected by way of a communication path. The master unit sends to the slave units timing signals generated by its own cycle signal generator by way of a communication path. The slave units determine the cycle difference and the phase difference between a timing signal generated by its own cycle signal generator and the timing signal sent from the master unit and, in accordance therewith, determine a cycle adjustment amount. The cycle signal generators of the slave units adjust the timing signal cycle based on the cycle adjustment amount.

Interpolation precision of phase difference detection pixels is raised. An image sensor (14) is provided with a color filter (30) upon which a basic sequence pattern, formed by disposing a first sequence pattern and a second sequence pattern in point symmetry, is repeatedly disposed. In the first sequence pattern, first filters are disposed on pixels in the four corners and in the center of a square array of 3×3 pixels, second filters are disposed in a horizontal line in the center of a square array, and third filters are disposed in a vertical line in the center of a square array. In the second sequence pattern, the first sequence pattern and the positions of the first filters are the same, while the positions of the second filters and the positions of the third filters have been swapped.

Provided is an orbiting memory capable of suppressing residual deviation even when a phase difference is caused between a signal to be compensated and information stored in a memory to be fed back and a disc device using the orbiting memory. The disc device includes: an adder to which a signal (s10) to be compensated and having a cyclic frequency component such as a control system error signal is inputted; and a feed back signal system for successively updating and storing an output signal of the adder for each cycle in a memory and inputting one-cycle information stored in the memory to the adder. The feed back signal system includes: a filter unit for outputting a signal contained in a learning band which is arbitrarily set among output signals from the adder; the memory for successively updating and storing the output signal of the filter unit; a phase correction unit capable of arbitrarily setting a phase amount when inputting the output of the memory to the adder; and a gain element for multiplying the one-cycle information subjected to the phase correction by the phase correction unit by a value not smaller than 0 and not greater than 1 and inputting the obtained value to the adder.

A biological property check device includes a plurality of probes (20) each having a light emitting element (26) for applying light to a biological tissue and a light reception element (28) for detecting the reflected light. Each probe (20) is successively selected by a switch circuit (60) under control of a control section (76) and connected to a property calculation section (64). The property calculation section (64) includes a phase shift circuit for changing the frequency according to the phase difference between the input waveform to the light emitting element (26) and the output waveform from the light reception element (28). According to the frequency change, the property of the biological tissue is calculated. The property calculated is displayed on a display section (74) via a data collection section (70) and a display processing section (72).