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High-linearity neuromorphic calculation circuit realized by passive voltage stabilizing circuit

A voltage stabilizing circuit and high linearity technology, which is applied in the field of neuromorphic computing, can solve the problems of severe circuit linearity, achieve stable integral current, solve poor linearity, and reduce circuit area and power consumption.

Active Publication Date: 2021-07-23
ZHEJIANG UNIV +1
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  • Description
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Problems solved by technology

However, circuits using passive integrators have serious problems in linearity

Method used

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  • High-linearity neuromorphic calculation circuit realized by passive voltage stabilizing circuit
  • High-linearity neuromorphic calculation circuit realized by passive voltage stabilizing circuit
  • High-linearity neuromorphic calculation circuit realized by passive voltage stabilizing circuit

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Embodiment Construction

[0035] The specific embodiments of the invention will be further described below in conjunction with the accompanying drawings.

[0036] Existing active integrators use operational amplifiers as voltage regulators ( figure 1 ), in multi-bit parallel neuromorphic computing, the use of multiple operational amplifiers greatly increases the computational power consumption of the circuit. However, the operation amplifier is removed and the simple 1T1R (1Transistor 1RRAM) storage unit ( figure 2 ) integration can reduce power consumption, but the linearity of the integration is greatly affected by the drop of the capacitor voltage, so it is difficult to obtain a calculation result with high precision.

[0037] Therefore the computing circuit designed by the present invention is as image 3 As shown, it includes 1R1T binary memory cell array, integral capacitor group, bit line capacitor voltage isolation transistor T 0 , passive voltage regulator circuit, input sequence control ...

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Abstract

The invention discloses a high-linearity neuromorphic calculation circuit realized by a passive voltage stabilizing circuit. A 1R1T binary storage unit array is connected with an input sequence control switch and a plurality of bit line capacitor voltage isolation transistors, and the input sequence control switch receives input data of a neural network. Each bit line capacitor voltage isolation transistor is connected with a biasing circuit through a respective passive voltage stabilizing circuit, the plurality of bit line capacitor voltage isolation transistors are jointly connected to an analog-to-digital conversion circuit, and a calculation result is output through the analog-to-digital conversion circuit ADC. According to the invention, the influence of the channel length modulation effect caused by the drop of the capacitor voltage in the integration process can be effectively eliminated, so that the integration current is more stable; and meanwhile, the stability of the source voltage of the T0 under different loads can be ensured, and the technical problem that the linearity of the weight value of the circuit is poor due to the fact that the load change is affected is solved.

Description

technical field [0001] The invention belongs to a neural network computing circuit in the field of neuromorphic computing, and relates to a multi-bit parallel binary neuromorphic computing circuit based on a passive voltage stabilizing circuit. Background technique [0002] In the past decade, as the Internet of Things, cloud computing, computer vision, and artificial intelligence have become more and more closely integrated, sensing devices will become a key interface for smart products to connect to the real world. However, due to the generation of a large amount of sensing data, data transmission and calculation will also be a huge challenge. Traditional intelligent systems have problems such as high construction cost, high energy consumption, low energy efficiency, and high delay due to the separation of data collection, processing, and analysis. In order to solve these problems, it is necessary to put part of the calculation of artificial intelligence on lightweight Io...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F1/56
CPCG05F1/561Y02D10/00
Inventor 黄科杰章烨炜沈海斌
Owner ZHEJIANG UNIV
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