110 results about "Cascode current mirror" patented technology

Even harmonics are suppressed by a harmonics-reducing bias generator that drives bias voltages to cascode control transistors in series with driver transistors in a power amplifier. A first bias voltage is generated by mirroring pull-up currents in the power amplifier. A p-channel source transistor and a p-channel cascode current-mirror transistor also mirror the power amplifier pull-up current to a midpoint node. An n-channel sink transistor and an n-channel cascode current-mirror transistor mirror the pull-down current in the power amplifier to the midpoint node. An op amp compares the midpoint node to VDD/2, and drives the gate of a p-channel feedback transistor. Current from the p-channel feedback transistor flows through an n-channel cascode current-mirror transistor that generates a second bias voltage. The second bias voltage is adjusted until the midpoint node reaches VDD/2, causing the pull-up and pull-down currents in the power amplifier to better match, reducing even harmonics.

The invention discloses a gain increased operational transconductance amplifier which is formed in a manner that a bias constant current source is sequentially connected with differential input, a load current mirror, a cascode output stage and an adjustable auxiliary differential pair in sequence, wherein the differential input is composed of four PMOS pipes namely M1a, M2a, M1b and M2b; the load current mirror is composed of six NMOS pipes namely M3, M4, M5a, M6a, M5b and M6b; the cascode output stage is composed of six MOS pipes namely M7, M8, M9, M10, M11 and M12; the adjustable auxiliary differential pair is composed of M13, M14 and M15. Reutilization of current and the output stage increased adjustable auxiliary differential pair thoroughly solve the inherent contradiction among gain, bandwidth, power dissipation and the like in a circuit; the gain increased operational transconductance amplifier is slightly influenced by output voltage, an additional pole is not introduced, the simulation results show same static power dissipation, and multiplication is realized for gain and bandwidth; the gain increased operational transconductance amplifier further has the characteristics of fine tuning and high accuracy and is applicable to communication, electronic measurement and automatic control systems.

Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. In one embodiment, the self-biasing cascode current mirror is an optional aspect of the folded-cascode OTA. The self-biasing can advantageous reduce the number of biasing circuits used, which can save chip area and cost. One embodiment includes an input differential pair of a current-mirror OTA.

A bias circuit for providing at least first and second bias signals for biasing a cascode current source and/or a cascode current sink includes a resistive element and first, second and third transistors, each transistor having first and second source/drain terminals and a gate terminal. The first source/drain terminal of the first transistor is coupled to the gate terminal, the first bias signal being generated at the first source/drain terminal in response to receiving a first reference current at the first source/drain terminal. A first end of the first resistive element is coupled to the second source/drain terminal of the first transistor. The gate terminal of the second transistor is coupled to the gate terminal of the first transistor, the second bias signal being generated at the first source/drain terminal of the second transistor in response to receiving a second reference current at the first source/drain terminal of the second transistor. The first source/drain terminal of the third transistor is coupled to the second source/drain terminal of the second transistor, the second source/drain terminal of the third transistor is coupled to a second end of the first resistive element, and the gate terminal of the third transistor is coupled to the first source/drain terminal of the second transistor.

A cascode amplifier (CA) (60) is described having a bottom transistor (T1_new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1_new) to width (W1_new) and a series coupled top transistor (T2_new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of channel length (Lch2_new) to width (W2_new). An improved cascode current mirror (CCM) (74) is formed using a coupled pair of CAs (60, 60′), one (60) forming the reference current (RC) side (601) and the other (60′) forming the mirror current side (602) of the CCM (74). The gates (65, 65′) of the bottom transistors (T1_new, T3_new) are tied together and to the common node (21) between the series coupled bottom (T1_new) and top (T2_new) transistors of the RC side (601), and the gates (66′, 66′) of the top transistors (T2_new, T4_new) are coupled together and to the top drain node (64) of the RC side (601). The area of the CCM (74) can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.

A cascode current mirror circuit and a bandgap circuit are provided. The circuits are used together and function as a reference voltage circuit. The reference voltage circuit outputs a reference current resistant to temperature variation and ripple-voltage. Accordingly, a voltage stabilizing/regulating circuit corrects error voltage precisely and promptly, and the resultant voltage is temperature insensitive and ripple-voltage-independent.

An Early voltage and beta current compensated cascode current mirror includes a cascode current mirror having an input stage responsive to an input current, a current mirror circuit having a first stage responsive to the input stage and a second stage responsive to the first stage, and an output stage responsive to the second stage for providing an output voltage and current; and a compensation circuit, responsive to the cascode current mirror, having a first compensation stage, a second compensation stage and a bootstrapping buffer, the first compensation stage, in response to a change in the output voltage, impressing a corresponding change in voltage on the second compensation stage, the second compensation stage thereby providing a change in current to the cascode current mirror for cancelling current errors induced by base current modulation in the output stage, the bootstrapping buffer, in response to the change in voltage, impressing a corresponding change in voltage on the first compensation stage to prevent errors from base current modulation effects in the first compensation stage, the first and second compensation stages further providing a base current to the cascode current mirror for cancelling base current errors in the output current induced by the cascode current mirror.

Disclosed is a CMOS current mirror circuit including a first MOS transistor and a second MOS transistor constituting a current mirror, in which a drain of the first MOS transistor and a gate of the second MOS transistor are connected in common, a source of the first MOS transistor is directly grounded, and a gate of the first MOS transistor is connected to the drain of the first MOS transistor through a third MOS transistor which has a source connected to the drain of the first MOS transistor, a drain connected to the gate of the first MOS transistor, and a gate being biased. The source of the second MOS transistor is directly grounded. Current is input to the drain of the third MOS transistor. The drain current of the second MOS transistor is mirrored by cascode current mirror circuits. An output current is output from the source of a MOS transistor for conversion to a voltage by a circuit that receives the current which outputs a reference voltage.

A kind of CMOS common source common bar high plus current voltage converter, The invention relates to current voltage converting technique field, it includes common source common bar current mirror composed by transistors, the common source common bar current mirror is end-to-end joint by the common source common bar current mirror composed by four PMOS transistors and the common source common bar current mirror composed by four NMOS transistors, the alternating current signal is input from the joint position of upper and lower current mirror, and imaged by two current mirrors, the output voltage equals to the product of input current and output common source common bar structure resistance. The invention converts tiny pA class current signal to mV voltage, realizes high plus with character that the output resistance of the common source common bar current mirror is big, the structure is simple and plus is big, because there is feedback resistance, problem of stability does not be taken into account.

The invention discloses an all-CMOS (Complementary Metal Oxide Semiconductor) reference voltage source with a high power supply rejection ratio, which comprises a reference voltage source. The reference voltage source comprises a starting circuit, a current source circuit and a temperature compensating circuit, wherein an output end of the starting circuit is connected with an input end of the current source circuit; an output end of the current source circuit is connected with an input end of the temperature compensating circuit; an output end of the temperature compensating circuit forms an output end of the whole reference voltage source. The working characteristic of an MOS transistor working in a sub-threshold region is utilized by the all-CMOS reference voltage source, a nanoampere-magnitude reference current is generated; power supply noise is rejected by adopting a cascode current mirror. In addition, the all-CMOS reference voltage source not only has the advantages that the chip area is small and the power consumption is low and is only nanowatt-magnitude, but also has the advantages that the all-CMOS reference voltage source has the high power supply rejection ratio, the temperature drift coefficient is low, and the line-voltage regulation is low; moreover, a resistor, a diode and a triode are not used; the all-CMOS reference voltage source is compatible with a standard CMOS process; the layout area is effectively reduced; the production cost is decreased.

A circuit and a method for biasing a compound cascode current mirror (CCCM) that enables high-voltage swing at the output and accurate current mirroring is presented. The CCCM has mirror transistors and cascode transistors which may be of a different technology kind. The drain-source voltage Vds of the mirror transistor on the input leg of the CCCM is held at a voltage Vov that is generated by the biasing circuit; Vov is the overdrive voltage of the input mirror transistor of the CCCM and the value of Vov is maintained by the bias circuit and a feed-back amplifier such that the mirror transistor remains on the edge of its active region, over manufacture deviations and tracks even over operational conditions such as temperature and supply variations. The feed-back amplifier drives the gates of the cascode transistors and uses its feedback node to hold the Vds at Vov.

A bandgap voltage generator generates an output reference voltage and is configured to operate from a low voltage power supply and consumes low power. The bandgap voltage generator includes a non-cascode current mirror that is directly connected to a power supply input and that produces current mirror outputs in response to the power supply input. A differential amplifier senses two of the current mirror outputs, and generates an output that controls the non-cascode current mirror so that the current mirror outputs produce substantially the same current and voltage at the sensed current mirror outputs. A bandgap core circuit includes first and second bipolar devices that receive the constant current from the two current mirror outputs. The first bipolar device is scaled in size relative to the second bipolar device so as to produce an output voltage at a third current mirror output that is multiple of the characteristic bandgap voltage of the bipolar devices. The non-cascode current mirror includes FET devices having their respective sources connected to the power supply input, and having their respective drains connected to the respective current mirror outputs. The FETs are not implemented with a cascode configuration, so that the bandgap voltage generator can operate with a low voltage power supply and also consumes low power.

The invention discloses a current comparator, comprising a current difference stage, a gain stage and an output stage, wherein the current difference stage is a cascode current mirror, a current inputend is connected with an MOS transistor with short circuited gate and drain, so that the equivalent input impedance of the current comparator is reduced, and the comparison speed can be improved; thegain stage introduces a common source amplifier of a current source load with feedback, a current source bias voltage is generated by a high threshold voltage tube, so that the bias tube current canbe reduced, and the power consumption is reduced; and the output stage introduces a self-biased differential amplifier, so that the driving capability of the output comparator can be obviously improved. Theoretical analysis and simulation results indicate that the current comparator disclosed by the invention has the characteristics of high precision and high driving capability.

A current mirror circuit which is connected to first and second power supplies and generates a desired current, has a plurality of first transistors which are connected in parallel to the first power supply side and the gates of which are connected to a common node, a plurality of second transistors which are cascode-connected to the plurality of first transistors and the gates of which are supplied with a cascode bias potential and a cascode bias generation circuit which generates the cascode bias potential, wherein the cascode bias generation circuit maintains the cascode bias potential during normal operation at a first potential between the potentials of the first and second power supplies, and maintains the cascode bias potential during power-on at a second potential closer to the potential of the second power supply than the first potential.

A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain a conduction angle of at least about 180 DEG . The dc bias circuit includes a self-bias boosting circuit which has a cascode current-mirror circuit having an output coupled to a control terminal of the amplifying transistor by a resistor, and a capacitor coupled from the cascode current-mirror circuit to a common terminal. The value of the capacitor can be selected to obtain the desired amount of self-bias boosting.