24 results about "Cascode current mirror" patented technology

Bias circuits for CMOS power amplifiers are provided. The bias circuit includes a feedback module, a first bias module, and a second bias module. The feedback module has a first input connected to a output common mode voltage, a second input connected to a reference voltage, and an output connected to gates of main amplification transistors in a first differential amplification module; based on a difference between the output common mode voltage and the reference voltage, the feedback module adjusts gate voltages of main amplification transistors until the output common mode voltage is equal to the reference voltage; the first bias module provides bias voltages for the first differential amplification module; the second bias module provides bias voltages for a second differential amplification module. The present disclosure adopts direct negative feedback and cascoded current mirrors, which realize accurate DC gate bias and accurate control of the output common mode voltage.

The utility model discloses a readout circuit, a readout system and a solid-state imaging device for image sensing, which relate to the technical field of image sensing readout, and comprise a pixel array unit used for photoelectric signal conversion; a current mirror circuit unit; wherein the current mirror circuit unit comprises a cascode current mirror or two N-channel field effect transistors; a negative impedance conversion unit; and a charging and discharging acceleration unit. According to the utility model, the negative impedance conversion unit and the charging and discharging acceleration unit are utilized, and the negative impedance generated by the negative impedance conversion unit counteracts the parasitic capacitance and the parasitic resistance which influence the VSL establishment speed, so that the small signal establishment speed is accelerated; the charging and discharging acceleration unit is used for selectively providing charging and discharging current in the VSL descending establishment process or the VSL ascending establishment process, so that the large signal establishment speed is accelerated. In this way, corresponding response cooperation can be carried out for the VSL descending establishment process or the VSL ascending establishment process.

The present invention discloses a four-quadrant analog multiplier circuit and a control method based on a memristor. The analog multiplier circuit based on a memristor mainly includes a sign conversion circuit, an external control circuit, a memristor control circuit, a Cascode current mirror circuit composed of NMOS transistors, and a Cascode current mirror circuit composed of PMOS transistors. Among them, the Cascode current mirror circuit composed of NMOS transistors and the memristor control circuit form a first-quadrant memristor analog multiplier circuit, and the Cascode current mirror circuit composed of PMOS transistors and the memristor control circuit form a second-quadrant memristor analog multiplier circuit. The sign conversion circuit mainly converts the input signal into a signal in the first and second quadrants and inputs the signal into the corresponding quadrant memristor analog multiplier circuit. After receiving a positive input signal, the external control circuit outputs the control voltage required by the memristor analog multiplier circuit. Compared with the existing analog multiplier circuit, the memristor analog multiplier has higher linearity and accuracy, and the circuit structure and operation process are relatively simple.

The invention discloses a transistor structure, a cascode current mirror and a chip, and belongs to the technical field of integrated circuit chips. The transistor structure comprises at least one transistor unit. The transistor unit comprises a substrate and an active region formed on the substrate. The n grid electrodes are arranged on the active region in the first direction, n is an even number, diffusion regions are defined on the two sides of each grid electrode in the first direction, and the diffusion regions between every two adjacent grid electrodes are continuous; wherein the ith grid electrode is connected with the (ni + 1) th grid electrode, and i = 1, 2,..., n / 2. By sharing the diffusion regions, the area utilization rate is improved, wiring is simplified to reduce parasitic resistance and parasitic capacitance effects, and the layout performance is improved.

Methods and devices for a cascode current mirror with low headroom voltage are presented. According to one aspect, a gate voltage to a cascode transistor of an input leg of the current mirror is provided by a feedback block that operates from a mirrored current output by an output leg of the current mirror. The feedback block includes a feedback current mirror that outputs a mirrored current for conduction through a self-biasing diode-connected transistor that generates the gate voltage to the cascode transistor of the input leg. According to yet another aspect, the cascode current mirror includes a start-up circuit coupled between an input to the input leg and a gate of the cascode transistor of the input leg, the start-up circuit generating a start-up voltage during a transition mode of operation of the cascode current mirror. According to one aspect, a transistor is used as the start-up circuit.

The embodiment of the application provides a BUCK circuit lower tube driving circuit power supply, a BUCK circuit, and a switching power supply chip, the power supply comprises an error current generation module, an error current processing module, and a power supply output module, the error current processing module comprises an error voltage generation circuit, a transient load response capacitor, and a first CASCODE current mirror circuit, the error voltage generation circuit receives error current generated by the error current generation module to output error voltage, one end of the transient load response capacitor is connected with an output end of the error current processing module, the other end is connected with a gate of a common source end of the first CASCODE current mirror circuit, and the output end of the error voltage generation circuit serves as the output end of the error current processing module. The transient load response is good, the rising edge time of the power MOS tube is very short, the switching speed is fast, the cross-over loss is reduced, on the other hand, an external large-capacity capacitor is not needed, PIN pins are saved, and material cost is reduced.

The present invention discloses a high-precision bandgap reference circuit, comprising: a bandgap circuit, which adopts a cascode current mirror structure to generate a positive temperature coefficient current and a negative temperature coefficient voltage; a negative temperature coefficient current extraction circuit, which extracts the negative temperature coefficient voltage generated by the bandgap circuit and generates a negative temperature coefficient current; a current compensation circuit, which receives the current I0 output by the negative temperature coefficient current extraction circuit and the positive temperature coefficient current I generated by the bandgap circuit. IN , and output current with positive temperature coefficient I IN Second-order related compensation current I out The present invention not only retains the advantages of the traditional Bandgap voltage reference such as simple structure and strong process compatibility, but also achieves the goals of low output voltage temperature coefficient and low power consumption.

The invention discloses a high-performance analog front-end circuit applied to a piezoelectric sensor. The circuit comprises a chopping capacitor transimpedance rail-to-rail output operational amplifier circuit, a servoloop circuit module, a piezoelectric sensor modeling circuit, a buffer circuit and a two-phase non-overlapping clock generation circuit. Wherein the two-phase non-overlapping clock controls the chopping modulation switch to suppress low-frequency flicker noise; a cascode current mirror bias source follower of the servop module outputs nA-level current to compensate input leakage current, high output impedance of the cascode current mirror bias source follower and a Miller capacitor generate a secondary pole, and the lower limit cut-off frequency is reduced to the 0.026 Hz level; and the buffer circuit enhances the driving capability of the amplifier. The device can realize low noise, low lower limit cut-off frequency and leakage current compensation, reduces cost and power consumption, improves stability, and is suitable for measurement of vibration, pressure, acceleration and other physical quantities of the piezoelectric sensor.

The invention provides an operational-amplifier-free high-PSRR band-gap reference voltage source. The operational-amplifier-free high-PSRR band-gap reference voltage source comprises a Cascode current mirror module, a negative feedback module, a voltage clamping module and a band-gap core and reference output module. Under the condition that the technology is not changed, the compression point is improved, and the circuit can work in a larger radio frequency receiving range.

Methods and apparatus for a cascode current mirror with a large modulation range, low headroom voltage, and high output impedance are presented. An input branch of the current mirror comprises a compound transistor in series with an intrinsic transistor. The compound transistor comprises two regular transistors connected in series, each with dimensions twice that of the intrinsic transistor. An output branch of the current mirror comprises a regular transistor in series with an intrinsic transistor. A gate voltage of the compound transistor, provided at a node common to the gates of the two series-connected regular transistors, self-adjusts when a reference current flows through the input branch. This self-adjusted gate voltage is used to bias the regular transistor of the output branch.Preloads for the gates of the intrinsic transistors are provided by an intermediate node, which provides the series connection of the regular transistors of the compound transistor.

The invention provides a power-on reset circuit with a Schmitt trigger, which belongs to the technical field of integrated circuits, and comprises a current bias circuit which is composed of components M1, M2, M5, M6, M7 and M8, distributes current through a basic current mirror, and provides stable bias current for a subsequent circuit; the low-voltage cascode current mirror is composed of components M2, M3, M6 and M9, the output impedance is improved, and the influence of output voltage change on the current is reduced; the node capacitor is composed of a component M10 and provides reset time delay; a phase inverter and a Schmitt trigger, the phase inverter realizes level conversion, and the Schmitt trigger filters noise and jitter; and the discharging branch circuit is composed of a component M7, controls the drop speed of the output voltage through discharging, and is matched with the charging process to realize reset delay. By adopting the power-on reset circuit with the Schmitt trigger, the problems of a traditional POR circuit in the aspects of reset pulse amplitude, anti-interference capability and power consumption are solved.

The invention relates to the technical field of integrated circuit design, and provides a self-biased reference current source circuit which comprises a starting circuit and a reference current circuit. The starting circuit adopts a PMOS (P-channel Metal Oxide Semiconductor) tube (MP1-MP3) and an NMOS (N-channel Metal Oxide Semiconductor) tube (MN1-MN2) of which the grid electrodes are grounded, and an inverted tube of which the size ratio of MP1 to MP2 is 1.5: 20, so that the reference current circuit can be quickly helped to get rid of a degeneracy point and the continuous power consumption is reduced; the reference current generating circuit is composed of low-voltage cascode current mirrors (MP4-MP7, R1), triodes (Q1-Q2) and an NMOS tube (MN3), the cascode structure improves output impedance to shield power supply voltage fluctuation, and self-bias stable reference current is achieved through positive feedback. The problems that an existing reference current source is difficult to start, high in power consumption and sensitive to power supply voltage are solved, the temperature coefficient of the reference current can be lower than + / -50 ppm / DEG C, the power supply voltage rejection ratio can be increased by 20 dB or above, and the reference current source is suitable for high-precision analog chips.

Methods and apparatus for a low-headroom cascode current mirror are presented. In one aspect, a gate voltage for a cascode transistor of an input branch of the current mirror is provided by a feedback block operating on a mirrored current output from an output branch of the current mirror. The feedback block includes a feedback current mirror outputting a mirrored current for conduction through a self-biasing diode-connected transistor that generates the gate voltage for the cascode transistor of the input branch. In another aspect, the cascode current mirror includes a start-up circuit coupled between an input of the input branch and a gate of the cascode transistor of the input branch, the start-up circuit generating a start-up voltage during a transient mode of operation of the cascode current mirror.According to one aspect, a transistor is used as a starting circuit.

The invention discloses a current driving circuit for brain nerve stimulation. The current driving circuit comprises a positive-phase current pulse output circuit and a negative-phase current pulse output circuit, the normal-phase current pulse output circuit comprises a first low-voltage cascode current mirror module and a first auxiliary circuit module; the negative-phase current pulse output circuit comprises a second low-voltage cascode current mirror module and a second auxiliary circuit module; the first low-voltage cascode current mirror module and the second low-voltage cascode current mirror module are used for copying the current of the current source and then outputting positive-phase stimulation current or negative-phase stimulation current; the first auxiliary circuit module and the second auxiliary circuit module are used for expanding the feasible range of the bias voltage of the low-voltage cascode current mirror in the current driving circuit; a current monitoring circuit is additionally arranged to monitor the stimulation current, and it is ensured that the stimulation current is at a normal level; according to the invention, the output voltage range of the nerve stimulator is expanded, correct current copying in a full-swing range is realized, and the application scene of the nerve stimulator is wider.

The present invention provides a micro-LED (μLED) current-mode pixel drive circuit system, comprising: a reference current generating circuit, a pixel current driving unit, an 8-bit SRAM unit, a counter, and a comparator. The pixel current driving unit comprises a cascaded current mirror circuit and a switch control tube; the current of the cascaded current mirror circuit is the same as that of the reference current generating circuit. The comparator compares the data stored in the 8-bit SRAM unit with the data in the counter, converts the 8-bit pixel grayscale signal into a PWM signal, and controls the switch control tube via the PWM signal, thereby achieving PWM current control of the μLED brightness. The present invention can accurately copy the constant current of the reference current generating circuit to the cascaded current mirror circuit, and control the on-off time of the switch control tube via the PWM signal generated by the comparator, thereby achieving pulse modulation of the current. This improves the problems of increased difficulty in display brightness control and uneven display caused by traditional voltage control circuits, and can achieve better display effects and contrast.

There is described an electrical switching device for generating a current control electrical signal in a controlled cascode current mirror manner for functional in vivo stimulation, comprising first, second, third and fourth transistors, each transistor having associated source, drain and gate terminals, the second and fourth transistors are connected in an output cascode structure such that a source terminal of the fourth transistor is connected to a drain terminal of the second transistor and a drain terminal of the fourth transistor is connected to an output contact associated with the electrical switching device, a voltage potential associated with the current control electrical signal can be acquired at the output contact. The invention is characterized in that the gate terminal of the fourth transistor is connected in a switchable manner to at least one constant specifiable voltage potential.

The present invention relates to an in-memory accumulative multiplication calculation circuit based on branch current. The in-memory accumulative multiplication calculation circuit based on branch current includes a storage array for storing weight data, the storage array being composed of a plurality of identical SRAM cells, and each column of SRAM cells sharing bit lines BL and BLB. The bit lines BL and BLB are connected to a cascode current mirror unit for replicating a constant current source current. Each column of SRAM cells is connected to an operational amplifier unit for outputting the accumulative multiplication result via the bit line BL. The present invention provides a stable current for the bit lines BL and BLB through the cascode current mirror unit, and replaces the bit line voltage supply with the bit line current supply, thereby further reducing the operation power consumption; the operational amplifier unit can generate a stable output voltage, thereby ensuring the operation speed, stably outputting the operation result, and achieving high parallelism, thereby realizing high-speed and low-power multiplication and accumulation calculation.

This invention discloses a continuous-time current comparator capable of outputting maximum and minimum currents, comprising eight sets of common-source cascode current mirrors composed of NMOS transistors N1-N20 and PMOS transistors P1-P8; the drain of PMOS transistor P2 is simultaneously connected to the drains of NMOS transistors N5 and N7, the drain of PMOS transistor P6 is simultaneously connected to the drains of NMOS transistors N11 and N13, and the drain of PMOS transistor P8 is connected to the drain of NMOS transistor N17; the current to be compared, Ia, is input from the drain of NMOS transistor N1, and after the input, the current to be compared, Ib, is split into two paths, flowing to the drains of NMOS transistors N3 and N9 respectively; the drain of NMOS transistor N19 outputs the maximum current Imax, and the drain of NMOS transistor N15 outputs the minimum current Imin. After the input currents Ia and Ib are compared, the maximum current Imax and minimum current Imin corresponding to Ia and Ib are output through the current replication, summation and difference operation of the common source cascode current mirror, and the maximum current Imax and minimum current Imin are both continuous analog current signals.

The utility model discloses an over-temperature protection circuit and a chip. The over-temperature protection circuit comprises a current supply module, a cascode current mirror, a trim resistor and a voltage comparison module. The current providing module is used for providing current with a zero temperature coefficient; the cascode current mirror is used for carrying out mirror image processing on the current with the zero temperature coefficient and outputting the current with the zero temperature coefficient to a first end of the trim resistor; the trim resistor is used for converting the current with the zero temperature coefficient into detection voltage and outputting the detection voltage to a first input end of the voltage comparison module; the voltage comparison module is used for outputting an over-temperature indication signal according to the detection voltage and the reference voltage. The over-temperature protection circuit provided by the utility model has higher over-temperature detection precision, and the safety of the chip in the working process can be further improved.

The present disclosure provides an operational amplifier clamp circuit, comprising: an operational amplifier and a clamp voltage control circuit. The operational amplifier comprises a cascode current mirror and a first differential input transistor. The first end of the first differential input transistor is connected to the connection node of the first common-gate transistor and the first common-source transistor in the cascode current mirror; the second end of the first differential input transistor is grounded; the control end of the first differential input transistor and the clamp voltage control circuit both receive a first differential input signal; the clamp voltage control circuit is connected to the control end of the first common-gate transistor and is configured to output a first bias voltage to the first common-gate transistor, and to adjust the first bias voltage based on the first differential input signal; the first bias voltage is positively correlated with the voltage of the first differential input signal. Thus, the reliability of the operational amplifier clamp circuit is improved and faults caused by overvoltage or abnormal signals are reduced.

The invention provides a full MOSFET SiC reference voltage source suitable for a wide temperature range, and the reference voltage source comprises a starting circuit which is used for activating a reference voltage source circuit from a degenerate bias state when a power supply is powered on, and generating an enable signal; the self-biased current source circuit is used for generating branch current which rises along with the environment temperature in a wide temperature range under the action of an enable signal, and performing copying and load disturbance shielding processing on the branch current through the SiC MOSFET cascade cascode current mirror to form temperature compensation current with the same characteristics as the branch current; and the temperature compensation circuit is used for converting an input temperature compensation current into a reference voltage which is firstly increased and then reduced along with the increase of the environment temperature in a wide temperature range based on the temperature characteristic of the intrinsic parameter of the SiC MOSFET device. Based on the design, the design complexity of the reference voltage source circuit is remarkably reduced, and the output reliability in a wide temperature range is improved.

The invention discloses a high-precision BJT (Bipolar Junction Transistor) current mirror circuit based on a CMOS (Complementary Metal Oxide Semiconductor) process, which belongs to the field of integrated circuits and comprises a current source bias module, a current mirror core module and a current discharge module. The current source bias module is composed of a PMOS current source, an NMOS current mirror and a cascode current mirror. The current mirror core module is composed of a BJT triode. The current discharge module is composed of a PMOS tube, a resistor path, an NMOS tube connected with a capacitor, and a capacitor. Base bias current is provided for a BJT triode through the current source bias module, the inherent defect that a traditional BJT current mirror structure cannot accurately copy reference current is overcome, and meanwhile the current self-adaptability of the current source bias module is improved by adding the current discharge module. According to the invention, the BJT current mirror can be adopted to accurately copy the reference current under the CMOS technology, the precision is high, the matching performance is good, the flicker noise is low, and the performance of the current mirror can be obviously improved.

Methods and apparatus for a cascode current mirror with a large modulation range, low headroom voltage, and high output impedance are presented. An input branch of the current mirror comprises a compound transistor in series with an intrinsic transistor. The compound transistor comprises two regular transistors connected in series, each with dimensions twice that of the intrinsic transistor. An output branch of the current mirror comprises a regular transistor in series with an intrinsic transistor. A gate voltage of the compound transistor, provided at a node common to the gates of the two series-connected regular transistors, self-adjusts when a reference current flows through the input branch. This self-adjusted gate voltage is used to bias the regular transistor of the output branch.Preloads for the gates of the intrinsic transistors are provided by an intermediate node, which provides the series connection of the regular transistors of the compound transistor.

To provide a differential amplifier capable of a high-speed operation.SOLUTION: A differential amplifier 1 comprises: an input differential pair 12 that generates an output voltage Vout1 corresponding to a difference between a first input voltage Vinp and a second input voltage Vinn, and is connected to a non-inverting input terminal INP to which the first input voltage Vinp is input and an inverting input terminal INN to which the second input voltage Vinn is input; an active load circuit 20 including a cascode current mirror circuit 22 connected as an active load to the input differential pair 12; and an output stage 30 that generates the output voltage according to a signal at an output node of the cascode current mirror circuit 22. In the active load circuit 20, a capacitor is provided between a gate of a transistor constituting a first stage of the cascode current mirror circuit 22 and a reference voltage node.SELECTED DRAWING: Figure 1