78 results about "Harmonic rejection" patented technology

The utility model relates to a radio frequency power amplification circuit with a harmonic suppression function and a radio frequency chip. The radio frequency power amplification circuit comprises an input matching unit, a first-stage power amplification unit, a first-stage bias unit, a first-stage power supply unit, an inter-stage matching unit, a second-stage power amplification unit, a second-stage bias unit, a second-stage power supply unit and an output matching unit. According to the utility model, the LC type trap circuits are designed and used in the power supply unit and the inter-stage matching unit, so that secondary, tertiary and high-order harmonic suppression is realized in the radio frequency power amplification circuit; meanwhile, based on LC circuit structures in the power supply unit and the inter-stage matching unit, the inter-stage matching bandwidth is widened, and the linearity of the multi-stage power amplification unit is improved.

Architectures are presented for transmitters and receivers that use a harmonic rejection mixer that uses a 6-phase clock signal, while also using a differential in-phase / quadrature input signal (for the transmitter) or output signal (for the receiver). This results in crosstalk between the in-phase and quadrature components, where a digital correction circuit forms a linear combination of the baseband I / Q signals to generate the I / Q for the mixer in order to obtain the desired baseband signal. By using a differential I / Q signal, only two DACs / ADCs are needed, saving circuitry area and power consumption, while providing strong 2nd, 3rd, and 4th clock harmonic rejection. The clock signal can be composed of two sets of 3-phase signals, each signal having a 33% duty cycle.

The invention discloses a reactive compensation and harmonic suppression method and device for an underground coal mine mobile substation. The method comprises the following steps: acquiring a working condition signal of load side electric equipment and a voltage signal and a current signal of a wire inlet end of the reactive compensation and harmonic suppression device; based on the voltage signal and the current signal, determining a reactive power gap value of the low-voltage side of the mobile substation and a temperature rise contribution weight of harmonic waves of each preset frequency to a cable of the low-voltage side of the mobile substation; based on the working condition signal, the reactive power gap value and the temperature rise contribution weight, a cooperative control instruction is generated and comprises a switching control instruction for a reactive compensation module in the reactive compensation and harmonic suppression device and a filtering control instruction for a harmonic suppression module in the reactive compensation and harmonic suppression device; and reactive compensation and harmonic suppression are carried out on the low-voltage side of the mobile substation. According to the invention, the accuracy and fineness of reactive compensation and harmonic suppression of the underground coal mine mobile substation are improved, so that the high-quality stable power supply requirement of an underground power grid is met.

This invention discloses a millimeter-wave broadband high harmonic suppression tripler, comprising an input matching network, a time-domain shaping tripler unit, and a differential common-source output stage. The proposed time-domain shaping tripler unit employs transistor pairs with different gate widths and bias voltages to superimpose two sets of voltage signals of different amplitudes in the time domain, thereby enhancing the inherent harmonic suppression of the tripler unit. Furthermore, by connecting a common-mode impedance control in series at the center tap of the primary inductor coil of the output transformer of the tripler unit, the output power of the third harmonic is further improved. The input matching network achieves single-ended to differential conversion, with its primary and secondary coil center taps grounded and open-circuited respectively in a counterintuitive manner, improving differential-mode balance and common-mode stability. Simultaneously, by using a series-coupled inductor, the quality factor of the transistor input impedance is reduced, improving the bandwidth performance of the tripler.

The application discloses a high-efficiency omnidirectional rectenna based on a class-F harmonic suppression structure and belongs to the rectenna field, comprising: a plurality of rectenna units which are arranged at equal intervals and rotate around the same center and are used for receiving radio frequency energy; the rectenna unit comprises a receiving antenna and a rectifier circuit; the receiving antenna comprises an antenna radiation structure, a metal floor and a feed microstrip line; a U-shaped groove is arranged on a region of the antenna radiation structure which is close to the metal floor, and a rectangular groove is arranged in the U-shaped groove; the U-shaped groove and the rectangular groove are used for suppressing the radiation of the second harmonic and the third harmonic; the rectifier circuit is arranged on the upper surface of a PCB and is used for rectifying the output signal of the antenna radiation structure by the microstrip line and electronic components; and the plurality of rectenna units are connected through a direct current synthesis network, so that the size of the rectenna can be reduced and the efficiency of the rectenna can be improved.

The application discloses a micro-grid power quality global optimization method, comprising the following steps: collecting real-time data, dividing the real-time data into several segments according to the frequency, and calculating the harmonic compensation capacity of each frequency segment according to the real-time data; according to the calculated harmonic compensation capacity, priority allocation is performed on the compensation order of the contaminated nodes in the micro-grid; the virtual impedance of the inverter and the injected damping resistance are adjusted, and the harmonic current and resonance phenomenon in the micro-grid are suppressed in the frequency segment; according to the adjusted virtual impedance and damping resistance, the node admittance matrix is updated, the compensation capacity of the inverter is monitored in real time, the real-time monitoring data is compared with the threshold value, if the threshold value is exceeded, the inverter is corrected, otherwise, no change is made. Through the frequency segment control, the pertinence and effect of harmonic suppression are improved, the frequency segment suppression of the micro-grid harmonic and high-frequency resonance is realized, the residual capacity of the inverter is dynamically matched with the harmonic compensation demand, and the safe and stable operation of the system is ensured.

The application discloses a kind of ultra-wideband high harmonic suppression power amplifier, including low-frequency power amplification branch, high-frequency power amplification branch, harmonic suppression matching network, the harmonic suppression matching network includes low-frequency harmonic suppression matching network, high-frequency harmonic suppression matching network and common output end;The low-frequency power amplification branch, high-frequency power amplification branch respectively to the frequency different low-frequency band signal, high-frequency band signal in work wideband is carried out power amplification, the low-frequency harmonic suppression matching network, high-frequency harmonic suppression matching network respectively to the impedance matching of fundamental wave in low-frequency band signal, high-frequency band signal after power amplification, while inhibiting second and third harmonic signals.The application solves the problem of low power efficiency and poor high-order harmonic suppression in the prior art.

The invention discloses a frequency quadrupler circuit, and belongs to the technical field of integrated circuits. The circuit comprises a first frequency multiplication stage and a second frequency multiplication stage which are cascaded. The core improvement is that the control ends of the third transistor and the fourth transistor in the second frequency multiplication stage are directly and electrically connected to the output nodes of the first transistor and the second transistor in the first frequency multiplication stage respectively. According to the connection mode, secondary harmonic signals which are naturally generated at two output nodes of the first-stage push-pull structure and are matched in amplitude and opposite in phase are directly used as differential input of the second stage, and therefore a necessary inter-stage transformer in the prior art is thoroughly omitted. The interstage transformer effectively solves the problems that in a traditional scheme, an interstage transformer is difficult to achieve at low frequency, the size is large, and the phase performance of differential signals is prone to being deteriorated, and has the advantages of being simplified in structure, reduced in size and better in output power and harmonic suppression performance.

Disclosed in the present invention is a high‑linearity, high‑power GaAs HBT power amplifier having a power detection function, characterized in that: the GaAs HBT power amplifier comprises a radio frequency path, a bias module and a power detection circuit. The radio frequency path is used to perform power amplification on a radio frequency signal, a negative feedback network is used to improve the stability and expand the bandwidth, and second harmonic suppression improves the overall linearity. The bias circuit is used to provide, to a three-stage amplification circuit, a bias voltage that dynamically changes along with an input power, so as to solve the problems of linearity degradation and current instability caused by a self-heating effect in a GaAs HBT transistor under high-power input, thereby mitigating amplitude-amplitude distortion and amplitude-phase distortion of the power amplifier. The power detection circuit is used to output a direct current voltage that is positively correlated with an output power, so as to achieve accurate control of the output power of the power amplifier. By fully integrating negative feedback, dynamic biasing and harmonic suppression techniques, the present invention effectively improves the overall linearity of the amplifier.

This invention provides a miniaturized, on-chip, internally matched power amplifier device with high harmonic suppression, belonging to the field of harmonic suppression amplifier technology. By introducing a cascaded design of multi-stage power amplifiers, combined with internal matching technology and the innovative application of high-dielectric ceramics and molybdenum-copper carriers, this invention successfully solves problems related to gain enhancement, harmonic suppression, and thermal management. This solution achieves miniaturization while simultaneously improving power density and gain, enhancing harmonic suppression performance to -45dBc, and optimizing efficiency. Furthermore, the combination of a molybdenum-copper carrier and a conformal heat dissipation module effectively reduces thermal resistance, extends device lifespan, and meets stringent high-temperature and high-frequency environmental requirements, improving system reliability and efficiency while reducing device size and weight.

The application discloses a current multiplexing phase-shifting mixer with high harmonic suppression ratio IN The I and Q two groups of differential signals generated by the quadrature generating unit are input into the I-path high harmonic suppression ratio phase-shifting mixing unit and the Q-path high harmonic suppression ratio phase-shifting mixing unit respectively, mixed with the differential local oscillator signal in the local oscillator signal and the control signal of the time sequence control unit, and phase-shifting is realized to generate the I and Q two paths of differential intermediate frequency signals; the positive terminal in the I-path differential intermediate frequency signal and the positive terminal in the Q-path differential intermediate frequency signal are input into the same load to generate an intermediate frequency positive output signal; the negative terminal in the I-path differential intermediate frequency signal and the negative terminal in the Q-path differential intermediate frequency signal are input into the same load to generate an intermediate frequency negative output signal; and the intermediate frequency positive output signal and the intermediate frequency negative output signal jointly constitute an intermediate frequency differential output signal. The application has the advantages of simple and compact structure, improved phase-shifting precision of the system, realized mixing, and reduced power consumption of the system.

The invention provides a miniaturized slide-type internal matching power amplification device with high harmonic suppression, relates to the technical field of harmonic suppression amplifiers, and provides a miniaturized slide-type internal matching power amplification device with high harmonic suppression by introducing a cascade design of a multi-stage power amplifier and combining an internal matching technology and innovative application of high-dielectric ceramic and molybdenum copper slide. The problems of gain improvement, harmonic suppression, thermal management and the like are successfully solved. According to the scheme, the miniaturized design is realized, the power density and the gain are also improved, the harmonic suppression performance is improved to-45dBc, and the efficiency is also optimized. Meanwhile, the molybdenum copper slide glass is combined with the conformal heat dissipation module, so that the thermal resistance can be effectively reduced, the service life of the device is prolonged, the strict high-temperature and high-frequency environment requirements are met, the reliability and the working efficiency of the system are improved, and the size and the weight of equipment are reduced.

The invention relates to an open-loop modulation transmitter with a harmonic suppression switched capacitor power amplifier. The transmitter comprises a sixteen-phase delay locked loop, a binary frequency shift keying modulator and the harmonic suppression switched capacitor power amplifier. The sixteen-phase delay locked loop provides sixteen paths of clock signals with equal phase difference to the binary frequency shift keying modulator, and the sixteen paths of clock signals are used as input signals of the binary frequency shift keying modulator; the binary frequency shift keying modulator is connected with the harmonic suppression switched capacitor power amplifier and provides a modulation signal for the harmonic suppression switched capacitor power amplifier; and the harmonic suppression switched capacitor power amplifier is used for amplifying the modulation signal and suppressing a harmonic component so as to output the modulation signal after harmonic suppression. According to the invention, high data rate transmission can be supported, the higher harmonic suppression capability is provided, the design requirement of a matching network can be relaxed while the frequency spectrum purity is ensured, the chip area is reduced, and the system cost is reduced.

The application discloses a double mixed inhibition type phase-locked loop method based on a generalized second-order integrator, and belongs to the technical field of grid-connected control. The method proposes a double mixed inhibition type second-order generalized integrator phase-locked loop, which can realize double inhibition of low-order harmonic and direct current offset of a power grid. The method adds a harmonic extraction branch on a traditional SOGI structure, and based on a pure harmonic signal output by the branch, the pure harmonic signal is subtracted from an in-phase branch output to generate a signal with higher harmonic suppression capability, so that low-order harmonic interference is significantly weakened. For the problem of direct current offset, the method introduces a high-pass filter and combines a phase compensation link, utilizes signal components in a two-phase rotating coordinate system and an output frequency of the phase-locked loop to perform real-time feedback correction, and thus eliminates the direct current offset and dynamically corrects fundamental phase error. The method has obvious advantages in steady-state accuracy and dynamic response, and can provide reliable synchronization technology support for renewable energy grid connection.

This invention relates to the technical field of carbon metering modules, and in particular to a high-precision carbon metering module, comprising an energy metering unit, a dynamic carbon emission factor processing unit, a microprocessor and control unit, a carbon metering algorithm module, and a display and output unit. The energy metering unit includes a sampling circuit and a digital filtering submodule. The sampling circuit adopts a multi-channel synchronous sampling architecture. The digital filtering submodule has a built-in harmonic suppression algorithm to suppress harmonic interference under nonlinear loads, ensuring metering accuracy under all operating conditions. The energy metering unit is directly connected to the AC power supply circuit under test, used to collect voltage and current signals in the circuit in real time, calculate and output instantaneous active power and cumulative energy data. It solves the problem from three dimensions: improving the accuracy of front-end energy metering, adapting the core dynamic carbon emission factor, and optimizing the carbon metering algorithm, to achieve real-time, high-precision, and traceable metering of carbon emissions on the electricity consumption side, while improving environmental adaptability and functional expandability.

The invention discloses a converter harmonic suppression method and system based on a generative adversarial network, and the method comprises the steps: obtaining a real-time sampled power grid current, and predicting an independent harmonic component vector and an inter-harmonic component vector through the specific architecture of the generative adversarial network, therefore, the technical problem that different periodic components are difficult to accurately distinguish and predict in parallel in a traditional method is solved, on this basis, compensation mode self-adaptive instruction synthesis is performed based on compensation mode setting, and a saturation detection and priority dynamic current redistribution mechanism is introduced to generate an instantaneous compensation current instruction. According to the method, high-efficiency and flexible compensation can still be realized when the capacity of the converter is limited, and finally, precise suppression of harmonic waves and inter-harmonic waves is realized through current closed-loop control and PWM driving signal generation. Through the mode, the limitation of an existing GAN model on harmonic and inter-harmonic separation and compensation instruction generation is effectively solved, and the prediction precision and the adaptability of a compensation strategy are improved.

A delay-locked loop (DLL) is provided that ensures that the phase outputs that are provided as inputs to the harmonic rejection mixer (HRM) are sufficiently accurate to allow the HRM to effectively cancel out the spurious harmonic frequencies, thereby improving HRM parameters. The phase detector of the DLL can be programmable to provide a “knob” that can be used post layout to adjust the output phase differences of the DLL to make them more precise. This feature overcomes issues with mismatches in silicon that in the past have affected the ability of the DLL to settle precisely to the desired phases. This, in turn, loosens design and manufacturing constraints that are currently employed to ensure that the DLLs settle precisely to the desired phases. Additionally, logic gates are eliminated from the phase detector and replaced with resistors to reduce current consumption and further looser design and manufacturing constraints.

The present disclosure relates to an amplifier arrangement (1, 100, 200) comprising a first amplifier device (2, 102, 202) and a second amplifier device (3, 103, 203) where each amplifier device (2, 3; 102, 103; 202, 203) is connected to an input circuit (8, 108) and has a first type output terminal (4, 6; D) and a second type output terminal (5, 7; S), where the output terminals (4, 6, D; 5, 7, S) are connected to an output circuit (9, 109, 109′). The first type output terminal (4, D) of the first amplifier device (2, 102, 202) is connected to the second type output terminal (7, S) of the second amplifier device (3, 103, 203) by means of a first connection (10, 110), and the first type output terminal (6, D) of the second amplifier device (3, 103, 203) is connected to the second type output terminal (5, S) of the first amplifier device (2, 102, 202) by means of a second connection (11, 111). The first type output terminal (4, D) of the first amplifier device (2, 102, 202) and the first type output terminal (6, D) of the second amplifier device (3, 103, 203) are electrically separated in the output circuit (9, 109, 109′), and the second type output terminal (5, S) of the first amplifier device (2, 102, 202) second type output terminal (7, S) of the second amplifier device (3, 103, 203) are electrically separated in the output circuit (9, 109, 109′).

The invention discloses a filter for improving far-end suppression based on a thin-film interdigital structure, and the filter is characterized in that an even number of frequency strips which are symmetrically arranged left and right are formed on a circuit surface, each frequency strip is provided with a resonance through hole, and the resonance through holes in the two adjacent frequency strips at the same side are located at the upper and lower different ends; the middle portions of the opposite sides of the frequency strips on the leftmost side and the rightmost side are connected to a left port and a right port through a left micro-band line and a right micro-band line respectively, the left micro-band line and the right micro-band line are symmetrically arranged, the left micro-band line and the right micro-band line form one or more turning lines, the turning lines protrude upwards / downwards / leftwards / rightwards, and the turning lines are connected with the left port and the right port respectively. Under the condition that a low-pass filter is not added, through adjusting the inflection lines of the left micro-strip line and the right micro-strip line and then finely tuning frequency coupling, the suppression degree with small harmonic position span is satisfied. According to the invention, the required harmonic suppression degree can be improved, and an additional low-pass filter is omitted.

The invention discloses a higher harmonic suppression method and system, which is applied to the technical field of direct current transmission, and comprises the following steps: obtaining three-phase current data of an LCC converter; performing error analysis processing on the three-phase current data and a preset current instruction value to obtain three-phase harmonic error current data; based on the three-phase harmonic error current data, performing compensation deviation processing on the obtained output current data of the MMC converter to obtain three-phase harmonic compensation current data; after coordinate transformation, a PI controller is adopted to superpose a repetitive controller to obtain output after harmonic suppression; and modulating to generate a control waveform of the MMC converter, thereby realizing harmonic suppression of the SLCC circuit. The core of the method is to introduce a power grid strength adaptive strategy: a harmonic suppression mode is automatically switched according to a power grid strength grade, and adaptive modification of parameters of a repetitive controller is realized. According to the method, unified suppression of full-higher harmonics under power grid working conditions with different intensities is realized.

This disclosure provides systems, methods, and devices for wireless communications that support downconversion of signals with improved harmonic rejection. In a first aspect, an apparatus includes a first plurality of mixers with each mixer coupled to two oscillating signals that are 180 degrees apart in phase; a second plurality of mixers with each mixer coupled to two oscillating signals that are 180 degrees apart in phase, wherein a combined load of the first plurality of mixers and the second plurality of mixers on the plurality of oscillating signals is symmetric as to each oscillating signal of the plurality of oscillating signals; and a shared capacitor coupling the RF input to the first plurality of mixers and the second plurality of mixers. Other aspects and features are also claimed and described.

The invention provides a harmonic suppression circuit, a performance test method and industrial equipment, and relates to the technical field of radio frequency. The harmonic suppression circuit comprises a CLC filter circuit, an LC filter circuit and an absorption type resonance branch circuit which are cascaded in sequence; the CLC filter circuit comprises a first capacitor, a first inductor and a second capacitor which are electrically connected in sequence; one ends of the first capacitor and the second capacitor away from the first inductor are respectively grounded; the LC filter circuit comprises a second inductor and a third capacitor which are electrically connected; one end of the second inductor far away from the third capacitor is connected between the first inductor and the second capacitor; one end of the third capacitor far away from the second inductor is grounded; the absorption resonance branch is configured to present low impedance in a target harmonic frequency band; one end of the absorption resonance branch is connected between the second inductor and the third capacitor, and the other end is grounded. Based on the harmonic suppression circuit, harmonic waves can be effectively suppressed and prevented from interfering operation of related equipment.

High linearity harmonic rejection mixers are disclosed herein. In certain embodiments, a mixer operates to mix a signal received at an input with a local oscillator signal from a local oscillator. The mixer includes a plurality of in-phase (I) signal paths and a plurality of quadrature-phase (Q) signals paths that are selectively activated by a plurality of clock signal phases of the local oscillator signal. For example, each clock signal phase selects a corresponding I signal path and Q signal path that are active for that clock signal phase. The mixer is implemented such that a total absolute current of the I signal path and the Q signal path is substantially constant for each of the clock signal phases.

A radio frequency (RF) receiver is described, the RF receiver comprising: a plurality of analog mixing circuits including circuits for down-converting an input RF signal; a plurality of analog combining and scaling circuits operably connected to the analog mixing circuits and for generating a plurality of intermediate signals; a digital combining and scaling circuit operably connected to the analog combining and scaling circuits, the digital combining and scaling circuit comprising: in-phase signal component (I) circuitry for performing a first combining and scaling operation on a set of two or more of the plurality of intermediate signals to generate an in-phase signal component of a baseband signal; quadrature phase signal component (Q) circuitry for performing a second combining and scaling operation on another set of two or more of the plurality of intermediate signals to generate a quadrature phase signal component (Q) of the baseband signal.

This invention belongs to the field of microwave antenna and RF front-end circuit technology, specifically relating to a broadband filter dielectric resonator antenna with wide harmonic suppression characteristics and a method for controlling its radiation characteristics. The method includes the following steps: obtaining an initial electromagnetic state parameter set and performing fundamental mode field distribution decoupling calculations; constructing an open-loop feeder partially coupled topology to generate a hybrid broadband response signal set; parsing the passband envelope and attenuation determination to map a folded open-loop resonator to generate lower stopband zeros; determining the harmonic frequency band energy density threshold to trigger a multi-topology notch filter to generate an upper stopband zero array; and compensating for phase group delay and gain flatness to output the converged final radiation state parameters of the antenna. This invention overcomes the problems of multimode interference between the feed network and the radiator, the inability to independently generate stopband radiation zeros, and nonlinear phase group delay shift caused by the lack of distributed notch filter node cooperative configuration.

The invention discloses an output current harmonic suppression method, device, equipment and medium for a network construction type charging pile, and the method comprises the steps: obtaining an output current signal of the network construction type charging pile, and extracting a corresponding harmonic current component from the output current signal according to a preset number of times; based on the harmonic current component, respectively determining a first harmonic suppression compensation signal and a second harmonic suppression compensation signal, the first harmonic suppression compensation signal being a compensation signal obtained by combining the harmonic current component with impedance calculation, the second harmonic suppression compensation signal is a compensation signal calculated by combining the harmonic current component with the quasi-proportional resonance controller; and the first harmonic suppression compensation signal and the second harmonic suppression compensation signal are utilized to suppress the current of the control output end of the current loop of the network-forming type charging pile, and an output suppression signal is obtained. Compensation suppression is carried out through the two harmonic suppression compensation signals, the range of compensation suppression can be widened, and the suppression effect is improved.

The invention discloses an ultra-wideband high-harmonic suppression power amplifier, which comprises a low-frequency power amplification branch, a high-frequency power amplification branch and a harmonic suppression matching network, and is characterized in that the harmonic suppression matching network comprises a low-frequency harmonic suppression matching network, a high-frequency harmonic suppression matching network and a common output end; the low-frequency power amplification branch and the high-frequency power amplification branch respectively amplify power of low-frequency band signals and high-frequency band signals with different frequencies in a working broadband, and the low-frequency harmonic suppression matching network and the high-frequency harmonic suppression matching network respectively carry out impedance matching on fundamental waves in the low-frequency band signals and the high-frequency band signals after power amplification. And meanwhile, secondary and third harmonic signals are suppressed. The problems that in the prior art, a power amplifier is low in power generation efficiency and poor in higher harmonic suppression degree are solved.

The invention discloses an intelligent cooperative harmonic suppression method and related equipment, and the method comprises the steps: obtaining a voltage signal and a current signal, and carrying out the preprocessing, and obtaining the preprocessing data; performing spectrum analysis on the preprocessed data to obtain spectrum data of a plurality of harmonic waves; based on the frequency spectrum data, determining governance weights corresponding to the passive filtering unit, the active filtering unit and the reactor unit respectively; and based on the governance weight, respectively adjusting a capacitance parameter of the passive filter unit, a compensation current parameter of the active filter unit and an impedance parameter of the reactor unit. According to the invention, harmonic wave coverage in a wide frequency range is realized through an intelligent adaptive filtering mode, load fluctuation and power grid frequency deviation are adapted, the harmonic wave treatment effect is more stable, the defects of a traditional harmonic wave treatment technology in coverage range, scene adaptability and volume cost are overcome, and harmonic wave treatment requirements of different scenes can be met.

The invention provides a DC charging pile harmonic wave self-compensation control method and system, and the method and system comprise the steps: signal collection and preprocessing, harmonic wave detection and feature extraction, harmonic wave compensation strategy making, harmonic wave compensation execution, and system optimization and maintenance. According to the DC charging pile harmonic self-compensation control method and system provided by the invention, a dynamic self-adaptive harmonic compensation strategy is adopted, the compensation signal can be dynamically generated according to the difference value between the harmonic current and the limit, the response time of the compensation device is shortened, and the response time is shortened compared with that of a traditional active filter; the problems of two core pain points, insufficient compensation real-time performance and poor dynamic working condition adaptability in harmonic suppression are solved, the harmonic current change can be rapidly tracked, it is ensured that the compensation current and the harmonic current are equal in size and opposite in phase all the time, the harmonic suppression rate is high, the common connection point is stable, and the power grid stability is high. And the large-scale power failure risk caused by resonance is avoided.