60results about How to "Reduce bias current" patented technology

The invention relates to an electronic device and a method for DC-DC conversion using a comparator for generating an output signal for driving a power switch of a switch mode DC-DC converter. The electronic device is configured to reduce a bias current of the comparator with a first slope in response to a decreasing load and to increase the bias current of the comparator with a second slope in response to an increasing load, wherein the second slope is steeper than the first slope.

The invention provides a voltage comparator, which comprises a current source, a differential gain module and a conversion module, wherein the current magnitude of the current source is of nanoampere level; the differential gain module comprises a first transistor, a second transistor, a third transistor and a fourth transistor; the first transistor and the second transistor are connected with the current source respectively; the third transistor and the fourth transistor form a current mirror structure; the third transistor is connected with the first transistor; and the fourth transistor is connected with the second transistor through a ninth transistor for forming asymmetric differential gain. According to the voltage comparator provided by the invention, since the transistor which works in a sub-threshold region has higher transconductance-to-current ratio Gm / Ib than the transistor which works in a saturation region, the power consumption is lower; and in order to reduce the power consumption, the bias current in the voltage comparator provided by the embodiment is low, and the time delay of the voltage comparator is also low.

Provided is a voltage regulator having improved transient response characteristics even when a load current is switched from a light load to a heavy load. The voltage regulator includes, to a gate of a detection transistor constituting an output current detection circuit: a resistive element for interrupting the gate of the detection transistor from an output terminal of a differential amplifier circuit in an AC manner; and a capacitive element connected to an output terminal of the voltage regulator in an AC manner.

The invention discloses a tera-hertz silica-based quadrupler and a frequency multiplier, belonging to the field of RFIC (Radio Frequency Integrated Circuit). The quadrupler comprises transistors (M1 and M2) and transmission lines (L1, L2 and L-1), wherein the drain ends of the transistors (M1 and M2) are respectively connected to an output port through the transmission lines (L1 and L2), source ends are connected with a ground line, grid ends are respectively connected with the signal input ends of an path (I) and the path (Q) of a baseband signal (f0); the transmission line (L-1) is connected between the output port and a power supply; and the length of the transmission lines (L1 and L2) are 1 / 4 of that of the corresponding wavelength of a signal (2f0), the length of the transmission line (L-1) is 1 / 4 of that of the corresponding wavelength of a signal (4f0). The multi-frequency multiplier comprises a 2n frequency multiplier (1), a 2n frequency multiplier (2) and a transmission line (L), wherein the output ports of the 2n frequency multiplier (1) and the 2n frequency multiplier (2) are connected to be used as the output port of a 2n+1 frequency multiplier, the transmission line (L) is connected between the output port of the 2n+1 frequency multiplier and the power supply, and the length of the transmission line (L) is 1 / 4 of that of the corresponding wavelength of a signal (2n+1f0). The tera-hertz silica-based quadrupler and the multi-frequency multiplier, provided by invention, have the advantages of high output frequency, pure frequency spectrum, low power consumption and easiness for integration.

A mixer circuit of a receiving system, requiring low noise characteristics at lower frequency, includes a bypass current source (41) which is connected in parallel with an LO transistor (21) between an IF output terminal (33) and a drain terminal of an RF transistor (11), and a bypass current source (42) which is connected in parallel with an LO transistor (22) between an IF output terminal (34) and the drain terminal of the RF transistor (11), thereby decreasing a current flowing through the LO transistors (21, 22) without decreasing a bias current flowing through the RF transistor (11). Accordingly, it is possible to suppress flicker noises occurring from the LO transistors (21, 22) without lowering the gain of the mixer, thereby realizing a mixer circuit with excellent low frequency noise characteristics, which can improve the NF characteristics at lower frequency.

An amplifier circuit including a CMOS inverter circuit that eliminates a DC offset caused by variations in characteristics of elements in each manufacturing process and is thus applicable to analog signal processing. The CMOS inverter circuit including a PMOS transistor (11), an NMOS transistor (12), and the like is provided with an NMOS transistor (13) connected to the NMOS transistor (12) to increase a source voltage of the NMOS transistor (12) and DC offset detecting means for detecting a DC offset and applying a voltage adjusted so as to reduce the DC offset to a gate of the NMOS transistor (13).

The invention provides a voltage supply circuit used for supplying voltage to a memory unit. The memory unit comprises a voltage input end. The voltage supply circuit comprises a first voltage regulator, a second voltage regulator and a control unit, wherein the first voltage regulator is used for regulating reference voltage to generate working voltage when the memory unit works and stops working when the memory unit does not work; the second voltage regulator is used for regulating the reference voltage to generate standby voltage; and the control unit is used for controlling the voltage input end to receive the working voltage after the memory unit works for a preset time, or receiving the standby voltage. The voltage supply circuit has the following advantage: the problem of slow response of the memory unit caused by delay of the voltage regulators is avoided.

The invention discloses an on-chip RC oscillator circuit, which belongs to the technical field of integrated circuits. The on-chip RC oscillator circuit includes a low power consumption temperature compensation circuit, a charge and discharge control circuit, a comparator circuit, an RS flip-flop and a buffer. In the low power consumption stable compensation circuit, the first NMOS transistor, the first PMOS transistor, the fourth PMOS transistor, the third resistor and the second NMOS transistor constitute a circuit that generates a bias current with a negative temperature coefficient; the second NMOS transistor, the second PMOS transistor The tube, the third PMOS tube, the third NMOS tube, and the second resistor form a loop that generates a positive temperature coefficient current; the two loops are connected through the second NMOS tube to achieve negative feedback, and the first capacitor and the first resistor are connected to the negative feedback loop. Le compensation improves stability, only four current branches are required to realize the positive and negative temperature coefficient current structure required for temperature compensation, and the power consumption is reduced; the first NMOS tube, the second NMOS tube, and the third NMOS tube work at sub-threshold The region realizes smaller bias current and lower power consumption.