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59results about How to "Reduce bias current" patented technology

Tera-hertz silica-based quadrupler and frequency multiplier

The invention discloses a tera-hertz silica-based quadrupler and a frequency multiplier, belonging to the field of RFIC (Radio Frequency Integrated Circuit). The quadrupler comprises transistors (M1 and M2) and transmission lines (L1, L2 and L-1), wherein the drain ends of the transistors (M1 and M2) are respectively connected to an output port through the transmission lines (L1 and L2), source ends are connected with a ground line, grid ends are respectively connected with the signal input ends of an path (I) and the path (Q) of a baseband signal (f0); the transmission line (L-1) is connected between the output port and a power supply; and the length of the transmission lines (L1 and L2) are 1/4 of that of the corresponding wavelength of a signal (2f0), the length of the transmission line (L-1) is 1/4 of that of the corresponding wavelength of a signal (4f0). The multi-frequency multiplier comprises a 2n frequency multiplier (1), a 2n frequency multiplier (2) and a transmission line (L), wherein the output ports of the 2n frequency multiplier (1) and the 2n frequency multiplier (2) are connected to be used as the output port of a 2n+1 frequency multiplier, the transmission line (L) is connected between the output port of the 2n+1 frequency multiplier and the power supply, and the length of the transmission line (L) is 1/4 of that of the corresponding wavelength of a signal (2n+1f0). The tera-hertz silica-based quadrupler and the multi-frequency multiplier, provided by invention, have the advantages of high output frequency, pure frequency spectrum, low power consumption and easiness for integration.
Owner:PEKING UNIV

Tera-hertz silica-based quadrupler and frequency multiplier

The invention discloses a tera-hertz silica-based quadrupler and a frequency multiplier, belonging to the field of RFIC (Radio Frequency Integrated Circuit). The quadrupler comprises transistors (M1 and M2) and transmission lines (L1, L2 and L-1), wherein the drain ends of the transistors (M1 and M2) are respectively connected to an output port through the transmission lines (L1 and L2), source ends are connected with a ground line, grid ends are respectively connected with the signal input ends of an path (I) and the path (Q) of a baseband signal (f0); the transmission line (L-1) is connected between the output port and a power supply; and the length of the transmission lines (L1 and L2) are 1 / 4 of that of the corresponding wavelength of a signal (2f0), the length of the transmission line (L-1) is 1 / 4 of that of the corresponding wavelength of a signal (4f0). The multi-frequency multiplier comprises a 2n frequency multiplier (1), a 2n frequency multiplier (2) and a transmission line (L), wherein the output ports of the 2n frequency multiplier (1) and the 2n frequency multiplier (2) are connected to be used as the output port of a 2n+1 frequency multiplier, the transmission line (L) is connected between the output port of the 2n+1 frequency multiplier and the power supply, and the length of the transmission line (L) is 1 / 4 of that of the corresponding wavelength of a signal (2n+1f0). The tera-hertz silica-based quadrupler and the multi-frequency multiplier, provided by invention, have the advantages of high output frequency, pure frequency spectrum, low power consumption and easiness for integration.
Owner:PEKING UNIV

On-chip RC oscillator circuit

The invention discloses an on-chip RC oscillator circuit, and belongs to the technical field of integrated circuits. The on-chip RC oscillator circuit includes a low-power-consumption temperature compensation circuit, a charge and discharge control circuit, a comparator circuit, an RS flip flop, and a buffer. A first NMOS transistor, a first PMOS transistor, a fourth PMOS transistor, a third resistor and a second NMOS transistor in the low-power-consumption temperature compensation circuit form a loop for generating a bias current with a negative temperature coefficient. A second NMOS transistor, a second PMOS tube, a third PMOS transistor, a third NMOS transistor and a second resistor form a loop that generates a positive temperature coefficient current. The two loops implement a negativefeedback connection through the second NMOS transistor, and the first capacitor and the first resistor perform the miller compensation for a negative feedback loop to improve stability. The oscillator circuit only needs four current branches, and the positive and negative temperature coefficient current structure required for temperature compensation is very simple, and the power consumption is low. The first NMOS transistor, the second NMOS transistor and the third NMOS transistor operate at a sub-threshold section, achieving a smaller bias current and consuming less power.
Owner:CHINA KEY SYST & INTEGRATED CIRCUIT

An on-chip rc oscillator circuit

The invention discloses an on-chip RC oscillator circuit, which belongs to the technical field of integrated circuits. The on-chip RC oscillator circuit includes a low power consumption temperature compensation circuit, a charge and discharge control circuit, a comparator circuit, an RS flip-flop and a buffer. In the low power consumption stable compensation circuit, the first NMOS transistor, the first PMOS transistor, the fourth PMOS transistor, the third resistor and the second NMOS transistor constitute a circuit that generates a bias current with a negative temperature coefficient; the second NMOS transistor, the second PMOS transistor The tube, the third PMOS tube, the third NMOS tube, and the second resistor form a loop that generates a positive temperature coefficient current; the two loops are connected through the second NMOS tube to achieve negative feedback, and the first capacitor and the first resistor are connected to the negative feedback loop. Le compensation improves stability, only four current branches are required to realize the positive and negative temperature coefficient current structure required for temperature compensation, and the power consumption is reduced; the first NMOS tube, the second NMOS tube, and the third NMOS tube work at sub-threshold The region realizes smaller bias current and lower power consumption.
Owner:CHINA KEY SYST & INTEGRATED CIRCUIT
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