Matching detection method and circuit of content addressable memory cell
A technology for addressing memory and storage units, applied in static memory, digital memory information, information storage, etc., can solve the problems of large power consumption, consumption, waste of matching signal lines, etc., to reduce current consumption, reduce current consumption, reduce The effect of bias voltage and bias current
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[0026] Specific embodiments of the present invention will be described in more detail below with reference to the accompanying drawings, Image 6 is a block diagram of an embodiment of the present invention or a non-memory cell matching detection circuit, Figure 7 Schematic diagram of yes or no memory cell matching detection circuit. Such as Image 6 As shown, the OR non-memory cell matching detection circuit includes: a pre-charge circuit, a charging circuit, a feedback control circuit, an equalization circuit, an OR non-memory cell, a sensitive amplifier (SA), a power supply and ground, wherein, the number of OR non-memory cells is greater than 1. The first matching signal line MLA and the second matching line signal MLB are formed by parallel connection of several NOR memory cells (hereinafter referred to as matching signal line MLA and matching line signal MLB).
[0027] Such as Figure 7 As shown, the circuit transistors N1, N2, N3, N4, N5 and the OR non-memory cells ...
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