14 results about "Load pull" patented technology

The invention relates to a manufacturing method of a power amplifier for improving power back-off efficiency, which belongs to the technical field of radio frequency microwave circuits, and comprises the following steps: step 1, based on load characteristics of an active device, determining an optimal efficiency impedance point under linear output power as optimal impedance of amplifier design; step 2, pulling out the determined optimal impedance by using a load pulling technology or LOADPULL, and drawing the optimal impedance on an SMITH original drawing; 3, based on the optimal impedance obtained through traction, low-loss impedance matching is achieved through the equal Q matching technology, loss and bandwidth are compatible, and impedance change and frequency band shaping are completed; 4, a two-stage or multi-stage amplification structure is adopted, and nonlinear compensation is realized by controlling grid voltages of front-stage and back-stage active devices and utilizing front-stage and back-stage gain compression and expansion characteristics; the method has the beneficial effects that the linear output power optimal efficiency impedance point is selected as the optimal impedance of the amplifier design, and the amplifier maintains higher linear output power and has higher rollback efficiency.

The utility model discloses a dynamic difference loading circuit, which relates to the technical field of direct current control circuits and comprises a digital-to-analog conversion circuit, a comparison circuit, a starting circuit and a metal oxide semiconductor (MOS) tube control circuit, one end of the digital-to-analog conversion circuit is connected with the comparison circuit, one end of the comparison circuit is connected with the starting circuit, and one end of the starting circuit is connected with the MOS tube control circuit. According to the utility model, the structure is scientific and novel, the digital-to-analog conversion circuit, the comparison circuit, the starting circuit and the MOS tube control circuit are utilized, the current firstly flows through the comparison circuit, the starting circuit controls the starting and stopping of an instrument, the MOS tube control circuit controls the actual flowing value of the current after starting, and finally the current returns to the comparison circuit to form continuously-controlled dynamic balance, so that the dynamic balance is realized. And the on-off degree of the MOS tube is controlled by amplifying the voltage difference through the comparison circuit, so that the MOS tube is always in a dynamic working state, thereby ensuring that the load pulling current is maintained in a dynamic balance state.

Triple band remotely configurable tuning probes for slide screw impedance tuners allow instantaneous larger frequency coverage beyond the capacity of existing tuning probes using the single horizontal and vertical axis mechanism of a prior art single probe, single band tuner. This is done by combining two types of tuning slug, a core slug and a saddle slug into a configurable tuning probe assembly mounted in the same mobile tuner carriage and controlled using the same single vertical axis mechanism with the help of two ridges on the core slug and a permanently mounted slug control fork. To avoid spurious resonance phenomena the tuning slugs are controlled, driven, and locked vertically sliding on each other, and guided appropriately allowing smooth, uninhibited vertical movement of the metallic bodies.

This invention relates to a power amplifier design method and a power amplifier. The power amplifier design method includes the following steps: performing load pull simulation on the target power amplifier to obtain the input and output impedances of the transistors; designing a bias circuit; designing an input matching network and an output matching network based on the input and output impedances of the transistors; optimizing the input and output matching networks using small-signal S-parameter simulation to obtain optimized input and output matching networks; and substituting the optimized input and output matching networks into the input and output terminals of the transistors to obtain the circuit structure of the target power amplifier. This invention obtains ideal large-signal simulation results for the power amplifier simply by optimizing the input and output matching networks using small-signal S-parameters, greatly improving the design efficiency of the power amplifier.

The present invention discloses a power amplifier design method based on Bayesian optimization with feasible domain shrinkage. This method first determines the matching network target impedance based on load pull and source pull. It then determines the matching network structure and component parameter values ​​using the Chebyshev low-pass topology method. Initial values ​​are sampled using optimal Latin hypercube sampling to obtain an input sample set. Sample point evaluation is performed using a normalized weighted approach. A particle swarm algorithm is used to search for optimal hyperparameters. Based on a trained Gaussian process model, the acquisition function (UCB) is maximized within the feasible domain to obtain the next evaluation point. This method continuously iterates to achieve a broadband, high-efficiency power amplifier. This invention proposes, for the first time, a power amplifier design method based on Bayesian optimization with feasible domain shrinkage. By dynamically changing the parameter value β to shrink the feasible domain, this method achieves a balance between global and local optimization, accelerates convergence, and effectively guides power amplifier layout optimization, ultimately achieving power amplifier design.

The invention provides an OIP3 parameter on-chip test method and device, and the method comprises the steps: predefining an impedance tuning region on a Smith chart, and predefining N target impedance points in the impedance tuning region, N being a natural number greater than 1; and exciting the tested device to carry out intermodulation distortion test through the dual-tone signal, and sequentially tuning the load impedance of the tested device to each target impedance point through load traction. According to the OIP3 parameter on-chip test method and test device provided by the invention, the problems that a traditional OIP3 test scheme cannot reflect the nonlinear characteristic change of a device caused by impedance mismatch in an actual working environment, the test result is influenced by parasitic parameters introduced by packaging and the like are solved.

A power amplifier (100) for reducing a load pull ratio includes at least three amplifiers that receive a first signal (S1), a second signal (S2), and a third signal (S3), respectively. The power amplifier (100) further comprises a circulator (140) comprising: an input port (142) connected to the output (116) of the first amplifier (110) and the output (124) of the second amplifier (120) and configured to: receive the first amplified signal (A1) and the second amplified signal (A2) and provide the first amplified signal (A1) and the second amplified signal (A2) to a load (150) through an output port (144) of the circulator (140); and an isolation port (146) connected to the output (134) of the third amplifier (130) and configured to receive the third amplified signal (A3) and provide the third amplified signal (A3) to the load (150) through the output port (144) of the circulator (140).

A universal load pull tuner for on wafer load pull and noise measurements is connected directly to the wafer-probe to minimize insertion loss and maximize the tuning range; it incorporates a suspended tuning module and an automated anti-tilting balancing mechanism with manual wafer tip planarization capability, all in a solid housing. The tuning module includes up to three mobile carriages and wideband tuning probes controlling independently impedances for up to three harmonic frequencies. The tuner is mountable under an angle matching the slope of the wafer probes and only requires a simple three axis positioner, without customized accessories, to operate.

An on-wafer load pull tuner system includes an intelligent, universal, remotely controlled, mechanical wafer-probe contact controlling device, supporting automatic microwave single or multi-probe balanced slide screw tuners. It allows contacting and stable on-wafer testing of sub-micrometric devices. Ultra-low loss rigid airlines (bend-lines) used to connect the tuner with the semiconductor chips, in order to improve the tuning range at the DUT reference plane, transfer mechanical contact control movements of the wafer probes attached to the rigid bend-lines, when a counterweight tilts the tuner assembly by controlling the center of gravity of the assembly.

The invention relates to a cold start method and device of a fuel cell and a vehicle, and relates to the technical field of vehicles, the method comprises the steps that the load pulling mode of cold start of the fuel cell is determined based on the cooling liquid inlet temperature and the cooling liquid outlet temperature of the fuel cell, and the load pulling mode comprises constant-pressure load pulling and constant-current load pulling; determining a ratio interval of the target ratio based on the load pulling mode; wherein the target ratio is the ratio of the heat absorption capacity and the heat productivity of the stack core in the fuel cell in unit time; determining a target cooling liquid flow interval based on the ratio interval and the heating power of the fuel cell in the load pulling mode; and performing cold start control on the fuel cell based on the target cooling liquid flow interval so as to improve the cold start efficiency of the fuel cell.

This invention discloses a full-process modeling method and system for microwave compound semiconductor devices, belonging to the field of microwave electronic device technology. The method includes six steps: device model creation, measured data import, small-signal model parameter extraction, nonlinear current model parameter extraction, nonlinear capacitance model parameter extraction, and global model verification. It achieves one-stop parameter extraction covering the entire process, integrating analytical and optimization algorithms to improve parameter accuracy. Global verification is performed across five dimensions: multi-bias S-parameters, current characteristics, capacitance characteristics, power sweep characteristics, and load pull circle diagram. Combined with commercial microwave simulation software, a directly loadable Verilog A model is output. This invention solves the problems of disjointed processes and insufficient verification dimensions in existing technologies, improving modeling efficiency and accuracy, and providing precise model support for high-frequency, high-power electronic devices.

The application relates to a power amplifier manufacturing method for improving power backoff efficiency, and belongs to the technical field of radio frequency microwave circuits, and comprises the following steps: step 1: based on the load characteristics of an active device, the optimal efficiency impedance point under linear output power is determined as the optimal impedance of amplifier design; step 2: the determined optimal impedance is pulled out by using a load pulling technology or LOADPULL, and is drawn on a SMITH chart; step 3: based on the optimal impedance obtained by pulling, an equal Q matching technology is adopted to realize low-loss impedance matching, compatibility of loss and bandwidth, impedance variation and frequency band shaping are completed; step 4: a two-stage or multi-stage cascade amplification structure is adopted, the gate voltages of front and rear active devices are controlled, and nonlinear compensation is realized by using gain compression and expansion characteristics of the front and rear stages; the application has the beneficial effects that the optimal efficiency impedance point under linear output power is selected as the optimal impedance of amplifier design, the amplifier maintains higher linear output power, and has higher backoff efficiency.

An improved pre-matched active modulated tuner is used for hybrid load pull testing microwave transistors subject to modulated signal stimulus. A modulation pattern correction method uses calibration data of a pre-matching passive slide screw tuner to modify the data management of the numeric processor of the active tuner and allows lower power requirement of the active tuner and precise target tuning using optimization with a realistic starting point.

A computer-implemented method of determining linearity of a power amplifier module (PAM) in load pull measurements includes: receiving an input dataset including a plurality of load pull parameters; processing, by a neural network, the input dataset including the plurality of load pull parameters; and; producing an output dataset including a linearity of the PAM