The invention discloses a
memory chip 3D stacking packaging structure and a packaging process thereof, and relates to the field of semiconductors. The invention relates to a
memory chip 3D stacking packaging structure and a packaging technology thereof, the
memory chip 3D stacking packaging structure comprises a
DBC substrate and
integrated circuit chips integrated on the
DBC substrate, the
integrated circuit chips are stacked, and the memory
chip 3D stacking packaging structure also comprises a packaging structure installed on the outer side of the
DBC substrate; the packaging structure comprises a packaging shell which covers the outer side of the DBC substrate, and a packaging cover which covers the outer side of the DBC substrate, a group of cooling fins are mounted on the outer wall of each
integrated circuit chip, and a plurality of cooling fins are arranged in each group and are distributed in a
vertical array; slots are formed in the corners of each group of cooling fins, heat conduction
insertion blocks are inserted into the inner walls of the slots, and the cooling fins in the same group are connected in series through the heat conduction
insertion blocks; according to the invention, accumulated heat of the integrated circuit
chip is led out through the cooling fin, then is conducted to the heat gathering frame through the heat conduction
insertion block, and then is gathered to the cooling plate through the heat gathering frame to be led out, so that external gas exchanges heat with the integrated circuit chip conveniently to cool the integrated circuit chip.