28 results about "DBc" patented technology

The invention discloses a radio frequency chip heat effect compensation system and method based on multi-physics field coupling, the system comprises a radio frequency chip body, a multi-physics field coupling calculation module, a temperature sensor array and a dynamic compensation algorithm module, and the method comprises the following steps: evaluating frequency deviation caused by a heat effect; collecting multi-point temperature data and converting the multi-point temperature data into frequency drift data; regional temperature regulation and control are executed through a temperature control array, and frequency drift is eliminated. The compensation effect is evaluated in real time, and compensation parameters are dynamically optimized. According to the invention, predictive compensation of frequency drift is realized, the compensation precision is improved by 2-3 times, and the response speed is improved by 5-10 times; the system has self-adaption and self-learning capabilities and can adapt to rapid temperature change as high as 0.5 DEG C / s, and the technical breakthrough that the system is more and more accurate is realized; while the performance is greatly improved, the frequency stability reaches 10 <-8 > magnitude, the phase noise is reduced by 12 dBc / Hz, the power is saved by more than 80%, the area is increased by less than 2 mm < 2 >, and the technical contradiction of high performance and inevitable high power consumption is solved.

The invention discloses a bit-level CAN (Controller Area Network) data load reversing method and device based on hierarchical clustering. The method comprises the following steps: acquiring original CAN message data in a vehicle running process through a CAN data acquisition tool, and processing the CAN message data by utilizing a frequency matrix, a probability matrix, a bit flipping rate and a hierarchical clustering method to obtain CAN message signal characteristics; performing reverse analysis on the CAN message signal by analyzing the characteristics of the CAN message signal and combining the signal type of the automobile to obtain a reverse analysis result; and controlling the functions of the automobile based on the reverse analysis result. According to the method and the device, the problem of dependence on special equipment and a database (DBC file) private by a manufacturer in the prior art is solved, and the technical problem of more accurate and finer-grained signal automatic reverse analysis is realized.

The invention provides a pre-distortion counteracting and secondary counteracting power amplification circuit, which is characterized in that an input signal is divided into two paths, one path generates a supporting pre-distortion signal through a supporting distortion extraction and adjustment circuit, and the supporting pre-distortion signal is combined with the other path of main signal to output a supporting pre-distortion power signal; one branch pre-distortion power signal is similarly offset with a branch distortion signal at the output end of the branch power amplification circuit, and a branch distortion offset signal is extracted from the branch power signal with the linearity of-45 dBc to-50 dBc, adjusted and output to the coupling input end of the main branch coupling circuit; the other path of supporting pre-distortion power signal is offset with the main path distortion signal at the output end of the main path power amplification circuit and is output to the main path input end of the main-branch coupling circuit, the two paths of supporting pre-distortion signals at the output end of the main-branch coupling circuit are offset, and the branch distortion signal and the main path distortion signal are similar or are offset in a similar pairing manner; the linearity of the main power amplification circuit is improved to-45 dBc to-50 dBc or above, the efficiency is improved, and the gain linear dynamic range of the C-type main power amplification circuit is expanded.

The invention discloses a power module junction temperature estimation method, which comprises the following steps of: calculating the total loss of a power component based on input three-phase current, three-phase duty ratio, bus voltage, sector position and carrier frequency; according to the obtained total loss and the DBC temperature collected in real time, the cooling water flow is estimated through a temperature difference method; based on the obtained total loss, the cooling water flow and the real-time DBC temperature, the cooling water estimated temperature of the corresponding phase is calculated; calculating the junction temperature by using the obtained total loss, the thermal resistance value corresponding to the cooling water flow and the obtained estimated temperature of the cooling water; and after the obtained three-phase junction temperature is maximized, a compensation table is selected according to the working condition of the motor to carry out compensation correction, and the high-precision estimated junction temperature is output. According to the method, cooling parameters are dynamically obtained through a collaborative estimation process, compensation is carried out according to working conditions, and high-precision junction temperature estimation without a direct temperature sensor is achieved.

The present disclosure provides a voltage monitor and a semiconductor device including the voltage monitor. The voltage monitor includes a first voltage-to-digital converter (VDC), a second VDC, a first digital-to-binary converter (DBC), a second DBC, and an adder. The first VDC is configured to generate a first digital signal in response to a clock signal, and the second VDC is configured to generate a second digital signal in response to the clock signal. The first DBC is connected to the first VDC, and configured to convert the first digital signal to a first binary signal. The second DBC is connected to the second VDC, and configured to convert the second digital signal to a second binary signal. The adder is connected to the first DBC and the second DBC, and configured to combine the first binary signal and the second binary signal into an output signal.

The invention discloses a CAN signal simulation system applied to a BMS-HIL test and a signal sending method, and belongs to the technical field of electric automobiles, and the CAN signal simulation system comprises an upper computer which is internally provided with a bus signal generation model; the bus signal generation model is automatically generated by importing a DBC file, and is used for configuring a period, an ID and a sending state of a generated signal; the real-time signal simulation machine is in communication connection with the upper computer and is used for simulating and generating a signal according to the configuration of the bus signal generation model; the CAN board card is electrically connected with the real-time signal simulation machine and is in communication connection with the tested controller through a CAN bus; and the CAN board card is used for receiving the simulation signal generated by the real-time signal simulation machine and sending the coded CAN message frame to the tested controller. The system has the advantages of being low in cost, good in expansibility, simple in wiring and higher in fault injection capacity.

The application relates to the technical field of message processing, and discloses a DBC message signal assignment and analysis method and system, terminal equipment and a storage medium. By reading and analyzing a DBC file, a message structure body, a message dictionary, a signal structure body and a signal dictionary are created in a code. The DBC is stored in the form of the code, and is convenient to call in the code. In the process of developing and testing CAN communication related products, the functions of signal assignment and signal analysis need to be realized in the code. In the CAN network communication process, a large number of message interactions exist, so the data area of the message is manually constructed in advance before each interaction, and the values to be assigned to some signals are written in, which is prone to errors and a large number of similar codes, and when errors occur, it is not easy to troubleshoot problems. By calling the tool, time can be saved, the data area of the message is automatically constructed through the tool, errors can be avoided, and the work efficiency is greatly improved.

The invention relates to the field of wireless communication, and discloses a 210-220GHz radio frequency receiving module, which comprises a case 1 and a receiving circuit system, the case 1 comprises a local oscillator interface 2, an intermediate frequency interface 3, a radio frequency interface 4 and a power supply interface 5, the receiving circuit system is integrated in the case 1, and the receiving circuit system comprises a local oscillator generation unit 11, a frequency mixing unit 12 and a receiving unit 13 which are mutually cascaded. The spurious suppression is greater than 40dBc; the total power consumption is less than 5W.

Embodiments of the application provide an airborne VHF frequency band power amplifier, and relate to the field of wireless communication, the airborne VHF frequency band power amplifier comprises: a voltage-controlled attenuator, a three-stage power amplification circuit, a filter circuit, a transceiver switch circuit, a coupling detection circuit and a standing wave protection circuit connected in sequence; wherein the three-stage power amplification circuit is further connected with a temperature compensation circuit. The VHF frequency band power amplifier provided by the application realizes super-high gain flatness in the whole frequency band, the output power change in the working frequency band is less than 0.1 dB, the output power is greater than 41 dBm, the distortion under AM modulation is less than 4%, the transceiver isolation is greater than 60 dBc, and the receiving insertion loss is less than 0.2 dB.

The impedance measurement method comprises the following steps: S1, inputting a first current to carry out first impedance measurement to obtain an impedance value Za; s2, inputting a second current to carry out second impedance measurement to obtain an impedance value Zb; s3, calculating the difference between the impedance value Za and the impedance value Zb to obtain Dab; s4, when Dab is smaller than or equal to an allowable range, outputting an average value of the impedance value Za and the impedance value Zb to obtain a final impedance value, and when Dab is larger than the allowable range, inputting a third current, and performing third impedance measurement to obtain an impedance value Zc; s5, calculating the difference between the impedance value Zb and the impedance value Zc to obtain Dbc; and S6, when Dbc is smaller than or equal to an allowable range, outputting an average value of the impedance value Zb and the impedance value Zc to obtain a final impedance value, and when Dab is larger than the allowable range, inputting the current again and repeating the steps.

The invention relates to a low-insertion-loss broadband cavity filter and a design method thereof. The low-insertion-loss broadband cavity filter comprises a cavity, a cover plate covering the cavity, an input interface, an output interface and a plurality of resonators, wherein the input interface and the output interface are formed in the cavity; the resonators adopt a topological structure of a 10-order resonant cavity, and energy exchange is carried out between the adjacent resonators through a coupling structure, so that the insertion loss of the filter within the center frequency range of 1050 MHz to 1450 MHz is not greater than 0.3 dB, the 0.3 dB bandwidth is not less than 400 MHz, the ripple in a passband is not greater than 0.2 dB, and the port voltage standing wave ratio is not greater than 1.3. According to the invention, high-fidelity transmission of signals and high sensitivity of a system are ensured through extremely low insertion loss and in-band ripples; the ultra-wide flat passband is combined with the deep inhibition capability of 40dBc in a plurality of frequency bands, so that excellent frequency selectivity and anti-interference characteristics are provided; and the standing-wave ratio of the full-band inner port is 1.3, so that good impedance matching is ensured. The technical problem that broadband and low loss in a high-performance communication system are difficult to consider at the same time is solved.

The invention discloses an exposure machine special for a DBC ceramic copper-clad substrate, and belongs to the technical field of exposure machines, the exposure machine comprises a machine table, the top of the machine table is provided with a heat exchange heat dissipation port, one side of the machine table is fixedly connected with an illumination plate, the bottom of the illumination plate is provided with an LED lamp panel, and one side of the machine table corresponding to the illumination plate is provided with a table frame exchange port. A pair of exposure table frames are arranged in the table frame exchange port, and a storage box and an extension working plate are arranged on the two sides of the table frame exchange port respectively. According to the invention, through the arrangement of the substrate warping degree detection mechanism and the combination of a large-lead ball screw pair and an incremental rotary encoder, the micro displacement of the pressing plate is directly converted into a high-precision digital pulse signal, and the fine measurement of the flatness of the substrate is realized, so that the original invisible warping deformation becomes measurable and digitized; a basic data basis is provided for subsequent accurate compensation, and the problems of Mark point focusing failure and alignment deviation caused by warping are solved.

The invention discloses a whole vehicle CAN signal general analysis method and system based on time sequence feature matching, and belongs to the field of whole vehicle CAN signals, and the method comprises the steps: obtaining the ID range of a controller to which each CAN message in a CAN bus belongs; after a test working condition is determined according to the to-be-analyzed signal, CAN bus data are collected under the test working condition, and a corresponding CAN message is extracted from the CAN bus data according to the ID range of the controller to which the to-be-analyzed signal belongs; and carrying out time sequence feature matching calculation on the extracted CAN message and a database template, generating a DBC file according to the similarity from high to low, and verifying the validity of the analyzed signal according to the DBC file. According to the method and the device, the ID range of the message sent by the controller is determined in the vehicle CAN bus, and the simplified vehicle bus data and the template text data are subjected to time sequence characteristic matching calculation, so that high accuracy can be guaranteed, the calculation time consumption can be reduced to a great extent, and the vehicle CAN signal analysis efficiency is improved.

The invention relates to the technical field of computers, and discloses a detection method and device, electronic equipment, a medium and a program product. The method comprises the following steps: acquiring a DBC file; determining that the DBC file does not have a first error, the first error indicating that the signal layout cannot be correctly acquired; acquiring bit information occupied by each signal in the same signal group in the DBC file, wherein the bit information comprises a bit mark number; and according to the bit information occupied by each signal, under the condition that the bit information occupied by at least two signals is crossed and overlapped, determining that at least two signals in the same signal group in the DBC file have a bit crossing and overlapping error. According to the method, the efficiency and accuracy of checking the errors in the DBC file can be improved.

The invention discloses a calibration-free high-speed high-linearity low-noise FMCW millimeter wave radar phase-locked loop, which can generate frequency-modulated continuous waves (FMCW) with the step length of 30 Hz, the sweep frequency bandwidth covers the millimeter wave band of 76-81 GHz, the sweep frequency slope as high as 500 MHz / mu s is supported, the output signal power is stable, the linearity is superior to 0.01%, the locking time is less than 4 microseconds, the 80GHz carrier phase noise at the frequency offset of 1 MHz is as low as-100 dBc / Hz, and the phase-locked loop has the advantages of high linearity and low noise. The total power consumption is smaller than that of a conventional millimeter-wave phase-locked loop The overall performance of the antenna is obviously better than that of other existing schemes, and the antenna is suitable for a 76-81 GHz high-performance millimeter wave radar system.

The utility model belongs to the technical field of chip packaging, and particularly relates to a packaging structure of a 34mm IGBT module and the 34mm IGBT module, which comprises a base station, a first DBC board, a second DBC board, a first signal terminal group and a second signal terminal group, the first DBC board and the second DBC board are arranged on the top surface of the base station, the first signal terminal group and the second signal terminal group are arranged on the top surface of the base station, a first IGBT chip is arranged on the first DBC board, and the first IGBT chip is connected with the first signal terminal group through a first line; the second DBC board is provided with a second IGBT chip, and the second IGBT chip is connected with a second signal terminal group through a second line. The length of the first circuit is the same as that of the second circuit, so that the length of signal loops of the upper bridge and the lower bridge of the DBC layout is consistent, signal collection during testing is ensured, and the chip placement area is increased, so that more chip combinations with different sizes and chips with higher power in the future can be better coped with.

The application discloses a DBC ceramic copper-clad plate special exposure machine and belongs to the technical field of exposure machines.The machine table is provided with a heat exchange and heat dissipation port on the top, is fixedly connected with an illumination plate on one side, is provided with an LED lamp plate on the bottom of the illumination plate, is provided with a table frame exchange port on the side corresponding to the illumination plate, is provided with a pair of exposure table frames in the table frame exchange port, and is provided with a storage box and an extended work plate on the two sides of the table frame exchange port.The base plate warping degree detection mechanism is arranged, the combination of the large-lead ball screw pair and the incremental rotary encoder is used to directly convert the small displacement of the pressing plate into a high-precision digital pulse signal, the fine measurement of the base plate flatness is realized, the originally invisible warping deformation becomes measurable and data-based, basic data basis is provided for subsequent accurate compensation, and the Mark point focusing failure and the alignment deviation problem caused by warping are solved.

The invention discloses a bus communication data processing method, device and equipment, and belongs to the technical field of communication, and the method comprises the steps: based on a DBC file and a communication frame identifier in bus communication data, determining a metadata set of a signal corresponding to the communication frame identifier; wherein the metadata set comprises a signal start bit, a signal length, a coding type, a scaling factor and a signal offset; based on the coding type, the signal start bit and the signal length of the signal corresponding to the communication frame identifier, performing bit field extraction on the bus communication data to obtain an original value of the signal corresponding to the communication frame identifier; converting the original value based on a scaling factor and a signal offset of a signal corresponding to the communication frame identifier to obtain an analytic value; and based on the analytic value of the signal corresponding to the communication frame identifier and a preset time axis, a visual image corresponding to the signal is generated, and the time axis in the visual image is the same as the preset time axis. According to the scheme, the time axis alignment efficiency of the signal visualization image is improved.

This invention discloses an ultra-low spurious X / Ku broadband downconversion circuit and its implementation method, belonging to the field of radar communication technology. The circuit includes a reference clock, a first power divider, a second power divider, an input frequency measurement circuit, a phase-locked loop (PLL), a third power divider, a mixer-filter circuit, and an FPGA control unit. The frequency measurement module accurately measures the frequency of the external input signal, and the PLL dynamically adjusts the local oscillator frequency, effectively avoiding mixing intermodulation spurious signals. The final output signal is 1.8 GHz ± 500 MHz, with spurious suppression ≥ 75 dBc. This application achieves ultra-low spurious X / Ku broadband downconversion, significantly superior to traditional solutions (spurious suppression approximately 50 dBc), meeting the requirements of modern broadband radar systems.

The invention relates to a broadband low-phase-noise voltage-controlled oscillator based on a CMOS (Complementary Metal Oxide Semiconductor) process, aiming at solving the problems that the wide tuning and low-phase-noise of the traditional Class-F VCO are difficult to be compatible, the tuning range is narrow and the like. The core architecture comprises four parallel VCO (Voltage Controlled Oscillator) units, a matched buffer and a two-stage alternative selector, each VCO unit is integrated with an exclusive optimized transformer, a multi-bit digital controlled switched capacitor array and a parallel resistor array, and a unilateral tuning design is adopted. The switched capacitor array comprises a coarse tuning unit and a fine tuning unit, and is matched with the overlapping margin of each VCO sub-band to realize seamless connection; the transformer adopts a composite regular octagonal structure, so that the quality factor and the coupling coefficient are improved; the buffer suppresses signal crosstalk, and the selector ensures rapid low-loss switching. According to the scheme, ultra-wide continuous tuning is achieved, the full-band phase noise optimally reaches-131.666 dBc / Hz and 1 MHz, the frequency stepping precision and the signal stability are both considered, and the antenna is suitable for high-frequency and high-requirement scenes such as 5G millimeter wave communication and radar detection.

The application discloses a signal test method, device and equipment and a computer storage medium, and relates to the technical field of automobile communication. The signal test method comprises the following steps: receiving a first input, wherein the first input is used for determining a first initial signal; converting the first initial signal into a first standard signal based on a DBC file of a vehicle; encapsulating the first standard signal into a target message based on a message encapsulation rule corresponding to a target signal device in the vehicle; and sending the target message to the target signal device to perform signal test on the target signal device. According to the embodiment of the application, the operation learning cost in the signal test process can be reduced, the ease of use can be enhanced, and the signal simulation test efficiency can be improved.

The invention provides a frequency domain and time domain combined dynamic demodulation algorithm and system based on a digital phase-locked amplifier, relates to the technical field of weak signal detection and processing, and aims to overcome the defects of weak frequency tracking, time-frequency decoupling, noise suppression and signal fidelity contradiction of a traditional phase-locked amplifier. The CORDIC algorithm generates an orthogonal reference signal and dynamically adjusts gain, and combined noise reduction is realized by combining a frequency domain noise map and time domain adaptive filtering. The method has the beneficial effects that the system frequency tracking error lt is realized; the frequency is 0.1 Hz, the dynamic range is 130 dB, the total harmonic distortion is-92 dBc, and the harmonic suppression ratio is gt; the method is high in response speed, low in resource occupation and suitable for ultra-low-noise and wide-dynamic-range detection scenes such as quantum sensing, biological electromagnetic signal monitoring and high-precision spectral analysis.

A tunable voltage-controlled oscillator (VCO), a dual optical-frequency reference source, an electrical reference oscillator, and an electro-optic frequency divider (eOFD) form a microwave-frequency source. The VCO generates output and modulating signals at frequency fM that is tunable over at least ±5% or more of a nominal microwave frequency. From the VCO signal at fM and output from the dual optical-frequency reference source at frequencies v1 and v2, the eOFD generates an eOFD signal at δf=|v2−v1−n·fM| from which a loop-filtered error signal is derived, dependent on relative phase of the eOFD signal and a reference oscillator signal. The error signal is applied to the VCO to function as a phase-locked loop to stabilize the frequency fM, which can exhibit phase noise across the tuning range that is −120 dBc / Hz+10*log10(fM / 10 GHZ), or less, at 10 kHz offset frequency.

The invention provides a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) module stress wave source inversion method, device and equipment and a storage medium. Relates to the technical field of power device packaging state detection. The method comprises the following steps: constructing a simulation model of transmission of stress waves in a DBC board; wherein the simulation model comprises a DBC board module and a ceramic piezoelectric sensor module arranged below the DBC board module, a stress load is added on the upper surface of the DBC board module as excitation, and the stress load is simulated by Gaussian pulse; determining a transfer function according to the excitation source and the stress wave signal at the bottom of the DBC plate; building a DBC plate stress wave propagation experiment system, and obtaining a stress wave penetration signal; and according to the transfer function and the stress wave penetration signal, calculating to obtain a frequency domain signal and a time domain signal of the stress wave source. According to the invention, the stress wave signal at the bottom of the module is measured, and the signal of the stress wave source is successfully restored.

The present disclosure provides a voltage monitor and a semiconductor device including the voltage monitor. The voltage monitor includes a first voltage-to-digital converter (VDC), a second VDC, a first digital-to-binary converter (DBC), a second DBC, and an adder. The first VDC is configured to generate a first digital signal in response to a clock signal, and the second VDC is configured to generate a second digital signal in response to the clock signal. The first DBC is connected to the first VDC, and configured to convert the first digital signal to a first binary signal. The second DBC is connected to the second VDC, and configured to convert the second digital signal to a second binary signal. The adder is connected to the first DBC and the second DBC, and configured to combine the first binary signal and the second binary signal into an output signal.

A signal checking method, device, equipment, medium, program product and vehicle are disclosed. The method comprises: determining a to-be-checked signal group from a plurality of signal groups; acquiring a variable value corresponding to the to-be-checked signal group according to a name of the to-be-checked signal group, and storing the variable value in a temporary data array; after entering a use mode corresponding to a dbc file, checking a to-be-checked signal included in the to-be-checked signal group based on a name of the to-be-checked signal and the temporary data array through a preset checking function. The method can check different signals, and the checking process is simple, and the checking accuracy is high.

Provided in the present disclosure is a power amplification circuit with similar combining and cancellation. An output end of a parallel or series circuit for main-signal-branch similar input combining and input cancellation is connected to a main power amplification circuit, so as to form a power amplification circuit with similar combining and cancellation that has the function of a combined main circuit with branch similar input combining and input cancellation; and an output end of a combined-connection circuit for main-signal and branch similar input combining in the parallel or series circuit for main-signal-branch similar input combining and input cancellation is connected to an input end of the main power amplification circuit, so as to form a combined main circuit for branch similar input combining and a main signal. The present disclosure improves the linear ACPR value of a Class-C-like main power signal to 30-35 dBc or more after gain linear extension of a main power signal of a combined circuit for branch similar input combining and a main signal, and also improves the linear ACPR value of a Class-C-like main power signal to 40-45 dBc or more after gain linear extension of a main power signal of a combined main circuit with branch similar input combining and cancellation.