22 results about "Power-added efficiency" patented technology

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and / or a bottom surface of the rough buffer layer is / are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

The invention discloses a ka wave band high-efficiency power amplifier based on a GaAs technology. A circuit comprises an input stage tube core, a driving stage tube core, an output stage tube core, an output stage second harmonic suppression network, an inter-stage matching network, an output matching network, a grid electrode biasing circuit, a drain electrode biasing circuit and a stabilizing resistor. The input matching network adopts a T-shaped matching network structure, and the inter-stage matching circuit adopts a matching network combining an LC series structure and a T-shaped structure, so that the working bandwidth of the circuit is further improved, and the area of the power amplifier is reduced; the output efficiency of the whole power amplifier is improved by introducing a second harmonic suppression network at the output end by adopting a second harmonic suppression technology. According to the invention, based on the 0.15 [mu] m GaAs pHEMT technology, a three-stage cascade amplification and power distribution synthesis structure is adopted to realize that the output saturation power is greater than or equal to 29.5 dBm and the power additional efficiency is greater than or equal to 34% in the working frequency band of 34-38GHz, and the power amplifier has the advantages of high stability, high power additional efficiency, high saturation output power, wide working frequency band and the like.

The invention discloses a W-band high-backoff-efficiency power amplifier adopting a power synthesis technology, and relates to the technical field of millimeter wave integrated circuits, and the power amplifier comprises a power distribution network, a differential driving stage, an inter-stage matching network, a differential output stage, an active load modulation network and a self-adaptive bias network. A radio frequency input signal is divided into two paths of signals which are equal in amplitude and have a phase difference of 90 degrees through the power distribution network, and after the two paths of signals are subjected to differential amplification through the main path and the auxiliary path respectively, in-phase power synthesis output is completed through the active load modulation network. A self-adaptive bias network is introduced for an auxiliary circuit amplifier, a radio frequency input signal is accessed to the input end of the self-adaptive bias network, and auxiliary circuit bias is dynamically adjusted according to the size of input power: an auxiliary circuit is closed or slightly opened when the signal is small, and is completely opened when the signal is large, so that high linearity and high power additional efficiency are simultaneously realized in a wide power range. The power amplifier disclosed by the invention still keeps high efficiency in a backoff region, and is suitable for 5.5 G / 6G communication, radar and imaging systems.

The invention relates to the technical field of radio frequency integrated circuits, in particular to an E-type power amplifier of a pi-type matching network integrated with harmonic suppression, which comprises an input matching network, a two-stage amplifying circuit, an inter-stage matching circuit, an output matching network and a bias network, the two-stage amplification circuit comprises an input-stage transistor and an output-stage transistor, the inter-stage matching circuit is provided with a single capacitor C2 which is connected between the two-stage transistor, and the output matching network adopts a single-stage pi-type topological structure. According to the invention, effects of lower DC loss, higher power additional efficiency, better stability and higher harmonic suppression are realized.

A Doherty amplifier circuit having a tunable impedance and phase (“TIP”) circuit to provide an adjustable alpha factor, which allows for a selection of power added efficiency (PAE) curves that are useful for applications having different modulations or to meet other criteria. Embodiments include a Doherty amplifier having a TIP circuit that provides for tunability of the impedance ZINV (resulting in an adjustable alpha factor) while maintaining the phase of the output of the carrier amplifier at 90° (for a selected polarity)±a low phase variation. Embodiments of the TIP circuit include one or more series-connected TIP cells comprising at least one TIP circuit combined with a tunable phase adjustment circuit. In operation, when the impedance of a TIP cell is adjusted, adjustments within the cell are also made to provide a phase shift correction back towards 90° (at the selected polarity).

The present application belongs to but is not limited to the technical field of power amplifier chip, and particularly relates to a table-based frequency domain behavior model parameter extraction method and system, comprising: step 1, testing the output characteristics of the chip under different input powers; step 2, extracting the P2D model parameters of the power amplifier chip; step 3, extracting the bias current and third-order intermodulation product model files; step 4, dynamically calculating and realizing the third-order intermodulation and power added efficiency; and step 5, comparing and verifying the P2D model simulation and actual measurement of the power amplifier chip. The present application proposes a behavior model parameter extraction method capable of representing the power added efficiency and third-order intermodulation based on the table-based frequency domain P2D behavior model, and by combining the measured data of the dynamic drain current in the chip, the third-order intermodulation product output power of the chip and the simulation results of the fundamental wave output power of the chip, the dynamic calculation method of the power added efficiency and third-order intermodulation is broken through, and the simulation prediction of the power added efficiency and third-order intermodulation of the table-based frequency domain P2D model of the chip is realized.

The utility model discloses a power amplifier and a radio frequency front-end module, and the power amplifier comprises an amplification circuit which comprises a first amplification unit and a second amplification unit; the first bias circuit comprises a first bias unit, a first capacitor and a second capacitor, the first capacitor is connected between the third end of the first bias unit and the first signal input end, and the second capacitor is connected between the first end of the first bias unit and the output end of the first amplification unit; the second bias circuit comprises a second bias unit, a third capacitor and a fourth capacitor, the third capacitor is connected between the third end of the second bias unit and the output end of the first amplification unit, and the fourth capacitor is connected between the first end of the second bias unit and the output end of the second amplification unit. According to the power amplifier, not only can the linearity of the power amplifier be optimized, but also the durability can be ensured not to be deteriorated, so that the power additional efficiency of the power amplifier is improved.

This invention discloses a high-efficiency terahertz voltage-controlled oscillator and a phase-locked loop system based thereon, applicable to the field of terahertz communication. It addresses the problem that existing technologies cannot achieve maximum output power or maximum conversion efficiency for the oscillator. Based on the traditional cross-coupled oscillator, this invention adds a gate inductor L between the gates of the two transistors. gg Provides two transistors M P M N Operating at maximum power-added efficiency, the improved voltage-controlled oscillator of this invention outputs maximum power or achieves maximum DC-to-RF conversion efficiency. At the same time, the phase-locked loop system using the high-efficiency oscillator structure shown in this invention can eliminate the need for high-loss power dividers and other components required for multiple outputs, thereby saving the overall power consumption of the phase-locked loop.

The invention provides a bidirectional amplifier and electronic equipment, the bidirectional amplifier comprises a low noise amplification module, a power amplification module and a multiplexing matching network module, the multiplexing matching network module comprises a three-coil transformation unit, a first switch and a second switch; the first switch and the second switch are used for switching in-phase coupling of a second winding and a third winding in the three-coil transformation unit according to the sent voltage signal and switching in-phase coupling of the second winding and the third winding according to the received voltage signal; therefore, high isolation of a sending signal of the bidirectional amplifier, power additional efficiency of a high-frequency output signal and high gain and low noise of a receiving signal are realized. And the first switch and the second switch are embedded in the three-coil transformation unit, so that the chip area is not additionally occupied, and the advantages of high area efficiency and low cost are achieved.

The application discloses a push-pull power amplifier circuit, which comprises a first power amplifier, a second power amplifier, an impedance adjustable unit and a first switching switch; a first input end of the impedance adjustable unit is connected with an output end of the first power amplifier, and a second input end of the impedance adjustable unit is connected with an output end of the second power amplifier; a first end of the first switching switch is connected with an input end of the first power amplifier, and a second end of the first switching switch is grounded; when the push-pull power amplifier circuit works in a high-power mode, the first switching switch is turned off, and the impedance adjustable unit forms a first impedance value; when the push-pull power amplifier circuit works in a low-power mode, the first switching switch is turned on, and the impedance adjustable unit forms a second impedance value, and the first impedance value is smaller than the second impedance value. The technical scheme can improve power-added efficiency and gain flatness of the push-pull power amplifier circuit under different power modes.

Provided in the embodiments of the present disclosure are a communication method, apparatus and device, and a storage medium. The method comprises: a terminal receiving first information sent by a network device, wherein the first information comprises at least one or more pieces of output power information, and the first information is used by the terminal to determine terminal power consumption and / or power added efficiency of a power amplifier at one or more output powers corresponding to the one or more pieces of output power information.

The invention discloses a broadband high-efficiency millimeter wave CMOS power amplifier, and relates to the technical field of millimeter wave integrated circuits. The amplifier is composed of an input matching circuit, a power amplification core circuit and an output matching circuit, the core circuit adopts a four-stage stacked push-pull Class-B structure formed by complementary NMOS and PMOS devices, the output power is improved through alternate conduction, the channel width of each branch transistor is decreased progressively according to the number of stacked stages, series resonant inductors are arranged between the stacked stages, the inductance value is increased progressively, and the output power is increased progressively. Parasitic capacitance is compensated, group delay balance is guaranteed, and efficiency and gain flatness are improved; and the grid electrode of the stacked transistor is grounded through a capacitor to prevent overvoltage breakdown. The input matching circuit comprises a low-Q inductance-resistance matching network and a multi-stage gradual change impedance matching network, and the output matching circuit adopts the multi-stage gradual change impedance matching network, so that broadband matching is realized, and the loss is reduced; the maximum power additional efficiency reaches 40.2% in the frequency band of 10-40 GHz, the maximum saturation output power is 20.4 dBm, and the broadband millimeter wave power divider is suitable for a broadband millimeter wave communication system.

The application relates to a specific absorption rate adjusting method, device, computer equipment, storage medium and computer program product. The method comprises the following steps: acquiring a current bias parameter and a continuous working duration of a power amplifier respectively; determining an actual average specific absorption rate according to a preset mapping relationship, the bias parameter and the continuous working duration; if the actual average specific absorption rate is equal to a preset threshold value, controlling the power amplifier to work at a target bias parameter according to the preset mapping relationship, so that the actual average specific absorption rate is lower than the preset threshold value. By using the method, the actual average absorption rate of the communication equipment can be ensured to be lower than the safety standard preset threshold value of the region, and the power amplifier can work in a state with higher power additional efficiency, so that the transmission efficiency of the communication equipment is improved.

This invention discloses a variable-temperature aluminum nitride nucleation layer and its epitaxial growth method for suppressing radio frequency loss. The method involves setting the third-order AlN nucleation layer as a low-temperature-high-temperature-low-temperature layer and introducing in-situ crystalline SiN between the AlN interfaces. x Layer, this in-situ crystalline SiN x The layer effectively blocks Al / Ga interface diffusion, reducing the probability of parasitic conductive channel formation and effectively reducing RF device loss. The introduction of two low-temperature AlN nucleation layers effectively slows down Al / Ga diffusion, avoids the formation of conductive channels in the substrate, reduces leakage current during RF operation, and improves device power-added efficiency (PAE). Through three-stage temperature control, high-density nucleation and diffusion suppression are achieved in the low-temperature seed layer. The medium-high temperature crystallization layer significantly improves crystal quality and compresses dislocation density to a low level. Finally, the low-temperature high-resistivity layer effectively locks carbon atoms and improves resistivity, thereby achieving a synergistic improvement in the electrical and structural properties of the material.

The application provides a bidirectional amplifier and electronic equipment, comprising a low-noise amplification module, a power amplification module and a multiplex matching network module, the multiplex matching network module comprising a three-coil transformation unit, a first switch and a second switch; the first switch and the second switch switch the second winding and the third winding in the three-coil transformation unit to be in-phase coupled according to a sending voltage signal, and switch the second winding and the third winding to be anti-phase coupled according to a receiving voltage signal, so as to realize high isolation of the bidirectional amplifier sending signal, power additional efficiency of a high-frequency output signal and high gain and low noise of a receiving signal. Since the first switch and the second switch are both embedded into the three-coil transformation unit, no additional chip area is occupied, so that the advantages of high area efficiency and low cost are achieved.

The application discloses a multi-octave power amplifier design method based on Bayesian optimization, constructs a new acquisition function, and uses a Bayesian optimization algorithm to design a multi-octave power amplifier. Through data training, model fitting, prediction point classification, and sampling processes, a set of optimal parameters are obtained as power amplifier coefficients. The application of the method enables the PA to obtain considerable performance in a relatively short optimization time. In the range of 0.6-2.8 GHz, the output power of the power amplifier is greater than 40.3 dBm, the PAE is greater than 62%, and the gain is greater than 10.3 dB. The acquisition function CG-GPUCB is applied to the optimization of the PA circuit for the first time as an acquisition function of the Bayesian optimization algorithm, and the long optimization time is overcome. In a relatively short optimization time, the designed PA has a wider bandwidth under the conditions that the output power, power additional efficiency, gain and the like meet the index requirements.

Operating a power management circuit based on modulation bandwidth and power backoff is provided. The power management circuit includes a transceiver circuit, a power management integrated circuit (PMIC), and a power amplifier circuit that are configured to amplify a radio frequency (RF) signal for transmission in a wireless device. Herein, the power management circuit can be configured to operate under different operating conditions that are defined by modulation bandwidth of the RF signal and power backoff of the power amplifier circuit. The transceiver circuit is configured to adapt configurations and / or controls for the PMIC and / or the power amplifier circuit based on the different operating conditions. As a result, it is possible to improve power added efficiency (PAE), linearity, and / or noise tolerance in the power management circuit under the different operating conditions.

The application relates to the field of radio frequency and microwave electronic technology and discloses a high-efficiency high-linearity dual-frequency power amplifier which comprises an input duplexer, a high-frequency power amplifier, a low-frequency power amplifier, an analog voltage source, a power supply and an output duplexer; two input ends of the input duplexer are connected with a radio frequency input end; two output ends of the input duplexer are connected with an input end of the high-frequency power amplifier and an input end of the low-frequency power amplifier respectively; an output end of the high-frequency power amplifier and an output end of the low-frequency power amplifier are connected with two input ends of the output duplexer respectively; two output ends of the output duplexer are connected with a radio frequency output end; the analog voltage source is connected with a bias voltage end of the high-frequency power amplifier and a bias voltage end of the low-frequency power amplifier respectively; and the power supply is connected with a power supply end of the high-frequency power amplifier and a power supply end of the low-frequency power amplifier respectively. The application can realize high power additional efficiency and high linearity simultaneously under dual frequency bands.

The application discloses a high-efficiency high-linearity power amplifier with an adaptive bias circuit. The application realizes the technical scheme as follows: the high-efficiency high-linearity power amplifier with the adaptive bias circuit comprises a voltage reference source circuit, an adaptive bias circuit and a power amplifier. The adaptive bias circuit is used to provide a dynamically adjusted bias voltage for the power amplifier according to the input signal, so that the power amplifier can realize relatively constant gain under different power supply voltages, the problem of gain compression of the power amplifier under low-power-consumption bias voltage when the input power increases is relieved, and the linearity and power-added efficiency of the low-power-consumption power amplifier are greatly improved. The application relates to a power amplifier in a radio frequency receiver in the field of wireless communication, and particularly relates to a high-efficiency high-linearity power amplifier with an adaptive bias circuit based on a CMOS process.

The embodiment of the invention discloses a communication method and device, communication equipment and a storage medium. The method comprises: a terminal receiving first information sent by a network device, the first information at least comprising one or more pieces of output power information, the first information is used for the terminal to determine terminal power consumption and / or power additional efficiency of a power amplifier under one or more output powers corresponding to the one or more pieces of output power information.

The invention discloses a ku wave band power amplifier based on GaN, the power amplifier obtains source impedance and load impedance of maximum output power and maximum additional efficiency of tube cores of an input stage, a driving stage and an output stage through load traction and source traction, and an input stage matching network and an inter-stage matching network both adopt T-type matching networks. And the output-stage matching network adopts a series resonance network formed by connecting a microstrip line and a capacitor in series. The grid bias circuit and the drain bias circuit in the circuit both adopt a passive bias structure, and the structure can reduce the area and reduce the cost. The power amplifier provided by the invention realizes three-stage amplification at 14 GHz-18 GHz, the small signal gain is greater than or equal to 30 dB, the output power is greater than or equal to 35 dBm, the power additional efficiency is greater than or equal to 46%, the voltage standing wave ratio is small, the efficiency and the linearity are both considered, the integration level is improved to a certain extent, the production cost is reduced to a certain extent, and the power amplifier is suitable for popularization and application. The method can be widely applied to ku-band satellite communication, electronic countermeasure and phased array radar TR assemblies.