45 results about "Power-added efficiency" patented technology

The invention discloses a low-voltage gallium nitride power amplifier based on second harmonic suppression. The low-voltage gallium nitride power amplifier is used for solving the technical problem that the overall efficiency of a radio frequency system is low due to an existing radio frequency power amplifier. The amplifier comprises an input stage circuit, an input stage low-voltage gallium nitride transistor, an intermediate stage circuit, an intermediate stage low-voltage gallium nitride transistor, an output stage circuit, an output stage low-voltage gallium nitride transistor group, a drain bias capacitor, a drain bias voltage port and a secondary harmonic suppression output matching network, by arranging an input-stage low-voltage gallium nitride transistor, an intermediate-stage low-voltage gallium nitride transistor, an output-stage low-voltage gallium nitride transistor group, a secondary harmonic suppression output matching network and a corresponding connection relationship, the secondary harmonic suppression output matching network can be used for suppressing a low-voltage gallium nitride transistor on the basis of a low-voltage gallium nitride process technology. Harmonic suppression is directly carried out on the second harmonic, so that the output power and the power additional efficiency of the radio frequency power amplifier are improved, and the overall efficiency of a radio frequency system is improved.

The invention discloses a broadband power amplifier with an output reconfigurable network, and relates to the technical field of microelectronics, the broadband power amplifier with the output reconfigurable network adopts a three-stage amplification circuit with a gate width ratio of 1: 2: 8, and signal pre-amplification and gain improvement are realized through the first two stages of amplifiers; the last-stage eight-tracheid parallel structure outputs saturated power under high-voltage power supply and realizes power additional efficiency; the output reconfigurable network is controlled by a first switch and a second switch, the first switch is turned off and the second switch is turned on in a high-power mode, so that a compensation microstrip line is grounded to form a fundamental wave matching branch knot, the loss of a harmonic suppression network is avoided, and high-efficiency output is guaranteed; in a low-power mode, the first switch is switched on, the second switch is switched off, the first LC resonance unit and the second LC resonance unit jointly form a band-stop filtering network, secondary and third harmonic impedance is adjusted to be in a near-short-circuit state, so that generation of higher harmonics is restrained, phase distortion is offset through the compensation microstrip line, and the integrity of fundamental wave signals is maintained.

The invention discloses a variable gain power amplifier architecture with low phase error and high rollback efficiency, and belongs to the technical field of radio frequency front ends. Comprising a first transformer, a variable gain amplifier module, a second transformer, a power amplifier module and a coupling line output matching network, the coupling coefficient of the first transformer is k1, and the coupling coefficient of the second transformer is k2; each of the variable gain amplifier module and the power amplifier module comprises two self-adaptive bias modules, and the bias state of the power amplifier module is adjusted through the self-adaptive bias modules, so that the power additional efficiency and the linearity of the power amplifier module are improved; the phase change is offset by simultaneously adjusting the control voltage of the variable gain amplifier module and the grid voltage of the adaptive bias module. Due to good phase error, high output power and high rollback efficiency, the antenna is suitable for a millimeter wave phased array transmitter.

The invention provides a GaAs PHEMT-based power amplifier. The GaAs PHEMT-based power amplifier comprises an input matching circuit, an inter-stage matching circuit and an output matching circuit which are connected in sequence, and the output matching circuit adopts a reactance compensation network matching mode. The class E power amplifier obtains excellent performance, the reactance compensation technology is used in the frequency range of 2.45-2.85 GHz, the power additional efficiency PAE is 61%, the output 1dB compression point is larger than 29 dBm, and broadband, high efficiency and high power are achieved; the invention relates to a broadband hybrid class E power amplifier combining parallel circuit load and reactance compensation technology, the bandwidth of a diode parameter amplifier is improved by using the reactance compensation technology, and the output impedance is matched by designing a matching network as a low-pass network. The class-E power amplifier has the characteristics of high gain and high efficiency, and keeps good performance in the aspects of output, power gain and PAE.

A Doherty amplifier with an adjustable alpha factor is disclosed. The Doherty amplifier circuit has an adjustable impedance and phase ("TIP") circuit to provide an adjustable alpha factor that allows selection of a power added efficiency (PAE) curve that is useful for applications with different modulations or to meet other criteria. Embodiments include a Doherty amplifier with a TIP circuit that provides an impedance Z INV The invention provides an adjustable phase adjustment circuit for the carrier amplifier while maintaining the phase of the output of the carrier amplifier at 90° (for the selected polarity) ± low phase variation. An embodiment of the TIP circuit includes one or more series-connected TIP cells, the TIP cell including at least one TIP circuit combined with an adjustable phase adjustment circuit. In operation, when the impedance of the TIP cell is adjusted, adjustments are also made within the cell to provide phase shift correction back to 90° (at the selected polarity).

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and / or a bottom surface of the rough buffer layer is / are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

The invention discloses a ka wave band high-efficiency power amplifier based on a GaAs technology. A circuit comprises an input stage tube core, a driving stage tube core, an output stage tube core, an output stage second harmonic suppression network, an inter-stage matching network, an output matching network, a grid electrode biasing circuit, a drain electrode biasing circuit and a stabilizing resistor. The input matching network adopts a T-shaped matching network structure, and the inter-stage matching circuit adopts a matching network combining an LC series structure and a T-shaped structure, so that the working bandwidth of the circuit is further improved, and the area of the power amplifier is reduced; the output efficiency of the whole power amplifier is improved by introducing a second harmonic suppression network at the output end by adopting a second harmonic suppression technology. According to the invention, based on the 0.15 [mu] m GaAs pHEMT technology, a three-stage cascade amplification and power distribution synthesis structure is adopted to realize that the output saturation power is greater than or equal to 29.5 dBm and the power additional efficiency is greater than or equal to 34% in the working frequency band of 34-38GHz, and the power amplifier has the advantages of high stability, high power additional efficiency, high saturation output power, wide working frequency band and the like.

The invention discloses a W-band high-backoff-efficiency power amplifier adopting a power synthesis technology, and relates to the technical field of millimeter wave integrated circuits, and the power amplifier comprises a power distribution network, a differential driving stage, an inter-stage matching network, a differential output stage, an active load modulation network and a self-adaptive bias network. A radio frequency input signal is divided into two paths of signals which are equal in amplitude and have a phase difference of 90 degrees through the power distribution network, and after the two paths of signals are subjected to differential amplification through the main path and the auxiliary path respectively, in-phase power synthesis output is completed through the active load modulation network. A self-adaptive bias network is introduced for an auxiliary circuit amplifier, a radio frequency input signal is accessed to the input end of the self-adaptive bias network, and auxiliary circuit bias is dynamically adjusted according to the size of input power: an auxiliary circuit is closed or slightly opened when the signal is small, and is completely opened when the signal is large, so that high linearity and high power additional efficiency are simultaneously realized in a wide power range. The power amplifier disclosed by the invention still keeps high efficiency in a backoff region, and is suitable for 5.5 G / 6G communication, radar and imaging systems.

The invention relates to the technical field of radio frequency integrated circuits, in particular to an E-type power amplifier of a pi-type matching network integrated with harmonic suppression, which comprises an input matching network, a two-stage amplifying circuit, an inter-stage matching circuit, an output matching network and a bias network, the two-stage amplification circuit comprises an input-stage transistor and an output-stage transistor, the inter-stage matching circuit is provided with a single capacitor C2 which is connected between the two-stage transistor, and the output matching network adopts a single-stage pi-type topological structure. According to the invention, effects of lower DC loss, higher power additional efficiency, better stability and higher harmonic suppression are realized.

The invention discloses a temperature characteristic testing method for a high-power short-wave LDMOS solid-state power amplifier. Comprising a high-power short-wave LDMOS solid-state power amplifier direct-current temperature characteristic test, a high-power short-wave LDMOS solid-state power amplifier RF large-signal temperature characteristic test, a high-power short-wave LDMOS solid-state power amplifier dual-tone power and intermodulation temperature characteristic test and a high-power short-wave LDMOS solid-state power amplifier second / third harmonic temperature characteristic test. According to the core of the invention, a signal generator, a direct-current power supply, an alternating-current power supply, a digital power meter, a frequency spectrograph, an attenuator, a load, a temperature box and the like are adopted to realize the temperature characteristic test of the high-power short-wave LDMOS solid-state power amplifier. These instruments have the ability to test drain-source current Ids, output power Pout, gain Gain, power added efficiency PAE, dual-tone power, intermodulation, and second and third harmonic temperature parameters. Compared with other traditional testing technologies, the technology has the advantages of being high in accuracy, high in operability and the like. According to the invention, the temperature characteristic of the high-power short-wave LDMOS solid-state power amplifier can be effectively tested, and important guidance can be provided for the reliability design of the short-wave LDMOS solid-state power amplifier.

The invention discloses a high-efficiency and high-linearity power amplifier with a self-adaptive biasing circuit. According to the technical scheme, the high-efficiency and high-linearity power amplifier with the self-adaptive bias circuit comprises a voltage reference source circuit, the self-adaptive bias circuit and a power amplifier body. The self-adaptive bias circuit is adopted to provide a bias voltage which is dynamically adjusted along with the change of an input signal for the power amplifier, so that the power amplifier is ensured to realize relatively constant gain under different power supply voltages, and the problem of gain compression of the power amplifier when the input power is increased under the low-power-consumption bias voltage is solved; and the linearity and the power additional efficiency of the low-power-consumption power amplifier are greatly improved. The invention relates to a power amplifier in a radio frequency receiver in the field of wireless communication, in particular to a high-efficiency and high-linearity power amplifier with a self-adaptive biasing circuit based on a CMOS (complementary metal oxide semiconductor) process.

A Doherty amplifier circuit having a tunable impedance and phase (“TIP”) circuit to provide an adjustable alpha factor, which allows for a selection of power added efficiency (PAE) curves that are useful for applications having different modulations or to meet other criteria. Embodiments include a Doherty amplifier having a TIP circuit that provides for tunability of the impedance ZINV (resulting in an adjustable alpha factor) while maintaining the phase of the output of the carrier amplifier at 90° (for a selected polarity)±a low phase variation. Embodiments of the TIP circuit include one or more series-connected TIP cells comprising at least one TIP circuit combined with a tunable phase adjustment circuit. In operation, when the impedance of a TIP cell is adjusted, adjustments within the cell are also made to provide a phase shift correction back towards 90° (at the selected polarity).

The present application belongs to but is not limited to the technical field of power amplifier chip, and particularly relates to a table-based frequency domain behavior model parameter extraction method and system, comprising: step 1, testing the output characteristics of the chip under different input powers; step 2, extracting the P2D model parameters of the power amplifier chip; step 3, extracting the bias current and third-order intermodulation product model files; step 4, dynamically calculating and realizing the third-order intermodulation and power added efficiency; and step 5, comparing and verifying the P2D model simulation and actual measurement of the power amplifier chip. The present application proposes a behavior model parameter extraction method capable of representing the power added efficiency and third-order intermodulation based on the table-based frequency domain P2D behavior model, and by combining the measured data of the dynamic drain current in the chip, the third-order intermodulation product output power of the chip and the simulation results of the fundamental wave output power of the chip, the dynamic calculation method of the power added efficiency and third-order intermodulation is broken through, and the simulation prediction of the power added efficiency and third-order intermodulation of the table-based frequency domain P2D model of the chip is realized.

The example embodiments are directed to a push-pull amplifier embedded with cross-coupled transistor feedback cancellation. In one example, the amplifier may include a first load, a second load, a circuit comprising first and second field effect transistors (FETs) that are electrically coupled to each other and that are electrically coupled to the first load and the second load, and a feedback cancellation circuit that interconnects the first and second FETs and comprises coupling capacitors configured to increase gain, circuit stability, and Power Added Efficiency (PAE) from the first and second FETs.

The utility model discloses a power amplifier and a radio frequency front-end module, and the power amplifier comprises an amplification circuit which comprises a first amplification unit and a second amplification unit; the first bias circuit comprises a first bias unit, a first capacitor and a second capacitor, the first capacitor is connected between the third end of the first bias unit and the first signal input end, and the second capacitor is connected between the first end of the first bias unit and the output end of the first amplification unit; the second bias circuit comprises a second bias unit, a third capacitor and a fourth capacitor, the third capacitor is connected between the third end of the second bias unit and the output end of the first amplification unit, and the fourth capacitor is connected between the first end of the second bias unit and the output end of the second amplification unit. According to the power amplifier, not only can the linearity of the power amplifier be optimized, but also the durability can be ensured not to be deteriorated, so that the power additional efficiency of the power amplifier is improved.

The invention discloses a tuned dual-frequency matching power amplifier, comprising a dielectric plate, on which an input port, an input matching circuit, a stabilizing circuit, a transistor, a tuning circuit, a DC bias circuit, an output matching circuit and an output port are respectively arranged; the input port is connected to the input matching circuit, the input matching circuit is connected to the stabilizing circuit, the stabilizing circuit is connected to the gate of the transistor, the source of the transistor is grounded, its drain is connected to the tuning circuit, the tuning circuit is connected to the output matching circuit, and the output matching circuit is connected to the output port; the DC bias circuit is respectively connected to the gate and drain of the transistor to provide a gate bias voltage and a drain bias voltage. The whole power amplifier structure of the invention is simple and reliable, and is easy to process, with low cost and high power added efficiency. No power amplification is performed outside the working frequency band, and spectrum resources are better utilized.

The embodiment of the invention provides a radio frequency power amplifier, a radio frequency front-end module and electronic equipment. The radio frequency power amplifier comprises a differential power amplification circuit and a transformer, the transformer comprises a first coil and a second coil, the second coil and the first coil are mutually coupled, a first output end of the differential amplification circuit is connected with a first end of the first coil, a second output end of the differential amplification circuit is connected with a second end of the first coil, and a first end of the second coil is connected to a signal output end; the second end of the second coil is connected to the ground; wherein the first coil at least comprises a first sub-coil and a second sub-coil, and the first sub-coil and the second sub-coil are connected in parallel; the second coil at least comprises a third sub-coil and a fourth sub-coil, and the third sub-coil and the fourth sub-coil are connected in series. According to the radio frequency power amplifier, the transformer can realize a higher impedance conversion ratio, so that the power additional efficiency of the radio frequency power amplifier is improved, the power of a radio frequency signal is improved, and the radio frequency signal has higher power and coverage distance.

This invention discloses a high-efficiency terahertz voltage-controlled oscillator and a phase-locked loop system based thereon, applicable to the field of terahertz communication. It addresses the problem that existing technologies cannot achieve maximum output power or maximum conversion efficiency for the oscillator. Based on the traditional cross-coupled oscillator, this invention adds a gate inductor L between the gates of the two transistors. gg Provides two transistors M P M N Operating at maximum power-added efficiency, the improved voltage-controlled oscillator of this invention outputs maximum power or achieves maximum DC-to-RF conversion efficiency. At the same time, the phase-locked loop system using the high-efficiency oscillator structure shown in this invention can eliminate the need for high-loss power dividers and other components required for multiple outputs, thereby saving the overall power consumption of the phase-locked loop.

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and / or a bottom surface of the rough buffer layer is / are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

The present invention discloses a communication device based on an adaptive power amplifier module, which relates to the technical field of power amplifiers, and includes a radio frequency signal input module, a radio frequency signal processing and analysis module, a step-type adaptive power amplifier module based on chip control, and a radio frequency signal transmitting module. The present invention first needs to control the step-type adaptive power amplifier module to perform initial operation according to the maximum amplification power. During the operation, the power amplification strategy instruction based on the gradient descent method is executed, and the amplification power that can be provided by the step-type adaptive power amplifier module is sequentially decreased to find the optimal balance point of power added efficiency and amplifier linearity, so that the radio frequency amplified signal transmitted by the radio frequency signal transmitting module is stable and of moderate intensity, and the heat loss, power added efficiency and amplifier linearity of the power amplifier itself are at a balance point; the reliability of the communication device is improved.

A Doherty amplifier circuit having a tunable impedance and phase (“TIP”) circuit to provide an adjustable alpha factor, which allows for a selection of power added efficiency (PAE) curves that are useful for applications having different modulations or to meet other criteria. Embodiments include a Doherty amplifier having a TIP circuit that provides for tunability of the impedance ZINV (resulting in an adjustable alpha factor) while maintaining the phase of the output of the carrier amplifier at 90° (for a selected polarity)±a low phase variation. Embodiments of the TIP circuit include one or more series-connected TIP cells comprising at least one TIP circuit combined with a tunable phase adjustment circuit. In operation, when the impedance of a TIP cell is adjusted, adjustments within the cell are also made to provide a phase shift correction back towards 90° (at the selected polarity).

The present disclosure provides a control method and device, apparatus and a storage medium. The method includes: determining a first parameter corresponding to an output power with a highest occurrence probability in a target output power range of a power amplifier in a terminal, where the first parameter is used to optimize and control a power added efficiency of the power amplifier, and optimizing the power added efficiency of the power amplifier by using the first parameter.

The invention provides a bidirectional amplifier and electronic equipment, the bidirectional amplifier comprises a low noise amplification module, a power amplification module and a multiplexing matching network module, the multiplexing matching network module comprises a three-coil transformation unit, a first switch and a second switch; the first switch and the second switch are used for switching in-phase coupling of a second winding and a third winding in the three-coil transformation unit according to the sent voltage signal and switching in-phase coupling of the second winding and the third winding according to the received voltage signal; therefore, high isolation of a sending signal of the bidirectional amplifier, power additional efficiency of a high-frequency output signal and high gain and low noise of a receiving signal are realized. And the first switch and the second switch are embedded in the three-coil transformation unit, so that the chip area is not additionally occupied, and the advantages of high area efficiency and low cost are achieved.

An amplifier circuit is disclosed. The Doherty amplifier circuit has an adjustable impedance and phase ("TIP") circuit to provide an adjustable alpha factor that allows selection of a power added efficiency (PAE) curve that is useful for applications with different modulations or for meeting other criteria. Embodiments include a Doherty amplifier having a TIP circuit that provides adjustability to impedance ZINV (producing an adjustable alpha factor) while maintaining the phase of the output of the carrier amplifier at a phase change of 90 DEG (for a selected polarity) + / -low. Embodiments of a TIP circuit include one or more TIP cells connected in series, the TIP cells including at least one TIP circuit in combination with an adjustable phase adjustment circuit. In operation, when adjusting the impedance of the TIP cell, adjustments within the cell are also made to provide phase shift correction back to 90 DEG (at a selected polarity).

The application discloses a push-pull power amplifier circuit, which comprises a first power amplifier, a second power amplifier, an impedance adjustable unit and a first switching switch; a first input end of the impedance adjustable unit is connected with an output end of the first power amplifier, and a second input end of the impedance adjustable unit is connected with an output end of the second power amplifier; a first end of the first switching switch is connected with an input end of the first power amplifier, and a second end of the first switching switch is grounded; when the push-pull power amplifier circuit works in a high-power mode, the first switching switch is turned off, and the impedance adjustable unit forms a first impedance value; when the push-pull power amplifier circuit works in a low-power mode, the first switching switch is turned on, and the impedance adjustable unit forms a second impedance value, and the first impedance value is smaller than the second impedance value. The technical scheme can improve power-added efficiency and gain flatness of the push-pull power amplifier circuit under different power modes.

Provided in the embodiments of the present disclosure are a communication method, apparatus and device, and a storage medium. The method comprises: a terminal receiving first information sent by a network device, wherein the first information comprises at least one or more pieces of output power information, and the first information is used by the terminal to determine terminal power consumption and / or power added efficiency of a power amplifier at one or more output powers corresponding to the one or more pieces of output power information.

The invention belongs to but not limited to the technical field of power amplifier chips, and particularly relates to a table fundamental frequency domain behavior model parameter extraction method and system, and the method comprises the steps: 1, testing the output characteristics of a chip under different input powers; 2, P2D model parameters of the power amplifier chip are extracted; 3, extracting a bias current and third-order intermodulation product model file; step 4, dynamic calculation of third-order intermodulation and power additional efficiency is realized; and 5, performing comparison verification on power amplifier chip P2D model simulation and actual measurement. Based on a table fundamental frequency domain P2D behavior model, the invention provides a behavior model parameter extraction method capable of representing the power additional efficiency and the third-order intermodulation, and by combining the actual measurement data of the dynamic drain current in the chip, the output power of the third-order intermodulation product of the chip and the simulation result of the fundamental wave output power of the chip, the power additional efficiency and the third-order intermodulation of the chip can be represented. A dynamic calculation method of the power additional efficiency and the third-order intermodulation is broken through, and simulation prediction of the chip power additional efficiency and the third-order intermodulation of the table fundamental frequency domain P2D model is achieved.

The invention discloses a broadband high-efficiency millimeter wave CMOS power amplifier, and relates to the technical field of millimeter wave integrated circuits. The amplifier is composed of an input matching circuit, a power amplification core circuit and an output matching circuit, the core circuit adopts a four-stage stacked push-pull Class-B structure formed by complementary NMOS and PMOS devices, the output power is improved through alternate conduction, the channel width of each branch transistor is decreased progressively according to the number of stacked stages, series resonant inductors are arranged between the stacked stages, the inductance value is increased progressively, and the output power is increased progressively. Parasitic capacitance is compensated, group delay balance is guaranteed, and efficiency and gain flatness are improved; and the grid electrode of the stacked transistor is grounded through a capacitor to prevent overvoltage breakdown. The input matching circuit comprises a low-Q inductance-resistance matching network and a multi-stage gradual change impedance matching network, and the output matching circuit adopts the multi-stage gradual change impedance matching network, so that broadband matching is realized, and the loss is reduced; the maximum power additional efficiency reaches 40.2% in the frequency band of 10-40 GHz, the maximum saturation output power is 20.4 dBm, and the broadband millimeter wave power divider is suitable for a broadband millimeter wave communication system.

To provide an electronic device that can efficiently save power by increasing the power added efficiency (PAE) of a power amplifier.SOLUTION: An electronic device 100 includes a driver amplifier, a power amplifier, a power detector, and a bias circuit. The driver amplifier outputs a radio frequency (RF) signal. The power amplifier is electrically connected to the driver amplifier. The power amplifier has an input terminal IN, and receives an RF signal 132 through the input terminal and amplifies the RF signal. The power detector is electrically coupled to the input terminal and detects an input power W of the RF signal. The power detector outputs a driving voltage 120 according to the input power. The bias circuit 106 is electrically connected to the power amplifier and the power detector. The bias circuit outputs a driving current 122 to the power amplifier according to the driving voltage. The power amplifier amplifies the power of the RF signal from the input power to a target power according to the driving current 122.SELECTED DRAWING: Figure 1