Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof

A technology of low-temperature polysilicon and array substrates, applied in semiconductor/solid-state device manufacturing, optics, instruments, etc., can solve the problems of increased processing time and processing cost, complex manufacturing process, and various manufacturing processes, and achieve process reduction of exposure. Effect of reducing processing cost and shortening processing time

Active Publication Date: 2012-09-19
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] It can be seen from the above that in the prior art, in the manufacturing process of the low-temperature polysilicon TFT array substrate, a total of at least 7 patterning processes are required, the manufacturing process is complicated, the manufacturing process is numerous, the material consumption is high, and the processing time and processing time are increased cost

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  • Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof
  • Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof
  • Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof

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Experimental program
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Effect test

Embodiment 1

[0065] The method for manufacturing a low-temperature polysilicon TFT array substrate provided in Embodiment 1 of the present invention is described by taking the manufacture of a low-temperature polysilicon TFT array substrate by using a gray tone mask (GTM) as an example.

[0066] First, refer to Figure 3a The main principles of the GTM process are explained. The GTM mask plate uses the grating effect to make the intensity of the transmitted light different in different areas, so that the photoresist can be selectively exposed and developed. Figure 3a It shows the process of using the GTM mask 21 to expose the photoresist. In the GTM mask 21 , a transparent area 211 , an opaque area 212 and a translucent area 213 are included. The photoresist 22 is in a state after exposure, wherein the region 221 corresponds to the transparent region 211 of the GTM mask 21, the region 222 corresponds to the opaque region 212 of the GTM mask 21, and the region 223 corresponds to the tran...

Embodiment 2

[0097] The method for manufacturing a low-temperature polysilicon TFT array substrate provided in Embodiment 2 of the present invention is described by taking the manufacture of a low-temperature polysilicon TFT array substrate by using a semi-transparent mask (HTM) as an example.

[0098] First, refer to Figure 3b The main principle of the HTM process is explained. The HTM mask plate is used to selectively expose and develop the photoresist through the different intensity of light transmitted in different areas. Figure 3b It shows the process of exposing the photoresist by using the HTM mask 31 . In the HTM mask 31 , a transparent area 311 , an opaque area 312 and a translucent area 313 are included. The photoresist 32 is the state after exposure, wherein, the region 321 corresponds to the transparent region 311 of the HTM mask 31, the region 322 corresponds to the opaque region 312 of the HTM mask 31, and the region 323 corresponds to the translucent region of the HTM ma...

Embodiment 3

[0121] The low-temperature polysilicon TFT array substrate provided by the embodiment of the present invention, such as Figure 5Q shown, including:

[0122] Substrate 51;

[0123] A buffer layer 52 is formed on the substrate 51;

[0124] A polysilicon semiconductor active layer 53 is formed on the buffer layer 52;

[0125] A source 541 and a drain 542 are formed on the polysilicon semiconductor active layer 53; the source 541, the drain 542 and the polysilicon semiconductor active layer 53 form a TFT region;

[0126] A gate insulating layer 56 is formed on the source 541 and the drain 542;

[0127] A gate 57 and a gate line (not shown in the figure) are formed on the gate insulating layer 56;

[0128] A protective layer 58 is formed on the gate 57 and the gate line;

[0129] A pixel electrode layer 59 is formed on the protective layer 58, and the pixel electrode layer 59 is connected to the drain electrode 542 through a via hole 59' located on the protective layer 58 and...

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Abstract

The embodiment of the invention provides a low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and a manufacturing method thereof, and relates to the field of manufacturing of liquid crystal displays and AMOLED (Active Matrix / Organic Light Emitting Diode) displays. The treatment frequency of a composition technology is reduced, so that the manufacturing flow is simplified and the manufacturing cost is reduced. The method provided by the invention comprises the following steps of: forming a buffer layer on a substrate; forming a polycrystalline silicon layer on the buffer layer; forming a first metal layer on the polycrystalline silicon layer; performing composition process treatment on the first metal layer and the polycrystalline silicon layer by using a gray tone mask plate or semitransparent mask plate; and obtaining patterns of a data line, a source electrode, a drain electrode and a polycrystalline silicon semiconductor part through one-time composition process. The embodiment of the invention is used for manufacturing the low-temperature polycrystalline silicon TFT array substrate.

Description

technical field [0001] The invention relates to the field of manufacturing liquid crystal displays and AMOLED displays, in particular to a low-temperature polysilicon TFT (Thin Film Transistor, Thin Film Field Effect Transistor) array substrate and a manufacturing method thereof. Background technique [0002] Due to the defects of amorphous silicon itself, such as low on-state current, low mobility, and poor stability caused by too many defects, it has been restricted in many fields. Field of application, LTPS (Low Temperature Poly-Silicon, low temperature polysilicon) technology came into being. [0003] Such as figure 1 , figure 2 As shown, the low-temperature polysilicon TFT array substrate manufacturing method in the prior art includes: [0004] S101 , forming a buffer layer 12 on a substrate 11 . [0005] S102 , forming a polysilicon active layer pattern on the buffer layer through the first patterning process. [0006] S103 , depositing an inorganic material on t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L21/77G02F1/1362G02F1/1368
Inventor 马占洁龙春平
Owner BOE TECH GRP CO LTD
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