7600results about "Printed element electric connection formation" patented technology

Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed. Various techniques are described for mounting the contact structures to a variety of electronic components (e.g., semiconductor wafers and dies, semiconductor packages, interposers, interconnect substrates, etc.), and various process sequences are described. The resilient contact structures described herein are ideal for making a "temporary" (probe) connections to an electronic component such as a semiconductor die, for burn-in and functional testing. The self-same resilient contact structures can be used for subsequent permanent mounting of the electronic component, such as by soldering to a printed circuit board (PCB). An irregular topography can be created on or imparted to the tip of the contact structure to enhance its ability to interconnect resiliently with another electronic component. Among the numerous advantages of the present invention is the great facility with which the tips of a plurality of contact structures can be made to be coplanar with one another. Other techniques and embodiments, such as wherein the falsework wirestem protrudes beyond an end of the superstructure, or is melted down, and wherein multiple free-standing resilient contact structures can be fabricated from loops, are described.

A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and / or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and / or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling narrow trenches while the plating bath used during the second step, is optimized for filling wide trenches. The net result is a final layer having a planar surface, with all trenches being properly filled.

A process for applying a metallization interconnect as to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced sed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation off a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed. This invention can remarkably suppress unwanted radiation by absorbing the potential fluctuation (resonance) which occurs in a power supply loop by equivalently reducing the Q-value of the stray capacitance, absorbing the standing wave by the parallel plate lines matchedly terminated and, closing and shielding the parallel plate lines.

A copper plating bath comprising a reaction condensate of an amine compound and glycidyl ether and / or a quaternary ammonium derivative of this reaction condensate, and a plating method using this copper plating bath are disclosed. A copper plating bath capable of providing highly reliable copper plating on a substrate such as a silicone wafer semiconductor substrate or printed board having minute circuit patterns and small holes such as blind via-holes, through-holes, and the like, and a method of copper plating using the copper plating bath can be provided.

The present invention provides systems and methods for attenuating the effect of ambient light on optical sensors and for measuring and compensating quantitatively for the ambient light.