201results about "Printed element electric connection formation" patented technology

Provided in the present application are a multilayer circuit board and an electronic device. The multilayer circuit board comprises a circuit unit layer, wherein the circuit unit layer comprises at least two circuit layers arranged parallel to and spaced apart from each other, and an insulating layer sandwiched between adjacent circuit layers; surfaces arranged opposite each other in the direction of thickness of the circuit unit layer are a first side surface and a second side surface; the circuit unit layer is provided with via holes penetrating the circuit unit layer in the direction of thickness thereof; the via holes are defined by inner side walls; the first side surface or the second side surface is provided with a first copper plating layer; second copper plating layers connected to the first copper plating layer are plated on the inner side walls; and the at least two circuit layers are connected in parallel by means of the second copper plating layers. The multilayer circuit board of the present application achieves parallel connection between the circuit layers, effectively controls the resistance value of the circuit board and meets performance requirements while reducing the overall thickness of the multilayer circuit board and lowering the space requirements for mounting the multilayer circuit board.

The invention discloses a circuit board structure and a manufacturing method thereof, the circuit board structure comprises a first copper foil layer, an insulating layer, a second copper foil layer, a connecting hole and a first conductive layer, the first copper foil layer and the second copper foil layer are stacked in the thickness direction, the insulating layer is located between the first copper foil layer and the second copper foil layer, and the connecting hole is located between the first copper foil layer and the second copper foil layer. The connecting hole penetrates through the first copper foil layer and the insulating layer, the second copper foil layer is exposed at the bottom of the connecting hole, and the first conductive layer covers part of the surface, deviating from the insulating layer, of the first copper foil layer and the first inner side wall of the connecting hole.

The application discloses an improved semi-additive process based on customized ultra-thin copper foil flexible copper-clad plate and a fine circuit board, and belongs to the technical field of flexible printed circuit boards. The process adopts a customized ultra-thin copper foil FCCL substrate, and the circuit is prepared through substrate selection pretreatment, pattern size pre-compensation, laser drilling and black shadow process hole metallization, pattern transfer and selective electroplating thickening, film stripping and flash etching forming. The micro-etching amount is cooperatively controlled throughout the process, and combined with optimized plasma cleaning and high hole filling electroplating, the fine circuit production with a minimum line width and line spacing of 45 microns or less can be stably realized, and the highest fine circuit production can reach 25 / 25 microns. The application solves the problems of traditional process, such as large side etching, low precision, poor yield and the like, and the circuit board prepared has the advantages of excellent size stability, strong heat resistance and uniform micro-hole filling, is suitable for high-density interconnection and high-end consumer electronic demand, and has significant advantages of precision, yield and reliability compared with existing processes.

The application discloses a circuit board and a plating method. The plating method comprises the following steps: providing a substrate, forming a through hole on the substrate; providing a metal piece, the metal piece comprises a main body and an elastic part, the elastic part protrudes from the surface of the main body; inserting the metal piece into the through hole, and the elastic part abuts against the inner wall of the through hole; plating the substrate to form a plating layer, and the plating layer fills the through hole.

A method of manufacturing a packaging substrate according to the present disclosure includes a preparing step of preparing a panel-level packaging substrate comprising a core substrate, a first redistribution layer disposed on the core substrate, and a second redistribution layer disposed under the core substrate, and an electroless surface treatment step of forming terminals by simultaneously performing electroless surface treatment on an upper surface and a lower surface of the panel-level packaging substrate. The packaging substrate comprises a core layer, the first redistribution layer disposed on the core layer, the second redistribution layer disposed under the core layer, and the terminals disposed on an upper surface of the first redistribution layer and a lower surface of the second redistribution layer. A difference between a maximum thickness value and a minimum thickness value of the terminals formed on the packaging substrate is 5 µm or less. In such a case, terminals having improved thickness uniformity may be formed, and process efficiency during terminal formation may be promoted.

This invention discloses a method for back-drilling printed circuit boards (PCBs). The method includes: forming a first metallized via and a second metallized via on the PCB; obtaining the actual board thickness at the location of the first metallized via; controlling a drill bit to drill stepwise from a first surface conductive layer to a first distance from the upper surface of a reference conductive layer at the location of the first metallized via, based on the actual board thickness; controlling the drill bit to drill down to the reference conductive layer at the first distance from the upper surface of the reference conductive layer; and obtaining a continuity or disconnection signal of a continuity detection circuit based on the drill bit; setting a back-drilling depth based on the actual board thickness at the location of the first metallized via; and controlling the drill bit to drill down to the back-drilling depth after obtaining a disconnection signal of the continuity detection circuit to form a back-drilled hole. The technical solution of this invention improves the back-drilling accuracy and the quality of the back-drilled hole.

Method for manufacturing segmented electro-optic display backplanes includes (a) providing a laminate comprising an insulating layer having opposite first and second surfaces and a conductive metal layer having opposite first and second surfaces (the insulating layer second surface is superposed on the conductive metal layer first surface); (b) applying laser energy from a first laser source passing through the insulating layer onto selected portions of conductive metal layer first surface to cause adjacent portions of the insulating layer to be pyrolyzed to form conductive carbon regions; (c) applying laser energy from a second laser source on the insulating layer first surface to pyrolyze selected portions thereof into conductive carbon segments electrically isolated from each other by other portions of the insulating layer. The conductive carbon regions in the insulating layer form vias between each of the conductive carbon segments and one of the selected portions of the conductive metal layer.

The present invention provides a printed circuit board that allows for easy formation of fine circuits, improved transmission characteristics, reduced warping, and miniaturization of via diameters when forming embedded circuits. [Solution] This disclosure relates to a printed circuit board 100A comprising: a first insulating material 111a having a first opening v1; an insulating layer 111 laminated on one surface of the first insulating material 111a, filling at least a portion of the first opening v1, and comprising a second insulating material 111b made of a different material from the first insulating material 111a; a wiring pattern 112 arranged on one surface of the first insulating material 111a and embedded in the second insulating material 111b such that one surface is exposed from one surface of the second insulating material 111b; and a via pattern 113 spaced apart from the first insulating material 111a within the first opening v1 and embedded in the second insulating material 111b such that one surface is exposed from one surface of the second insulating material 111b.

A method for fabricating vias in a multilayer dielectric PCB stack (50) comprising alternating plurality of first dielectric layers (52) and second dielectric layers (54), the first dielectric layers (52) comprising a first dielectric material having a first glass transition temperature (Tg), and the second dielectric layers (54) comprising a second dielectric material having a second glass transition temperature (Tg) higher than the first glass transition temperature (Tg), wherein a plurality of vias (64) are formed (202, 204) into the plurality of first dielectric layers (52) and second dielectric layers (54), the method comprising: at least partially dissolving (206) the first dielectric layers (52) between the vias (64); filling (208, 210) the vias (64) and the spaces formed between the second dielectric layers (54) due to the voids left by the at least partial dissolution of the first dielectric layers (52) with metal (68, 70), thereby obtaining a metal network (72) interconnecting the vias (64) with each other.

The application discloses a drilling process of rigid-flex printed circuit board, comprising the following steps: board surface detection: detecting the board surface of the laminated rigid-flex printed circuit board, identifying and determining the uneven area of the board surface; filling treatment: filling the recessed part in the uneven area, and making the board surface tend to be flat after the filling material is solidified; setting the drilling alignment mark on the board surface after the filling treatment; drilling processing: drilling according to the drilling alignment mark. The recessed area is filled and treated, the height difference of the board surface is eliminated, the drill bit is uniformly stressed when contacting the board surface, the drill bit deflection is effectively prevented, and the hole deviation defects are reduced. The flat board surface makes the drill bit stably stressed when passing through different areas, and the hole wall roughness, burr or nail head phenomenon caused by the stress mutation is avoided.

The application belongs to the technical field of PCB plating, and relates to a high-precision LED PCB and a preparation method thereof, which comprises the following steps: pretreating a PCB substrate, wherein the PCB substrate has a through hole; depositing a first conductive layer on the hole wall of the PCB substrate; depositing a first metal layer on the surface and the hole wall of the PCB substrate; using a developing exposure process to make a resist film cover part of the surface of the circuit board and expose the through hole area of the surface of the circuit board, so as to form a plating pattern; depositing a second metal layer on the hole wall of the preset through hole area of the PCB substrate to obtain a preliminary product; and post-treating the preliminary product, wherein the post-treatment comprises resin hole plugging, film stripping and grinding to obtain the LED PCB. The application realizes a breakthrough in precision and reliability, greatly improves the product quality consistency, obtains a very high surface flatness of the copper surface, significantly optimizes the production efficiency and cost benefit, and provides a replicable paradigm for industry upgrading.

The present invention provides a method for producing a wiring board, the method eliminating the need for formation and removal of a mask when a via hole or a trench is formed, enabling an insulating material layer to have excellent insulation performance and electrical characteristics, and also enabling fine wiring. The present invention specifically provides a method for producing a wiring board, the method comprising: (1) a step in which a substrate having a conductor circuit and an insulating material layer that is formed on the conductor circuit and is formed of a cured product of a thermosetting material is prepared, and a photosensitive material layer is formed on the surface of the insulating material layer by performing either or both of coating or bonding of a photosensitive material onto the surface of the insulating material layer; (2) a step in which the photosensitive material layer is exposed to light and developed so as to form a plasma mask having an opening; (3) a step in which the insulating material layer is irradiated with plasma through the plasma mask so as to form either or both of a via hole and a trench in the insulating material layer positioned at the opening of the plasma mask, while thinning the plasma mask; and (4) a step in which a conductor layer is formed on the thinned plasma mask as well as on the surface of either or both of the via hole and the trench.

The present invention provides an electronic component-embedded substrate in which through-holes for embedding electronic components are formed in a glass layer, and which prevents cracks or breaks from occurring in the glass during the processing of the through-holes and / or during the process of placing electronic components in the through-holes, thereby improving yield. [Solution] This disclosure relates to an electronic component embedded substrate, comprising: a glass layer; a through-hole penetrating between the upper and lower surfaces of the glass layer; a metal layer, at least a portion of which is embedded within the glass layer and at least a portion of which is exposed from the glass layer through the wall surface of the through-hole; an electronic component, at least a portion of which is disposed within the through-hole; and a sealing material, at least a portion of which is embedded within the electronic component and which fills at least a portion of the through-hole.

This application relates to the field of printed circuit board (PCB) technology, and discloses a PCB manufacturing method and a PCB. The PCB manufacturing method includes: providing a substrate, the substrate including a first circuit layer, a second circuit layer, and an insulating layer; processing buried vias on the substrate, the buried vias including receiving holes and multiple routing holes, the inner wall of the routing holes being provided with conductive portions, the first circuit layer and / or the second circuit layer being connected to the conductive portions; placing electronic components within the buried vias, the first circuit layer, the second circuit layer, and the conductive portions being spaced apart from the electronic components; filling the space between the inner wall of the receiving holes and the electronic components with an insulating matrix, the insulating matrix supporting the electronic components. The PCB manufacturing method and PCB provided in this application are used to improve the problem of low wiring density around electronic components after they are embedded in the substrate of the PCB in related technologies.

A printed wiring board includes a first conductor layer, a resin insulating layer including resin and inorganic particles, a second conductor layer including a seed layer and an electrolytic plating layer on the seed layer, and a via conductor connecting the first conductor layer and second conductor layer and including the seed layer and electrolytic plating layer extending from the second conductor layer. The second conductor layer and via conductor are formed such that the seed layer includes an alloy including copper, aluminum and a metal including one or more metals selected from nickel, zinc, gallium, silicon and magnesium, and the resin insulating layer is formed such that the inorganic particles include first inorganic particles forming an inner wall surface in the opening and second inorganic particles embedded in the resin insulating layer and that shapes of the first inorganic particles are different from shapes of the second inorganic particles.

This application provides a method, apparatus, and terminal device for manufacturing a circuit board. The method includes: providing a substrate, the substrate including multiple target holes, an inner core board, an outer conductive layer, and a dielectric layer between the core board and the conductive layer; the core board including targets and circuitry; forming windows on the surface of the conductive layer based on the multiple target holes, and ablating the targets at their positions on the conductive layer to expose the targets; positioning based on the targets, ablating the windows to form blind vias, and forming depth-controlled vias in the conductive layer, the depth of the depth-controlled vias being greater than the depth of the blind vias; filling the blind vias and depth-controlled vias, making the blind vias flat and the depth-controlled vias visible recesses; and using the recesses corresponding to the depth-controlled vias as positioning references to fabricate a multilayer circuit board. This improves the alignment accuracy of the circuit board.

The invention discloses a circuit board, which is characterized by comprising a lead wire for mounting a patch fuse, which forms a circuit pattern and is broken in the middle; a patch fuse which is mounted to a broken portion of the patch fuse mounting lead wire and blocks a current flowing through the circuit pattern when an overcurrent occurs; the pattern fuse wire and the patch fuse mounting wire are arranged in parallel, and the middle of the pattern fuse wire and the patch fuse mounting wire are disconnected; and a pattern fuse which is formed at a broken portion of the pattern fuse wire and blocks a current flowing through the circuit pattern when an overcurrent occurs. Therefore, even if the patch fuse is damaged, the pattern fuse can properly cope with the blocking capacity.

The application provides a selective resin hole plugging protection structure of a rigid-flex printed circuit board, which comprises a dry film layer and a rigid-flex printed circuit board provided with a hole to be plugged, a hole not to be plugged and a recessed groove, the dry film layer is attached to the upper and lower sides of the rigid-flex printed circuit board, the dry film layer is provided with a window hole, the window hole corresponds to the position of the hole to be plugged on the rigid-flex printed circuit board, and the thickness of the dry film layer is greater than the depth of the recessed groove. In the application, the dry film layer with a thickness greater than the depth of the recessed groove is attached to the rigid-flex printed circuit board. During operation, the resin only enters the hole to be plugged through the window hole and does not flow into the hole not to be plugged and the recessed groove. During polishing, the resin remaining on the surface of the dry film layer is polished together with the dry film layer. The dry film layer remaining in the recessed groove after polishing can be completely removed through a film stripping process. Finally, the selective resin hole plugging operation of the hole to be plugged is realized, and the technical problem of uneven copper layer thickness of the rigid-flex printed circuit board caused by polishing of the resin remaining in the recessed groove in the prior art is effectively solved.

The present specification provides a substrate hole opening method, device and electronic equipment, which can be used in the field of semiconductor device processing. Based on the method, after obtaining a target substrate to be opened, a first type of etching operation can be performed on the first metal layer and the second metal layer on the surface of the core layer of the target substrate respectively, so as to open a matched first hole and a second hole on the first metal layer and the second metal layer respectively; then, a second type of etching operation is performed on the core layer through the first hole and / or the second hole, so as to open a third hole on the core layer, and then a required target hole can be obtained. Thus, a micro-hole with small size and high quality can be accurately opened on the substrate at a relatively small processing cost.

A resin-coated substrate 100 comprising a substrate 20 having an opening 10 and a resin coating 30 covering the substrate 20, the resin coating 30 having a portion 30A that covers the region around the opening 10, and a hanging portion 30B that hangs toward the inside of the opening 10.

A circuit board according to an embodiment includes a first insulating layer, a coating layer disposed on the first insulating layer, and a circuit pattern layer disposed on the coating layer, wherein the circuit pattern layer includes a first metal layer disposed on the coating layer, and a second metal layer disposed on the first metal layer, wherein the coating layer includes a first functional group bonded to the first insulating layer, and a second functional group bonded to the first metal layer.

A semiconductor storage device according to one embodiment comprises a first circuit board and a second circuit board. The first circuit board includes a first section, a second section that is thinner than the first section, and a plurality of first conductive sections on the second section. The second circuit board includes a plurality of second conductive sections. The plurality of second conductive sections overlaps the plurality of first conductive sections when viewed from a first direction, which is a thickness direction of the first circuit board. The plurality of second conductive sections are connected to the plurality of first conductive sections by solder in a one-to-one correspondence.

The invention relates to an electronics assembly (EA) comprising: - a circuit carrier (ST), - a semiconductor component (HB) which is embedded in the circuit carrier (ST) and has an electrical contact surface (KF1), - wherein the contact surface (KF1) of the semiconductor component (HB) is contacted physically and electrically by means of a microvia (MV), the microvia (MV) being sintered onto the contact surface (KF1) of the semiconductor component (HB) in a sintering process from a metallic, in particular copper-containing, sinter paste (SP). The invention also relates to an inverter comprising said electronics assembly (EA) and to a method for manufacturing said electronics assembly (EA)

A circuit assembly (200) is disclosed comprising a substrate (210) and conducting layers (250) on opposing sides of the substrate (210), there being at least one via (220) through the substrate (210), which via (220) forms a conductive path between the conducting layers, wherein the substrate (210) is a foam substrate, and wherein the via (220) is provided with a solid dielectric lining (270) plated with a conducting material (250).

The application discloses a method for embedding conductive glue and a PCB, and comprises the following steps: cutting - inner layer circuit - locally pasting conductive glue - glue pressing - PP slotting - pre-laminating - pressing - drilling - PTH slotting - PTH plating - outer layer circuit - solder mask - character - depth control slotting - surface treatment - plate slotting - electrical measurement - FQC - FQA. The application pastes the conductive glue with a required thickness at a corresponding specified position, then fixes the PP and the substrate through rivets, and then performs pressing, so that the conductive glue can be embedded in the substrate. Then, a metalized slot or a metalized hole is realized through conventional mechanical slotting or mechanical drilling, and then the metal slot hole is slotted along the conductive glue position by a certain length through mechanical depth control slotting, so that a T-shaped half metalized half non-metalized slot hole is formed, the non-metalized half can accommodate components, high thermal conductivity is realized, the lower layer of the electric layer is fully wrapped around the components, and the shielding effect is realized.