3068results about "Printed element electric connection formation" patented technology

A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by shadow mask techniques. Substrates formed in this manner enable significant increases in interconnect density and significant reduction of over-all substrate thickness.

Permanent physical and electrical attachment of electrically conductive contacts of a first component in a RFID device, such as a smart card or smart inlay, is made to the electrically conductive contacts of a second component of the device, for example, a conductive area, such as an antenna. Attachment is achieved by co-depositing metal and electrically conductive hard particles upon the conductive contacts of either the first or second components and then using a non-conductive adhesive to provide permanent bond between the components and their conductive contacts.

A first via land of a wiring layer on a first surface of a first insulation layer that is a rigid layer and a second via land of a wiring layer on a second surface of a second insulation layer that is a flexible layer are electrically and mechanically connected with a conductive pillar pierced through a third insulation layer disposed between the first insulation layer and the second insulation layer. In such a structure, a wiring board that can mount a highly integrated semiconductor device, that is small and thin, and that has high reliability can be accomplished.

A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

An integrated circuit chip having a heat spreader comprising CVD diamond extending along the chip support body and thermal vias extending through the support body in regions free of active devices or functional elements. The thermal vias may thermally conductive and electrically conductive or may be thermally conductive and electrically resistive. The integrated circuit chips may be 3D integrated circuit chips.

The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package, that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain non-sighted individuals. The hermetically sealed electronics package is directly bonded to the flex circuit or electrode by electroplating a biocompatible material, such as platinum or gold, effectively forming a plated rivet-shaped connection, which bonds the flex circuit to the electronics package. The resulting electronic device is biocompatible and is suitable for long-term implantation in living tissue.

A method of manufacturing a fabric article to include electronic circuitry in which a flex circuit is assembled to include conductive traces and pads on a flexible substrate, a fabric article is placed on a rigid surface, and the substrate of the flex circuit is secured to the fabric article. Also disclosed is a fabric article which includes electronic circuitry and an electrically active textile article.

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on one or both of top and bottom surfaces of a monolithic structure can facilitate the formation of selective wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

Deposition of metal in a preferred shape, including coatings on parts, or stand-alone materials, and subsequent heat treatment to provide improved mechanical properties. In particular, the method gives products with relatively high yield strength. The products often have relatively high elastic modulus, and are thermally stable, maintaining the high yield strength at temperatures considerably above 25 DEG C. This technique involves depositing a material in the presence of a selected additive, and then subjecting the deposited material to a moderate heat treatment. This moderate heat treatment differs from other commonly employed "stress relief" heat treatments in using lower temperatures and/or shorter times, preferably just enough to reorganize the material to the new, desired form. Coating a shape and heat treating provides a shaped deposit with improved material properties. Coating a shape with a portion connected to a base and a portion detached therefrom can provide a resilient, conductive contact useful for electronic applications.

A multilayer resin wiring board includes a metal core substrate having a first main surface and a second main surface; a plurality of wiring layers located on the first and second main surfaces of the metal core substrate; a plurality of insulating resin layers, each intervening between the metal core substrate and the wiring layers and between the metal core substrate and the wiring layers and between the wiring layers; and a via formed on the wall of a through hole for connection to the metal core substrate extending through the insulating resin layers and the metal core substrate so as to establish electrical conductivity to the metal core substrate. The metal core substrate has a thin portion which is thinner than the remaining portion of the metal core substrate. The through hole for connection to the metal core substrate is formed through the thin portion by laser machining.

The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

Surface-mount, solder-down sockets are described which permit electronic components such as semiconductor packages to be releasably mounted to a circuit board. Generally, the socket includes resilient contact structures extending from a top surface of a support substrate, and solder-ball (or other suitable) contact structures disposed on a bottom surface of the support substrate. Composite interconnection elements are described for use as the resilient contact structures disposed atop the support substrate. In use, the support substrate is soldered down onto the circuit board, the contact structures on the bottom surface of the support substrate contacting corresponding contact areas on the circuit board. In any suitable manner, selected ones of the resilient contact structures atop the support substrate are connected, via the support substrate, to corresponding ones of the contact structures on the bottom surface of the support substrate.

A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

A wiring board for light-emitting element, comprising a ceramic insulating substrate, and a conductor layer formed on the surface or in the inside of the insulating substrate, and having a mounting region mounting a light-emitting element on one surface of the insulating substrate; wherein the insulating substrate is provided with a heat-conducting pole-like conductor having a thermal conductivity higher than that of said insulating substrate; and the heat-conducting pole-like conductor is extending through the insulating substrate in the direction of thickness thereof from the light-emitting element mounting region of the insulating substrate, and is formed by the co-firing with the insulating substrate. The wiring board is produced inexpensively by co-firing, features excellent heat-radiating performance, is capable of quickly radiating the heat from the light-emitting element when the light-emitting element is mounted, and effectively prevents a decrease in the brightness of the light-emitting element caused by the heat.

Disclosed are a printed wiring board having micro-via holes highly reliable for conduction and a method of making the micro-via hole by providing a coating or sheet of an organic substance containing 3 to 97% by volume of at least one selected from a metal compound powder, a carbon powder or a metal powder having a melting point of at least 900° C. and a bond energy of at least 300 kJ/mol on a copper foil as an outermost layer of a copper-clad laminate having at least two copper layers, or providing a coating or sheet of the same after oxidizing a copper foil as an outermost layer, irradiating the coating or sheet with a carbon dioxide gas laser at an output of 20 to 60 mJ/pulse, thereby removing a micro-via-hole-forming portion of at least the copper foil as the outermost layer, then irradiating micro-via-hole-forming portions of the remaining layers with a carbon dioxide gas laser at an output of 5 to 35 mJ/pulse to make a micro-via hole which does not penetrate through the copper foil in a bottom of the micro-via hole, and electrically connecting the copper foil as the outermost layer and the copper foil in the bottom of the micro-via hole with a metal plating or an electrically conductive coating composition.

A conducting thin-film nanoprobe card fabrication method includes the steps of: (a) arranging nanotubes on a substrate in vertical; (b) covering the nanotubes with a liquid polymeric resin and then hardening the polymeric resin to form a conducting nanomembrane; (c) removing a part of the polymeric resin from the conducting nanomembrane to expose one end of each nanotube to outside; (d) removing the substrate and preparing a ceramic substrate having contacts at one side and metal bumps at the other side and plated through holes electrically respectively connected with the contacts and the metal bumps; (e) mounting the nanomembrane on the ceramic substrate to hold the nanotubes in contact with the contacts of the ceramic substrate, and (f) forming recessed holes in the nanomembrane by etching and inserting a metal rod in each recessed hole to form a respective probe.

The present invention provides a light source module with high efficiency, super bright LEDs featured with efficient heat dissipation. This invention comprises a printed circuit board installed with an LED array which is composed of multiple emitter LEDs. To achieve efficient effect for heat dissipation, there is more than one hole punctured on the printed circuit board right underneath each emitter LED. The surface of each punctured hole is coated with thermal conductive layer such that the accumulative heat generated by the high power LEDs can be effectively dissipated through the conductive layer.

An apparatus for suppressing noise in an electronic device includes a multiple layer structure in which localized arrays of chip capacitors and/or patches around sources of electromagnetic waves are used. The PCB includes multiple conductive layers at different potentials, dielectric layers separating the conductive layers, conductive rods extending between at least two of the conductive layers, and a layer of patches disposed adjacent or on one or more of the conductive layers. The conductive rods are connected to one of the conductive layers and chip capacitors connect the conductive rods to another of the conductive layers. A particular location can be effectively isolated from noise using a few unit cells of an array of patches/capacitors partially or completely surrounding the particular location.

A probing device for electrically contacting with a plurality of electrodes 3, 6 aligned on an object 1 to be tested so as to transfer electrical signal therewith, comprising: a wiring sheet being formed by aligning a plurality of contact electrodes 21, 110b, corresponding to each of said electrodes, each being planted with projecting probes 20, 110a covered with hard metal films on basis of a conductor thin film 41 formed on one surface of an insulator sheet 22 of a polyimide film by etching thereof, while extension wiring 23, 110c for electrically connecting to said each of said contact electrodes being formed on basis of a conductor thin film formed on either said one surface or the other surface opposing thereto of said insulator sheet of the polyimide film; and means for giving contacting pressure for obtaining electrical conduction between said extension wiring and said object to be tested by contacting tips of said projecting contact probe formed onto said each contact electrode through giving pressuring force between said wiring sheet and said object to be tested.

There is presented a high frequency module, in which a recess 2a for mounting power amplifier device is formed on a lower surface of a dielectric substrate 2, and a recess 2b for mounting surface acoustic wave filter is formed on an upper surface of the dielectric substrate 2, and a power amplifier device 4 and a surface acoustic wave filter 8 are mounted through conductive bumps 3a and 3b on the recesses 2a and 2b, respectively. In addition, a through-hole conductor 11 whose one end is exposed at the lower surface of the dielectric substrate 2 is provided between the recesses 2a and 2b. The exposed end of the through-hole conductor 11 is attached to a thermal dissipation conductor 15 on an upper surface of an external electric circuit board 7 through a brazing material 13.

A circuit board design is disclosed that is useful in high-speed differential signal applications uses either a via arrangement or a circuit trace exit structure. A pair of differential signal vias in a circuit board are surrounded by an opening that is formed within a ground plane disposed on another layer of the circuit board. The vias are connected to traces on the circuit board by way of an exit structure that includes two flag portions and associated angled portions that connect the flag portions to circuit board traces. In an alternate embodiment, the circuit board traces that leave the differential signal vias are disposed in one layer of the circuit board above a wide ground strip disposed on another layer of the circuit board.

An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

A front-and-back electrically conductive substrate includes a plurality of posts composed of a material that can be anisotropically etched and having an electrically conductive portion that has at least a first surface and a second surface that communicate with each other, and an insulative substrate that supports the plurality of posts.

A method of manufacturing a substrate with through electrodes of the present invention, includes the steps of forming a metal post over a temporal substrate in a state that the metal post is peelable from the temporal substrate, placing a normal substrate in which a through hole is provided in a position corresponding to the metal post over the temporal substrate, whereby inserting the metal post on the temporal substrate into the through hole in the normal substrate, and obtaining a through electrode that is formed of the metal post passing through the normal substrate by peeling the temporal substrate from the metal post.

A metal layer 18 is sandwiched between insulating layers 14 and 20 so that required strength is maintained. Hence it follows that the thickness of a core substrate 30 can be reduced and, therefore, the thickness of a multi-layer printed circuit board can be reduced. Formation of non-penetrating openings 22 which reach the metal layer 18 in the insulating layers 14 and 20 is simply required. Therefore, small non-penetrating openings 22 can easily be formed by applying laser beams. Thus, through holes 36 each having a small diameter can be formed.

A stereoscopically connected structure is made up of a first circuit board and a second circuit board which are mounted with other electronic components, and a relay board having a recess which is mounted with an electronic component and is provided with a lead-out wiring extending from the electronic component, and also having a land part to be connected with the lead-out wiring on one of the surfaces of the relay board that face the first circuit board and second circuit board. Thus the relay board can mount the electronic component thereon as well as connect the first circuit board and the second circuit board, thereby achieving high density mounting.

Connectors for electronic devices are described. The connector is formed by ball bonding a plurality of wires to contact locations on a fan out substrate surface. The wires are cut off leaving stubs. A patterned polymer sheet having electrical conductor patterns therein is disposed over the stubs which extend through holes in the sheet. The ends of the wires are flattened to remit the polymer sheet in place. The wire is connected to an electrical conductor on the polymer sheet which is converted to a contact pad on the polymer sheet. A second wire is ball bonded to the pad on the polymer sheet and cut to leave a second stub. The polymer sheet is laser cut so that each second stub is free to move independently of the other second studs. The ends of the second stubs are disposed against contact locations of an electronic device, such as an FC chip, to test the electronic device.

A multilayer wiring board assembly component comprises: an insulating substrate component (the insulating resin layer 111); a conductive layer 112 formed on one surface of said insulating substrate component 111 in the form of an electrode pattern; an adhesive layer 113 formed on the other surface of said insulating substrate component 111; and a conductive resin composition 115 with which is filled a through hole passing through said insulating substrate component 111, said adhesive layer and said conductive layer in order to make interlayer interconnection. The bore diameter of the conductive layer portion 114b of the through hole 114 is smaller than the bore diameter of the insulating resin layer portion and the adhesive layer portion 114a to establish electrical connection between the conductive resin composition 115 and the conductive layer 112 by the rare surface 112a of the conductive layer 112.

A pre-solder structure on a semiconductor package substrate and a method for fabricating the same are proposed. A plurality of conductive pads are formed on the substrate, and a protective layer having a plurality of openings for exposing the conductive pads is formed over the substrate. A conductive seed layer is deposited over the protective layer and openings. A patterned resist layer is formed on the seed layer and has openings corresponding in position to the conductive pads. A plurality of conductive pillars and a solder material are deposited in sequence in each of the openings. The resist layer and the seed layer not covered by the conductive pillars and the solder material are removed. The solder material is subject to a reflow-soldering process to form pre-solder bumps covering the conductive pillars.

The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package, that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain non-sighted individuals. The hermetically sealed electronics package is directly bonded to the flex circuit or electrode by one of several methods, including attachment by an electrically conductive adhesive, such as epoxy or polyimide, containing platinum metal flake in biocompatible glue; diffusion bonding of platinum bumps covered by an insulating layer; thermal welding of wire staples; or an integrated interconnect fabrication. The resulting electronic device is biocompatible and is suitable for long-term implantation in living tissue.