36results about How to "Excellent characteristic frequency" patented technology

The invention discloses a dual-strain bipolar complementary metal-oxide semiconductor (BiCMOS) integration device based on a silicon on insulator (SOI) substrate and a preparation method thereof. The preparation method comprises following steps that a negative-silicon (N-Si) layer, a positive-silicon germanium (P-SiGe) layer and an N-Si layer continuously grow on the SOI substrate, a deep groove isolator is prepared, a collector zone shallow groove isolator and a base zone shallow groove isolator are prepared, a collector zone is photo-etched, phosphonium ions are injected to form a collector electrode, a base electrode and a transmitter electrode, and a SiGe heterojunction bipolar transistor (HBT) device is formed; a strain SiGe material grow on the substrate, an N-channel MOS (NMOS) device active region and a P-channel MOS (PMOS) device active region are formed, a pseudo grid is prepared, a source drain region of the NMOS and the PMOS devices is respectively generated in a self-aligning way, the pseudo grid is eliminated, a lanthanum oxide (La2O3) material is prepared in a pressing groove at the pseudo grid to form a grid medium and metal tungsten (W) to form a grid electrode, a lead is photo-etched, and a dual-strain plane BiCMOS integration device and a circuit based on the SOI substrate are formed. According to the method, the characteristic that a hole mobility of the strain SiGe material is higher than that of the bulk-Si material is adequately utilized to prepare the dual-strain plane BiCMOS integration circuit based on the SOI substrate, so that the performance of the existing analog and digital-analog mixed integrated circuit is greatly improved.

The invention discloses a crystal plane-based tri-polycrystal-plane Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and a preparation method of the device. The preparation process is as follows: preparing an SOI (Silicon On Insulator) substrate; growing N type Si epitaxy and preparing a deep-trench isolator so as to form a collector electrode contact region and a nitride side wall, etching a window in a base region, growing a SiGe base region, conducting photoetching on a collector electrode window, depositing N type Poly-Si, and preparing an emitting electrode and the collector electrode to form an HBT (Heterojunction Bipolar Transistor) device; etching a deep trench in an NMOS (N-Channel Metal Oxide Semiconductor) device region, selectively growing a strain Si epitaxial layer with a crystal plane (100) to prepare an NMOS device with a Si channel; selectively growing a strain SiGe epitaxial layer with a crystal plane (110) to prepare a PMOS (P-Channel Metal Oxide Semiconductor) device with a SiGe channel, and thus forming the crystal plane-based tri-polycrystal-plane Bin CMOS integrated device and a circuit. According to the crystal plane-based tri-polycrystal-plane Bi CMOS integrated device and the preparation method, the characteristics that the electronic mobility of tensile strain Si material is higher than that of Si material, the electronic mobility of strain SiGe material is higher than of that of body Si material, and the electronic mobility is anisotropic are utilized, and based on the SOI substrate, the plane Bi CMOS integrated circuit is prepared, and the performance of the Bi CMOS integrated device is enhanced.

The invention discloses a silicon-on-insulator silicon germanium heterojunction bipolar transistor (SOI SiGe HBT0 planar integrated device and a preparation method thereof. The preparation method comprises following steps of continuously growing N-channel silicon (N-Si), P-channel silicon germanium (P-SiGe) and an N-channel silicon (N-Si) layer to deposit a dielectric layer to prepare shallow-trench isolation, photo-etching a collector region shallow-trench isolation area, preparing a collector region shallow-trench isolation, etching and depositing a dielectric layer, photo-etching a base-region shallow-trench isolation area, preparing a base-region shallow-trench isolation, photo-etching a collector region and injecting phosphorous ions to form a collector electrode contact region, photo-etching a base region and injecting boron ions to form a base electrode contact area, finally forming a SiGe HBT device, finally photo-etching a transmitting region lead hole, a base region lead holeand a collector region lead hole, metalizing, photo-etching leads, and forming an HBT integrated circuit with the thickness of the base region of 20 to 60nm. The technical method provided by the invention is compatible with the processing technique of the traditional CMOS integrated circuit, so that under the situation that the fund and the equipment investment are small, the SOI-based bipolar complementary metal-oxide semiconductor (BiCMOS) device and an integrated circuit are prepared, and the performance of the traditional analog and digital mixed integrated circuit is greatly improved.

The invention discloses a tri-strain SOI (Silicon On Insulator) Si based BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) integrated device based on crystal face selection and a preparation method thereof. The preparation method comprises the steps of: preparing a SOI substrate; continuously growing an N-Si layer, a P-SiGe layer and an N-Si layer and depositing a dielectric layer to prepare a shallow trench isolation region of a collecting region and a shallow trench isolation region of a base region; carrying out photo-etching on the collecting region and phosphorous ion injection, forming a collecting electrode contact region and a base electrode contact region and forming a SiGe HBT (Heterojunction Bipolar Transistor) device; etching the deep trench in an NMOS (N-channel Metal Oxide Semiconductor) region, selectively growing a strain Si epitaxial layer with the crystal face (100), and preparing a strain Si channel NMOS device; selectively growing a strain Si epitaxial layer with the crystal face (110) in an active region of a PMOS (P-channel Metal Oxide Semiconductor), and preparing a compression strain SiGe channel PMOS device; and forming the tri-strain SOI Si based BiCMOS integrated device based on crystal face selection and a circuit. According to the tri-strain SOI Si based BiCMOS integrated device based on crystal face selection and the preparation method of the tri-strain SOI Si based BiCMOS integrated device based on crystal face selection, a performance-enhanced planar BiCMOS integrated circuit is prepared based on the SOI substrate by means of characteristics that the electronic mobility of the strain Si material is higher than that of the body strain Si material and the hole mobility of the compression strain Si material is higher than that of the body strain Si material and the mobility is anisotropic adequately.

The invention discloses an SOI (Silicon-On-Insulator)-BJT (Bipolar Junction Transistor) double-strain-plane Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and a preparation method of the device. The preparation process is as follows: growing an N type Si epitaxial collector region on an SOI substrate sheet, preparing a deep-trench isolator, and manufacturing a conventional Si bipolar transistor in a bipolar device region; etching a deep trench in an active region of an MOS (Metal Oxide Semiconductor) device by utilizing a dry etching process, and respectively and selectively growing a P type Si layer, a P type SiGe gradual change layer, a P type SiGe layer, a P type strain Si layer which are taken as an active region of an NMOS (N-Channel Metal Oxide Semiconductor) device, an N type Si layer, an N type strain SiGe layer and an N type Si cap layer which are taken as an active region of a PMOS (P-Channel Metal Oxide Semiconductor) device in the trench in an epitaxial manner; and preparing a virtual grid electrode, respectively injecting LDD (Laser Detector Diode) of the MOS device, depositing SiO2, preparing a side wall, and conducting self alignment to form source drain of the NMOS device and the PMOS device; and etching a virtual grid, depositing a SiON grid dielectric layer and a W-TiN composite grid, and thus finally forming the Bi CMOS integrated device with the channel being 22-45nm. According to the method, the tensile strain Si with high electronic mobility and compressive strain SiGe with high hole mobility are respectively taken as conducting channels of the NMOS device and the PMOS device, so that the performances of the Bi CMOS integrated device and a circuit are improved greatly.

The invention discloses a double-polysilicon planar SOI BiCMOS integrated device and a preparation method. The preparation method growing N-Si on a SOI substrate as the collector region of a bipolar device, etching a base region by lithography, growing P-SiGe, i-Si and i-Poly-Si on the base region, preparing deep trench isolation, and preparing an emitter, a base and a collector to obtain a SiGe HBT (heterojunction bipolar transistor) device; etching a trench on the active region of an NMOS (n-channel metal oxide semiconductor) device by lithography, and growing four material layers in the trench; etching a trench on the active region of a PMOS (p-channel metal oxide semiconductor) device, growing three material layers in the trench, and preparing a drain and a gate on the active region of MOS (metal oxide semiconductor) to obtain an MOS device; and etching leads by lithography to obtain the double-polysilicon planar SOI BiCMOS integrated device and circuit. According to the invention, the double-polysilicon planar SOI BiCMOS integrated circuit prepared by the method is enhanced in performance by fully utilizing the characteristics that the electron mobility of a tensile strained Si material is higher than that of a bulk Si material and that the hole mobility of a compressive strained SiGe material is higher than that of the bulk Si material.

The invention discloses a double poly-crystal plane strain BiCMOS integrated device based on a SOI (Silicon On Insulator) substrate and a preparation method. The preparation method comprises the following steps: preparing a deep slot isolator on the SOI substrate; forming a collector contact region, a nitride side wall and a base region window; growing SiGe and Poly-Si on the base region, thereby forming a SiGe HBT (Heterojunction Bipolar Transistor) device; etching a slot on a NMOS (N-channel Metal Oxide Semiconductor) device active region, preparing a grid dielectric layer and a grid poly-crystal on the NMOS device active region, thereby forming a NMOS device; etching a slot on a PMOS (P-channel Metal Oxide Semiconductor) device active region and preparing a drain and a grid on the PMOS device active region, thereby forming a PMOS device; and photo-etching a lead, thereby preparing a BiCMOS integrated device and a circuit. According to the preparation method, a BiCMOS integrated circuit with an enhanced property is prepared by adopting a self-aligning technology and fully utilizing the characteristics that the electronic mobility of a spreading strain Si material is higher than that of a semiconductor Si material and the hole mobility of a compressive strain SiGe material is higher than that of the semiconductor Si material.

The invention discloses a tri-polycrystal strain SiGe BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) integrated device and a preparation method. The preparation method comprises the steps of: firstly, preparing an SOI (Silicon On Insulator) substrate; etching a bipolar device region; preparing a tri-polycrystal SiGe HBT (Heterojunction Bipolar Transistor) device in the region; then photoetching an MOS (Metal Oxide Semiconductor) active region; continuously growing an Si buffer layer, a strain SiGe layer and an intrinsic Si layer in the region; respectively forming active regions of an NMOS (N-channel Metal Oxide Semiconductor) device and a PMOS (P-channel Metal Oxide Semiconductor) device; depositing SiO2 and polycrystalline silicon on the active region of the MOS device; preparing a pseudo grid by etching; forming a light dope source drain and a source drain of the MOS device by a self-aligning process; then removing the pseudo grid; preparing grid dielectric lanthanum oxide and tungsten to form the grid; and finally metalizing and photoetching a lead to prepare the integrated device and a circuit. The preparation process provided by the the invention adopts the self-aligning process, and the light dope source drain structure is adopted in the MOS structure so that the influence of hot carriers on the performance of the device is effectively inhibited and the reliability of the device is improved.

The invention discloses a manufacturing method of a mixed crystal plane strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor Transistor) integrated device and a circuit. The method comprises the steps of manufacturing an SOI (Silicon on Insulator) substrate, with the base material of the upper layer being a (110) crystal face, and the base material of the lower layer being a (100) crystal face; manufacturing a conventional Si (Silicon) bipolar transistor in a bipolar device area; selectively growing a strain Si epitaxial layer with the crystal face as (100) in an NMOS (N-channel Metal Oxide Semiconductor) device area to manufacture a strain Si channel NMOS device; selectively growing a strain SiGe (Silicon Germanium) epitaxial layer with the crystal face as (110) in a PMOS (P-channel Metal Oxide Semiconductor) device active area to manufacture a compression strain SiGe channel PMOS device of a channel; and photoetching a lead, so as to form the mixed crystal plane strain BiCMOS integrated device with a 22-45nm MOS (Metal Oxide Semiconductor) device conducting channel. According to the invention, the characteristics that the electron mobility of a tensile strain Si material is higher than the electron mobility of a body Si material, and the electron mobility of a compression strain SiGe material is higher than the electron mobility of the body Si material, and the characteristic of mobility aeolotropy are made full use of to manufacture the mixed crystal plane strain BiCMOS integrated device and the circuit with enhanced performances based on the SOI substrate.

The invention discloses a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device on the basis of a SOI (Silicon On Insulator) substrate and a preparation method. The preparation method comprises the following steps of: firstly, continuously growing an N-Si layer, a P-SiGe layer and an N-Si layer on the SOI substrate, depositing a medium layer, preparing a collector region shallow-trench isolation and a base region shallow-trench isolation, photoetching a collector region and implanting phosphorous ions into the collector region to form a collector electrode contact region, photoetching a base region and implanting boron ions into the base region to form a base electrode contact region and forming a SiGe HBT (Heterojunction Bipolar Trthissistor) device; photoetching active region grooves of NMOS (N-channel Metal Oxide Semiconductor) and PMOS (P-channel Metal Oxide Semiconductor) devices, respectively and continuously growing a Si buffer layer, a gradient SiGe layer, a fixed component SiGe layer and an N-type strain Si groove layer and a Si buffer layer, a gradient SiGe layer, a fixed component SiGe layer, a strain Si P-LDD (Laser Detector Diode) layer, a strain Si groove layer, a strain Si P-LDD layer and the like in the active region grooves and preparing a drain electrode and a grid electrode of the PMOS device to form the PMOS device; and preparing a gate dielectric layer and gate polycrystal of the NMOS device to form the NMOS device so as to form the BiCMOS integrated device and a circuit. According to the invention, the performance-enhanced BiCMOS integrated circuit is prepared at a temperature of 600 to 800 DEG C by sufficiently utilizing the characteristic of anisotropism of the mobility ratio of the strain Si material.

The invention is suitable for the field of semiconductor integrated circuit, and provides a tri-polycrystal SOI (Silicon-On-Insulator) SiGe HBT (Heterojunction Bipolar Transistor) integrated device and a preparation method thereof. The preparation method comprises the following steps: continuously growing N-Si, P-SiGe, i-Si, i-Poly-Si on an SOI substrate; depositing a dielectric layer; preparing a shallow-trench isolator; photoetching a collecting zone shallow-trench isolation region; preparing a collecting zone shallow-trench isolator; etching and depositing the dielectric layer; photoetching a base region shallow-trench isolation region; preparing a base region shallow-trench isolator; photoetching a collector and implanting phosphonium ions; photoetching a base electrode and implanting boron ions; photoetching an emitter and implanting phosphonium ions; forming the contact regions of the collector, the base electrode and the emitter; and finally forming the HBT device to compose HBT integrated circuit in which the thickness of the base region is 20-60nm. The technique provided by the invention is compatible with the processing technique of the existing CMOS integrated circuit; under the condition of very few fund and equipment investments, the BiCMOS integrated device and circuit based on SOI can be prepared so that the performance of the existing analog and digital-analog hybrid integrated circuit is greatly improved.