36results about How to "Excellent characteristic frequency" patented technology

The invention discloses a crystal plane-based tri-polycrystal-plane Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and a preparation method of the device. The preparation process is as follows: preparing an SOI (Silicon On Insulator) substrate; growing N type Si epitaxy and preparing a deep-trench isolator so as to form a collector electrode contact region and a nitride side wall, etching a window in a base region, growing a SiGe base region, conducting photoetching on a collector electrode window, depositing N type Poly-Si, and preparing an emitting electrode and the collector electrode to form an HBT (Heterojunction Bipolar Transistor) device; etching a deep trench in an NMOS (N-Channel Metal Oxide Semiconductor) device region, selectively growing a strain Si epitaxial layer with a crystal plane (100) to prepare an NMOS device with a Si channel; selectively growing a strain SiGe epitaxial layer with a crystal plane (110) to prepare a PMOS (P-Channel Metal Oxide Semiconductor) device with a SiGe channel, and thus forming the crystal plane-based tri-polycrystal-plane Bin CMOS integrated device and a circuit. According to the crystal plane-based tri-polycrystal-plane Bi CMOS integrated device and the preparation method, the characteristics that the electronic mobility of tensile strain Si material is higher than that of Si material, the electronic mobility of strain SiGe material is higher than of that of body Si material, and the electronic mobility is anisotropic are utilized, and based on the SOI substrate, the plane Bi CMOS integrated circuit is prepared, and the performance of the Bi CMOS integrated device is enhanced.

The invention discloses a tri-strain SOI (Silicon On Insulator) Si based BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) integrated device based on crystal face selection and a preparation method thereof. The preparation method comprises the steps of: preparing a SOI substrate; continuously growing an N-Si layer, a P-SiGe layer and an N-Si layer and depositing a dielectric layer to prepare a shallow trench isolation region of a collecting region and a shallow trench isolation region of a base region; carrying out photo-etching on the collecting region and phosphorous ion injection, forming a collecting electrode contact region and a base electrode contact region and forming a SiGe HBT (Heterojunction Bipolar Transistor) device; etching the deep trench in an NMOS (N-channel Metal Oxide Semiconductor) region, selectively growing a strain Si epitaxial layer with the crystal face (100), and preparing a strain Si channel NMOS device; selectively growing a strain Si epitaxial layer with the crystal face (110) in an active region of a PMOS (P-channel Metal Oxide Semiconductor), and preparing a compression strain SiGe channel PMOS device; and forming the tri-strain SOI Si based BiCMOS integrated device based on crystal face selection and a circuit. According to the tri-strain SOI Si based BiCMOS integrated device based on crystal face selection and the preparation method of the tri-strain SOI Si based BiCMOS integrated device based on crystal face selection, a performance-enhanced planar BiCMOS integrated circuit is prepared based on the SOI substrate by means of characteristics that the electronic mobility of the strain Si material is higher than that of the body strain Si material and the hole mobility of the compression strain Si material is higher than that of the body strain Si material and the mobility is anisotropic adequately.

The invention discloses a double poly-crystal plane strain BiCMOS integrated device based on a SOI (Silicon On Insulator) substrate and a preparation method. The preparation method comprises the following steps: preparing a deep slot isolator on the SOI substrate; forming a collector contact region, a nitride side wall and a base region window; growing SiGe and Poly-Si on the base region, thereby forming a SiGe HBT (Heterojunction Bipolar Transistor) device; etching a slot on a NMOS (N-channel Metal Oxide Semiconductor) device active region, preparing a grid dielectric layer and a grid poly-crystal on the NMOS device active region, thereby forming a NMOS device; etching a slot on a PMOS (P-channel Metal Oxide Semiconductor) device active region and preparing a drain and a grid on the PMOS device active region, thereby forming a PMOS device; and photo-etching a lead, thereby preparing a BiCMOS integrated device and a circuit. According to the preparation method, a BiCMOS integrated circuit with an enhanced property is prepared by adopting a self-aligning technology and fully utilizing the characteristics that the electronic mobility of a spreading strain Si material is higher than that of a semiconductor Si material and the hole mobility of a compressive strain SiGe material is higher than that of the semiconductor Si material.

The invention discloses a tri-polycrystal strain SiGe BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) integrated device and a preparation method. The preparation method comprises the steps of: firstly, preparing an SOI (Silicon On Insulator) substrate; etching a bipolar device region; preparing a tri-polycrystal SiGe HBT (Heterojunction Bipolar Transistor) device in the region; then photoetching an MOS (Metal Oxide Semiconductor) active region; continuously growing an Si buffer layer, a strain SiGe layer and an intrinsic Si layer in the region; respectively forming active regions of an NMOS (N-channel Metal Oxide Semiconductor) device and a PMOS (P-channel Metal Oxide Semiconductor) device; depositing SiO2 and polycrystalline silicon on the active region of the MOS device; preparing a pseudo grid by etching; forming a light dope source drain and a source drain of the MOS device by a self-aligning process; then removing the pseudo grid; preparing grid dielectric lanthanum oxide and tungsten to form the grid; and finally metalizing and photoetching a lead to prepare the integrated device and a circuit. The preparation process provided by the the invention adopts the self-aligning process, and the light dope source drain structure is adopted in the MOS structure so that the influence of hot carriers on the performance of the device is effectively inhibited and the reliability of the device is improved.

The invention is suitable for the field of semiconductor integrated circuit, and provides a tri-polycrystal SOI (Silicon-On-Insulator) SiGe HBT (Heterojunction Bipolar Transistor) integrated device and a preparation method thereof. The preparation method comprises the following steps: continuously growing N-Si, P-SiGe, i-Si, i-Poly-Si on an SOI substrate; depositing a dielectric layer; preparing a shallow-trench isolator; photoetching a collecting zone shallow-trench isolation region; preparing a collecting zone shallow-trench isolator; etching and depositing the dielectric layer; photoetching a base region shallow-trench isolation region; preparing a base region shallow-trench isolator; photoetching a collector and implanting phosphonium ions; photoetching a base electrode and implanting boron ions; photoetching an emitter and implanting phosphonium ions; forming the contact regions of the collector, the base electrode and the emitter; and finally forming the HBT device to compose HBT integrated circuit in which the thickness of the base region is 20-60nm. The technique provided by the invention is compatible with the processing technique of the existing CMOS integrated circuit; under the condition of very few fund and equipment investments, the BiCMOS integrated device and circuit based on SOI can be prepared so that the performance of the existing analog and digital-analog hybrid integrated circuit is greatly improved.