Double-polysilicon planar SOI (silicon on insulator) BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method

An integrated device, double polycrystalline technology, applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve the problems of low mechanical strength, high cost, incompatibility, wide application and development, etc.

Inactive Publication Date: 2012-10-17
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although GaAs and InP-based compound devices have superior frequency characteristics, their preparation process is more complicated than Si process, high cost, difficult to prepare large-diameter single

Method used

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  • Double-polysilicon planar SOI (silicon on insulator) BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0114] Embodiment 1: Preparation of conductive channel 22nm double polycrystalline planar SOI BiCMOS integrated device and circuit,

[0115] Specific steps are as follows:

[0116] Step 1, epitaxial material preparation.

[0117] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , the thickness is 300nm, and the upper layer material is a doping concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;

[0118] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 250nm on the upper layer of Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 ;

[0119] (1c) Deposit a layer of SiO with a thickness of 200nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD). 2 layer;

[0120](1d) Deposit a layer of SiN with a thickness of 100 nm on the surf...

Embodiment 2

[0178] Embodiment 2: Prepare conductive channel 30nm double-polycrystalline planar SOI BiCMOS integrated device and circuit, the specific steps are as follows:

[0179] Step 1, epitaxial material preparation.

[0180] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 350nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;

[0181] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 270nm on the upper layer of Si material at 700°C, as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 ;

[0182] (1c) Deposit a layer of SiO with a thickness of 240nm on the surface of the substrate at 700°C by chemical vapor deposition (CVD). 2 layer;

[0183] (1d) Deposit a layer of SiN with a thickness of 150 nm on the surface of the s...

Embodiment 3

[0241] Embodiment 3: prepare the dual-polycrystalline planar SOI BiCMOS integrated device and circuit of 45nm conductive channel, the specific steps are as follows:

[0242] Step 1, epitaxial material preparation.

[0243] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;

[0244] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 300nm on the upper Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 ;

[0245] (1c) Deposit a layer of SiO with a thickness of 300nm on the surface of the substrate at 800°C by chemical vapor deposition (CVD). 2 layer;

[0246] (1d) Deposit a SiN layer with a thickness of 200nm on the surface of the substrate at 800°C by c...

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Abstract

The invention discloses a double-polysilicon planar SOI BiCMOS integrated device and a preparation method. The preparation method growing N-Si on a SOI substrate as the collector region of a bipolar device, etching a base region by lithography, growing P-SiGe, i-Si and i-Poly-Si on the base region, preparing deep trench isolation, and preparing an emitter, a base and a collector to obtain a SiGe HBT (heterojunction bipolar transistor) device; etching a trench on the active region of an NMOS (n-channel metal oxide semiconductor) device by lithography, and growing four material layers in the trench; etching a trench on the active region of a PMOS (p-channel metal oxide semiconductor) device, growing three material layers in the trench, and preparing a drain and a gate on the active region of MOS (metal oxide semiconductor) to obtain an MOS device; and etching leads by lithography to obtain the double-polysilicon planar SOI BiCMOS integrated device and circuit. According to the invention, the double-polysilicon planar SOI BiCMOS integrated circuit prepared by the method is enhanced in performance by fully utilizing the characteristics that the electron mobility of a tensile strained Si material is higher than that of a bulk Si material and that the hole mobility of a compressive strained SiGe material is higher than that of the bulk Si material.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular prepares a double-polycrystalline planar SOI BiCMOS integrated device and a preparation method. Background technique [0002] Integrated circuits are the cornerstone and core of the economic development of an information society. Just as the American engineering and technology circle recently named the fifth electronic technology among the 20 greatest engineering and technological achievements in the world in the 20th century, "from vacuum tubes to semiconductors and integrated circuits, they have become the cornerstone of intelligent work in various industries today." Integrated circuits. It is one of the typical products that can best reflect the characteristics of knowledge economy. At present, the electronic information industry based on integrated circuits has become the world's largest industry. With the development of integrated circuit technol...

Claims

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Application Information

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IPC IPC(8): H01L27/12H01L21/84H01L29/423H01L21/28H01L21/8249
Inventor 张鹤鸣王斌宣荣喜宋建军胡辉勇舒斌戴显英郝跃
Owner XIDIAN UNIV
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