Layout method of SiC JBS device

Abstract

The invention provides a layout method of a SiC JBS device, which comprises the following steps of: growing an epitaxial layer on the crystal surface of a silicon carbide substrate, and dividing an active region with a rectangular structure on the epitaxial layer, arranging a terminal protection region at the periphery of the active region, arranging a plurality of P-type regions in the active region, arranging the plurality of P-type regions in a multi-row and multi-column staggered manner, implanting ions into each P-type region, and arranging Schottky contact regions between the P-type regions, and depositing an ohmic contact metal layer on the back surface of the silicon carbide substrate to generate the SiC JBS device. The plurality of P-type regions are arranged in the SiC JBS devicein a multi-row and multi-column staggered manner, so that the reverse breakdown characteristic of the SiC JBS device is ensured, the Schottky barrier region area is increased, and the conduction capability is improved.

Description

technical field [0001] The invention relates to the field of semiconductor devices and their manufacture, in particular to a layout method for SiC JBS devices. Background technique [0002] High-power diodes are an important branch of semiconductor power electronic devices, mainly including Schottky Barrier Diodes (Schottky Barrier Diode, SBD), Junction Barrier Schottky Diodes (JBS), and PiN diodes. In the field of silicon carbide (SiC) with high voltage and high current, SiC SBD diodes are widely used due to their low forward voltage drop, but the existence of Schottky barriers makes the reverse leakage current of SBD diodes relatively large, limiting for its high-voltage applications. Although the SiC PiN diode has a high blocking voltage, due to the conductance modulation effect, the energy loss of the SiC PiN diode is relatively large during reverse recovery. [0003] Therefore, in order to solve the above problems, the junction barrier Schottky diode structure is usua...

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Problems solved by technology

At present, in order to increase the conduction current of the device, the way of multi-cell parallel connection is usually adopted. Different cell shapes and layouts will affect the breakdown voltage and on-resistance, but the common square array, because the diagonal P+ area spacing is greater than The distance between adjacent P+ regions cannot effectively reduce the Schottky surface electric field in the middle region, which affects the pinch-off ability of the Schottky junction during reverse bias; and the strip structure is difficult to achieve ideal uniformity in terms of processing technology , so it is worth studying to provide a SiC JBS device that is easy to implement and has high precision in the process

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