A hybrid crystal plane plane strain bicmos integrated device and preparation method

A plane strain, mixed crystal plane technology, applied in semiconductor/solid state device manufacturing, electric solid state devices, semiconductor devices, etc., can solve the problem that the mobility cannot be optimized at the same time, the limitation, the low mobility of Si material carrier materials, etc. question

Inactive Publication Date: 2016-03-30
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] As early as the 1950s, it has been found that applying stress on silicon materials will change the mobility of electrons and holes, thereby changing the performance of NMOS and PMOS devices prepared on semiconductor materials; but electrons and holes do not Does not always respond to the same stress in the same way; at the same time, NMOS devices and PMOS devices are prepared on the same crystal plane, and their mobility cannot be optimized at the same time
[0007] Due to the low mobility of Si materials, the performance of integrated circuits manufactured by SiBiCMOS technology, especially the frequency performance, is greatly limited.

Method used

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  • A hybrid crystal plane plane strain bicmos integrated device and preparation method

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0104] Embodiment 1: Prepare 22nm mixed plane strain BiCMOS integrated device and circuit, the specific steps are as follows:

[0105] Step 1, SOI substrate material preparation.

[0106] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0107] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;

[0108] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

[0109] (1d) SiO on the surface of the lower and upper substrate materials after polishing 2 ...

Embodiment 2

[0156] Embodiment 2: Prepare 30nm mixed crystal plane plane strain BiCMOS integrated device and circuit, the specific steps are as follows:

[0157] Step 1, SOI substrate material preparation.

[0158] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0159] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;

[0160] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;

[0161] (1d) SiO on the surface of the l...

Embodiment 3

[0208] Embodiment 3: Prepare 45nm mixed plane strain BiCMOS integrated device and circuit, the specific steps are as follows:

[0209] Step 1, SOI substrate material preparation.

[0210] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0211] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si wafer with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;

[0212] (1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;

[0213] (1d) SiO on the surface of the lower and upper substrate materials after polishing 2 Relatively cl...

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Abstract

The invention discloses a manufacturing method of a mixed crystal plane strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor Transistor) integrated device and a circuit. The method comprises the steps of manufacturing an SOI (Silicon on Insulator) substrate, with the base material of the upper layer being a (110) crystal face, and the base material of the lower layer being a (100) crystal face; manufacturing a conventional Si (Silicon) bipolar transistor in a bipolar device area; selectively growing a strain Si epitaxial layer with the crystal face as (100) in an NMOS (N-channel Metal Oxide Semiconductor) device area to manufacture a strain Si channel NMOS device; selectively growing a strain SiGe (Silicon Germanium) epitaxial layer with the crystal face as (110) in a PMOS (P-channel Metal Oxide Semiconductor) device active area to manufacture a compression strain SiGe channel PMOS device of a channel; and photoetching a lead, so as to form the mixed crystal plane strain BiCMOS integrated device with a 22-45nm MOS (Metal Oxide Semiconductor) device conducting channel. According to the invention, the characteristics that the electron mobility of a tensile strain Si material is higher than the electron mobility of a body Si material, and the electron mobility of a compression strain SiGe material is higher than the electron mobility of the body Si material, and the characteristic of mobility aeolotropy are made full use of to manufacture the mixed crystal plane strain BiCMOS integrated device and the circuit with enhanced performances based on the SOI substrate.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a mixed crystal plane strain mixed crystal plane strain BiCMOS integrated device and a preparation method. Background technique [0002] In the contemporary era of highly developed information technology, microelectronic technology represented by integrated circuits is the key to information technology. As the fastest-growing, most influential and most widely used technology in human history, integrated circuits have become an important symbol to measure a country's scientific and technological level, comprehensive national strength and national defense strength. [0003] "Moore's Law", which has had a huge impact on the development of the microelectronics industry, states that the number of transistors on an integrated circuit chip doubles approximately every 18 months, and the performance also doubles. For more than 40 years, the world's m...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/06H01L21/8249
Inventor 张鹤鸣李妤晨宋建军胡辉勇宣荣喜吕懿舒斌郝跃
Owner XIDIAN UNIV
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