A hybrid crystal plane plane strain bicmos integrated device and preparation method
A plane strain, mixed crystal plane technology, applied in semiconductor/solid state device manufacturing, electric solid state devices, semiconductor devices, etc., can solve the problem that the mobility cannot be optimized at the same time, the limitation, the low mobility of Si material carrier materials, etc. question
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Embodiment 1
[0104] Embodiment 1: Prepare 22nm mixed plane strain BiCMOS integrated device and circuit, the specific steps are as follows:
[0105] Step 1, SOI substrate material preparation.
[0106] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0107] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;
[0108] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0109] (1d) SiO on the surface of the lower and upper substrate materials after polishing 2 ...
Embodiment 2
[0156] Embodiment 2: Prepare 30nm mixed crystal plane plane strain BiCMOS integrated device and circuit, the specific steps are as follows:
[0157] Step 1, SOI substrate material preparation.
[0158] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0159] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;
[0160] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;
[0161] (1d) SiO on the surface of the l...
Embodiment 3
[0208] Embodiment 3: Prepare 45nm mixed plane strain BiCMOS integrated device and circuit, the specific steps are as follows:
[0209] Step 1, SOI substrate material preparation.
[0210] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0211] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si wafer with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;
[0212] (1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;
[0213] (1d) SiO on the surface of the lower and upper substrate materials after polishing 2 Relatively cl...
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