Silicon-on-insulator silicon germanium heterojunction bipolar transistor (SOI SiGe HBT) planar integrated device and preparation method thereof
An integrated device and planar technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as poor heat dissipation performance, low mechanical strength, and high cost
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Embodiment 1
[0074] Embodiment 1: prepare the SOI SiGe HBT planar integrated device and circuit method with a base thickness of 20nm, the specific steps are as follows:
[0075] Step 1, epitaxial material preparation.
[0076] (1a) Select an SOI substrate, the support material 1 of the lower layer of the substrate is Si, and the middle layer 2 is SiO 2 , the thickness is 150nm, and the upper layer material 3 has a doping concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;
[0077] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 50nm on the upper Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 ;
[0078] (1c) Using chemical vapor deposition (CVD), grow a layer of SiGe layer with a thickness of 20nm on the substrate at 600°C. As the base region, the Ge composition of this layer is 15%, and the doping concentration is 5×10 18 cm -3 ;
[0079] (1d) Usi...
Embodiment 2
[0109] Embodiment 2: prepare the SOI SiGe HBT planar integrated device and circuit method with a base thickness of 40nm, the specific steps are as follows:
[0110] Step 1, epitaxial material preparation.
[0111] (1a) Select an SOI substrate, the support material 1 of the lower layer of the substrate is Si, and the middle layer 2 is SiO 2 , the thickness is 300nm, and the upper material 3 has a doping concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;
[0112] (1b) Using the method of chemical vapor deposition (CVD), grow an N-type epitaxial Si layer 4 with a thickness of 80nm on the upper Si material at 700°C as the collector region, and the doping concentration of this layer is 5 ×10 16 cm -3 ;
[0113] (1c) Using chemical vapor deposition (CVD), at 700°C, grow a layer of SiGe layer 5 with a thickness of 40nm on the substrate, as the base region, the Ge composition of this layer is 20%, and the doping concentration is 1×10 19 cm -3 ;
[0114] (1d)...
Embodiment 3
[0144] Embodiment 3: preparation of SOI SiGe HBT planar integrated device and circuit method with a base thickness of 60nm, the specific steps are as follows:
[0145] Step 1, epitaxial material preparation.
[0146] (1a) Select an SOI substrate, the support material 1 of the lower layer of the substrate is Si, and the middle layer 2 is SiO 2 , the thickness is 400nm, and the upper layer material 3 has a doping concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;
[0147] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer 4 with a thickness of 100 nm on the upper Si material at 750 ° C, as the collector region, and the doping concentration of this layer is 1 ×10 17 cm -3 ;
[0148] (1c) Using the chemical vapor deposition (CVD) method, at 750°C, grow a layer of SiGe layer 5 with a thickness of 60nm on the substrate. As the base region, the Ge composition of this layer is 25%, and the doping concentration is ...
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