A kind of bipolycrystalline planar soi BiCMOS integrated device and its preparation method
An integrated device, double polycrystalline technology, applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve the problems of low mechanical strength, high cost, incompatibility, wide application and development, etc.
- Summary
- Abstract
- Description
- Claims
- Application Information
 AI Technical Summary 
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0114] Embodiment 1: Preparation of conductive channel 22nm double polycrystalline planar SOI BiCMOS integrated device and circuit,
[0115] Specific steps are as follows:
[0116] Step 1, epitaxial material preparation.
[0117] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , the thickness is 300nm, and the upper layer material is a doping concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;
[0118] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 250nm on the upper layer of Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 ;
[0119] (1c) Deposit a layer of SiO with a thickness of 200nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD). 2 Floor;
[0120] (1d) Deposit a SiN layer with a thickness of 100nm on the surface o...
Embodiment 2
[0178] Embodiment 2: Prepare conductive channel 30nm double-polycrystalline planar SOI BiCMOS integrated device and circuit, the specific steps are as follows:
[0179] Step 1, epitaxial material preparation.
[0180] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 350nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;
[0181] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 270nm on the upper layer of Si material at 700°C, as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 ;
[0182] (1c) Deposit a layer of SiO with a thickness of 240nm on the surface of the substrate at 700°C by chemical vapor deposition (CVD). 2 Floor;
[0183] (1d) Deposit a layer of SiN with a thickness of 150 nm on the surface of the su...
Embodiment 3
[0241] Embodiment 3: prepare the dual-polycrystalline planar SOI BiCMOS integrated device and circuit of 45nm conductive channel, the specific steps are as follows:
[0242] Step 1, epitaxial material preparation.
[0243] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;
[0244] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 300nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 ;
[0245] (1c) Deposit a layer of SiO with a thickness of 300nm on the surface of the substrate at 800°C by chemical vapor deposition (CVD). 2 Floor;
[0246] (1d) Deposit a SiN layer with a thickness of 200nm on the surface of the substrate at 80...
PUM
 Login to View More
 Login to View More Abstract
Description
Claims
Application Information
 Login to View More
 Login to View More - R&D
- Intellectual Property
- Life Sciences
- Materials
- Tech Scout
- Unparalleled Data Quality
- Higher Quality Content
- 60% Fewer Hallucinations
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com
