A double polycrystalline strained si BiCMOS integrated device and its preparation method
An integrated device, double polycrystalline technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of confinement, low carrier material mobility of Si materials, etc.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0129] Embodiment 1: the preparation channel length is the double polycrystalline strained Si BiCMOS integrated device and circuit of 22nm, and concrete steps are as follows:
[0130] Step 1, epitaxial growth.
[0131] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 150nm, and the upper material is doped with a concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;
[0132] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 50nm on the upper Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 .
[0133] Step 2, deep trench isolation preparation.
[0134] (2a) Deposit a layer of SiO on the surface of the substrate at 600 °C by chemical vapor deposition (CVD) 2 ;
[0135] (2b) In the photolithographic isolation area, a deep groove with a depth of 2.5 ...
Embodiment 2
[0200] Embodiment 2: the preparation channel length is the strained Si BiCMOS integrated device and circuit of double polycrystalline of 30nm, and specific steps are as follows:
[0201] Step 1, epitaxial growth.
[0202] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 300nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;
[0203] (1b) Using chemical vapor deposition (CVD), grow an N-type epitaxial Si layer with a thickness of 80nm on the upper Si material at 700°C as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 .
[0204] Step 2, deep trench isolation preparation.
[0205](2a) Deposit a layer of SiO on the surface of the substrate at 700°C by chemical vapor deposition (CVD) 2 ;
[0206] (2b) In the photolithographic isolation area, a deep groove with a depth of 3 μm is etch...
Embodiment 3
[0271] Embodiment 3: the preparation channel length is the double polycrystalline strained Si BiCMOS integrated device and circuit of 45nm, and concrete steps are as follows:
[0272] Step 1, epitaxial growth.
[0273] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;
[0274] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 .
[0275] Step 2, deep trench isolation preparation.
[0276] (2a) Deposit a layer of SiO on the surface of the substrate at 800°C by chemical vapor deposition (CVD) 2 ;
[0277] (2b) In the photolithographic isolation area, a deep groo...
PUM
Property | Measurement | Unit |
---|---|---|
Thickness | aaaaa | aaaaa |
Thickness | aaaaa | aaaaa |
Thickness | aaaaa | aaaaa |
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com