The invention discloses a vertical-channel mixed-lattice-strain
BiCMOS integrated device and a preparation method. The preparation method comprises preparing an SOI (
silicon on insulator) substrate, epitaxially growing a Si layer on the substrate as a collector region, preparing
deep trench isolation, and preparing a double-polysilicon SiGe HBT (
heterojunction bipolar
transistor) device on the active region of the bipolar device by self-alignment process;
etching an active region of a PMOS (p-channel
metal oxide semiconductor) device by
lithography, continuously growing seven material
layers on the active region, andpreparing a drain and a gate to obtain the PMOS device;
etching a trench in the active region of an NMOS (n-channel
metal oxide semiconductor) device by
lithography, continuously growing four material
layers on the active region, preparing a
gate dielectric layer
and gate polysilicon to obtain the NMOS device,
etching lead holes by
lithography, alloying, and etching leads by lithography to obtain the vertical-channel mixed-lattice-strain
BiCMOS integrated device and circuit with a
CMOS conductive channel of 22 to 45nm. The preparation method provided by the invention can prepare the performance-enhanced vertical-channel mixed-lattice-strain
BiCMOS integrated device at 600 to 800 DEG C by fully utilizing the characteristics of mobility
anisotropy of the tensile strained Si material.