51results about How to "Reduce the erase voltage" patented technology

A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate.

The invention provides a nonvolatile memory. The nonvolatile memory is provided with a storage unit, wherein the storage unit is provided with a stack structure, a first floating gate, a second floating gate, erase gate dielectric layers, auxiliary gate dielectric layers, a first doping region, a second doping region, a first control gate and a second gate, wherein the stack structure comprises a gate dielectric layer, an auxiliary gate, an insulation layer and an erase gate which are sequentially arranged, the first floating gate and the second floating gate are respectively arranged on side walls of two sides of the stack structure, the erase gate dielectric layers are arranged between the erase gate and the first floating grid and between the erase gate and the second floating grid, the auxiliary gate dielectric layers are arranged between the auxiliary gate and the first floating gate and between the auxiliary gate and the second floating gate, the first doping region and the second doping region are respectively arranged at two sides of the stack structure, the first floating gate and the second floating gate, and the first control gate and the second gate are respectively arranged on the first floating gate and the second floating gate. By the nonvolatile memory, low-voltage operation can be performed, and the reliability of a semiconductor component is further improved.

A memory and a formation method thereof are disclosed. The method includes the following steps: a substrate is provided, the substrate includes erasure regions, floating gate regions and word line bitline regions, wherein the floating gate regions are located on both sides of the erasure regions, and the word line bit line regions are located on both sides of the erasure regions and the floatinggate regions; a floating grid electrode structure membrane and a dielectric layer located on the floating grid electrode structure membrane are formed on the substrate, and a first opening exposing the floating grid electrode structure membrane of the floating gate regions and the word line bit line regions are disposed in the dielectric layer; a first side wall is formed on the side wall of the first opening; a control grid electrode membrane is formed on the bottom of the first opening; a second side wall is formed on the side wall of the first side wall; the control grid electrode membraneand the floating grid electrode structure membrane exposed by the first side wall, the second side wall, and the dielectric layer are removed to form a floating gate structure layer, a control grid electrode layer and a second opening; the dielectric layer and the floating gate structure layer on the erasure regions are removed to form a third opening and a floating grid electrode structure; and an erasure grid electrode structure is formed in the third opening. The method enables the production efficiency of the memory to be improved.