50results about How to "Reduce the erase voltage" patented technology

A nonvolatile memory cell has charge trapping dielectric (160) which has been modified (i.e. oxidized) adjacent to edges of blocking dielectric (180). The modification reduces the charge-trapping density adjacent to the edges of the blocking dielectric, and hence reduces the leakage current at the edges. Other features are also provided.

Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.

A nonvolatile semiconductor memory device enabling a high sensitivity read operation by a low voltage, provided with a gate insulating film comprised of a bottom insulating film, a charge storing film, and a top insulating film successively stacked from the bottom, the bottom insulating film including a silicon oxynitride film directly under the charge storing film, and reading a bit of data stored at a local portion of a sub-source line side of a memory transistor and a bit of data stored at a local portion of a sub-bit line side independently by the reverse read method, whereby the incubation time is suppressed by the presence of silicon oxynitride, the controllability of the thickness of the charge storing film is improved, and the threshold voltage in an erase state is decreased, and a method of high sensitivity reading whereby a lower voltage and improved operational reliability are achieved.

A non-volatile memory having an isolation structure, a floating gate transistor, a specific dielectric layer and an erase gate is provided. The isolation structure is disposed in a substrate to define an active region. The floating gate transistor having a floating gate, a tunneling dielectric layer, a first source/drain region and a second source/drain region is disposed on the substrate. The floating gate is disposed on the substrate and runs across the active region. The tunneling dielectric layer is disposed between the floating gate and the substrate. The first source/drain region and the second source/drain region are disposed in the substrate at the sides of the floating gate, respectively. The specific dielectric layer serves as an inter-layer dielectric layer, which is disposed on top of the floating gate. The erase gate is a conductive plug disposed upon the specific dielectric layer.

The invention discloses a preparation method for a resistive random access memory. The resistive random access memory comprises a bottom electrode, a resistance change dielectric layer material and a top electrode which are assembled in sequence. Preparation of the resistance change dielectric layer material includes the following steps that firstly, a first precursor, first inert gas, a second precursor and second inert gas are fed into a reactor in order, and a monolayer metallic oxide film is deposited on the bottom electrode through a cycle of hot atomic layer deposition; secondly, a plasma enhancement process is carried out on the film; finally, the steps are carried out circularly and alternately. In the preparation process of a resistance change dielectric layer, a brand new in-situ plasma enhancement hot atomic layer deposition technology is brought in, so the surface appearance and defects of the metallic oxide film can be adjusted on a large scale; the resistive random access memory obtained through the preparation method can achieve precision control over device resistance switching characteristics to enable the device switch ratio and erase/write voltage to be adjusted, and has excellent resistance change stability.

A flash memory structure and a method of making the same are provided. The flash memory structure comprises a substrate, a source, a drain, a tunnel isolation layer, a ferroelectric-charge-trapping layer, at least one blocking isolation layer and at least one gate. The substrate is made of a semiconductive material. The source is formed on the substrate. The drain is formed on the substrate and spaced apart from the source. The tunnel isolation layer is formed on the substrate. The ferroelectric-charge-trapping layer is formed on the tunnel isolation layer and contains a charge-trapping layer and a ferroelectric negative-capacitance effect layer. The at least one blocking isolation layer is formed on the ferroelectric-charge-trapping layer. The at least one gate is formed on the blocking isolation layer. The ferroelectric negative-capacitance effect layer is made of a material with the ferroelectric negative-capacitance effect.

The invention discloses a method for improving the efficiency of erasing a floating gate, which comprises the following steps: sequentially forming a floating gate (FG) oxide layer, a FG polycrystalline silicon layer, an oxide layer-nitride layer-oxide layer (ONO) dielectric layer, a control gate (CG) polycrystalline silicon layer, a CG silicon nitride layer, a CG silicon oxide layer and a CG silicon nitride hard mask layer on a semiconductor substrate; coating photoresist on the CG silicon nitride hard mask layer, and patterning the photoresist; taking the patterned photoresist as a mask, and sequentially etching the CG silicon nitride hard mask layer, the CG silicon oxide layer, the CG silicon nitride layer, the CG polycrystalline silicon layer and the ONO dielectric layer to form two CGs; forming a CG side wall layer at two sides of each CG; forming a sacrificial layer at the outside of each CG side wall layer; taking the CG side wall layers, the sacrificial layer and the CG as masks, and etching the FG polycrystalline silicon layer to form FG; removing the sacrificial layer; and sequentially forming the oxide layer and depositing the polycrystalline silicon film outside the CG side wall layer and the FG, and finally forming the erasing gate EG by the polycrystalline silicon film. The method can effectively improve the efficiency of erasing the floating gate.

A memory and a formation method thereof are disclosed. The method includes the following steps: a substrate is provided, the substrate includes erasure regions, floating gate regions and word line bitline regions, wherein the floating gate regions are located on both sides of the erasure regions, and the word line bit line regions are located on both sides of the erasure regions and the floatinggate regions; a floating grid electrode structure membrane and a dielectric layer located on the floating grid electrode structure membrane are formed on the substrate, and a first opening exposing the floating grid electrode structure membrane of the floating gate regions and the word line bit line regions are disposed in the dielectric layer; a first side wall is formed on the side wall of the first opening; a control grid electrode membrane is formed on the bottom of the first opening; a second side wall is formed on the side wall of the first side wall; the control grid electrode membraneand the floating grid electrode structure membrane exposed by the first side wall, the second side wall, and the dielectric layer are removed to form a floating gate structure layer, a control grid electrode layer and a second opening; the dielectric layer and the floating gate structure layer on the erasure regions are removed to form a third opening and a floating grid electrode structure; and an erasure grid electrode structure is formed in the third opening. The method enables the production efficiency of the memory to be improved.

The present invention provides a non-volatile memory having a memory cell and an erasing method thereof. The memory cell includes a stacked structure, a floating gate, a tunneling dielectric layer, an erasing dielectric layer, a source, a drain, a control gate and an inter-gate dielectric layer. The stacked structure includes a gate dielectric layer, a gate and an insulation layer disposed in the order. The floating gate is disposed on a first sidewall of the stacked structure. The tunneling dielectric layer is disposed under the floating gate. The erasing dielectric layer is disposed between the gate and the floating gate. The erasing dielectric layer includes a first portion and a second portion with a thickness less than or equal to the first portion, and a corner portion of the floating gate is adjacent to the second portion. The source and the drain are separately disposed on the two sides of the stacked structure and the floating gate. The control gate is disposed on the source and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate, thereby being able to operate with a low operation voltage, and further increasing the reliability of a semiconductor element.

The invention belongs to the technical field of transistors, and discloses a double-gate ferroelectric transistor, a preparation method and a data erasing and reading method.The double-gate ferroelectric transistor comprises a substrate and a channel, the channel is arranged above a lining body and located in the middle of the lining body, and a source electrode region and a drain electrode region are arranged on the two sides of the channel respectively; a source electrode is arranged on the source electrode region, a drain electrode is arranged on the drain electrode region, and an insulating layer, a lower gate electrode, a ferroelectric gate dielectric layer and an upper gate electrode are sequentially arranged above the channel from bottom to top. The dual-gate ferroelectric field transistor has the beneficial effects that the erasing process is realized by adding pulses between the upper gate electrode and the lower gate electrode, so that voltage is prevented from falling on the insulating layer; the breakdown of the insulating layer caused by an overlarge electric field on the insulating layer is avoided, and the anti-fatigue property of the transistor is improved; and voltage division of the insulating layer can be avoided, so that the programming and erasing voltage and the working voltage of the ferroelectric field effect transistor are reduced.

A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate.

According to the split-gate flash memory and the forming method thereof provided by the invention, in the forming method of the split-gate flash memory, the floating gate tip is formed while the floating gate is formed, no process step is added in the whole process, and meanwhile, the newly added floating gate tip enhances the erasure capability of a memory cell and greatly improves the numericalvalue of current Ir1, so reliability of the memory cell is improved; the erase voltage on the erase gate during erase is reduced, so that the read operation interference is reduced, and the static power consumption and the dynamic power consumption of the split-gate flash memory for low-voltage read operation are reduced; in addition, the source line formed by the subsequent process only influences the erasing efficiency and does not influence the channel, so durability characteristic of the memory unit can be improved.