Nonvolatile memory manufacturing method thereof

Abstract

The invention provides a nonvolatile memory. The nonvolatile memory is provided with a storage unit, wherein the storage unit is provided with a stacked structure, floating gates, a tunneling dielectric layer, an erasing gate dielectric layer, an auxiliary gate dielectric layer, a source electrode region, a drain electrode region, control gates and an inter-gate dielectric layer; the stacked structure is provided with successively arranged gate dielectric layer, auxiliary gates, insulating layer and erasing gates; the floating gates are arranged at the side wall of the first side of the stacked structure; the tunneling dielectric layer is arranged below the floating gates; the erasing gate dielectric layer is arranged between the erasing gates and the floating gates; the auxiliary gate dielectric layer is arranged between the auxiliary gates and the floating gates; the source electrode region and the drain electrode region are respectively arranged at two sides of the stacked structure and the floating gates; the control gates are arranged on the source electrode region and the floating gates; and the inter-gate dielectric layer is arranged between the control gates and the floating gates.

Description

technical field [0001] The present invention relates to a semiconductor element and its manufacturing method, and in particular to a non-volatile memory and its manufacturing method. Background technique [0002] Non-volatile memory has been widely used in personal computers and electronic devices due to its advantages that data can be stored, read, and erased multiple times, and the stored data will not disappear after power failure. [0003] A typical non-volatile memory is designed to have a stacked gate (Stack-Gate) structure, which includes a tunnel oxide layer, a floating gate (Floating gate), and an inter-gate dielectric that are sequentially arranged on the substrate. layer and control gate (Control Gate). When programming or erasing the flash memory device, an appropriate voltage is applied to the source region, the drain region and the control gate respectively, so that electrons are injected into the polysilicon floating gate, or electrons are transferred from th...

AI Technical Summary

Problems solved by technology

However, the shortening of the gate length will shorten the channel length (Channel Length) under the tunnel oxide layer, which will easily cause abnormal electrical penetration (Punch Through) between the drain and the source, which will seriously affect the memory cell. electrical performance

Moreover, when programming and / or erasing memory cells, electrons repeatedly pass through the tunnel oxide layer, which will wear out the tunnel oxide layer, resulting in reduced reliability of the memory element.

Images