Nonvolatile memory manufacturing method thereof

Abstract

The invention provides a nonvolatile memory, which has a storage unit. The memory unit has a stack structure, a floating gate, a tunnel dielectric layer, an erase gate dielectric layer, an auxiliary gate dielectric layer, a source region, a drain region, a control gate and an inter-gate dielectric layer. The stack structure has a gate dielectric layer, an auxiliary gate, an insulating layer and an erasing gate arranged in sequence. The floating gate is disposed on the sidewall of the first side of the stack structure. The tunneling dielectric layer is disposed under the floating gate. The erasure gate dielectric layer is disposed between the erasure gate and the floating gate. The auxiliary gate dielectric layer is disposed between the auxiliary gate and the floating gate. The source region and the drain region are respectively disposed on two sides of the stack structure and the floating gate. The control gate is disposed on the source region and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate.

Description

technical field [0001] The present invention relates to a semiconductor element and its manufacturing method, and in particular to a non-volatile memory and its manufacturing method. Background technique [0002] Non-volatile memory has been widely used in personal computers and electronic devices due to its advantages that data can be stored, read, and erased multiple times, and the stored data will not disappear after power failure. [0003] A typical non-volatile memory is designed to have a stacked gate (Stack-Gate) structure, which includes a tunnel oxide layer, a floating gate (Floating gate), and an inter-gate dielectric that are sequentially arranged on the substrate. layer and control gate (Control Gate). When programming or erasing the flash memory device, an appropriate voltage is applied to the source region, the drain region and the control gate respectively, so that electrons are injected into the polysilicon floating gate, or electrons are transferred from th...

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Problems solved by technology

However, the shortening of the gate length will shorten the channel length (Channel Length) under the tunnel oxide layer, which will easily cause abnormal electrical penetration (Punch Through) between the drain and the source, which will seriously affect the memory cell. electrical performance

Moreover, when programming and / or erasing memory cells, electrons repeatedly pass through the tunnel oxide layer, which will wear out the tunnel oxide layer, resulting in reduced reliability of the memory element.

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