8results about How to "Reduce operating voltage" patented technology

The invention discloses a manufacturing method of a memory device and the memory device, and the manufacturing method comprises the steps: providing a semiconductor substrate which comprises a substrate and a hard mask layer on the substrate; a plurality of first grooves are formed in the active area of the substrate from the hard mask layer, one part of the first grooves are located in the storage area, the other part of the first grooves are located in the leading-out area, and the parts, in the substrate, of the first grooves are defined as base body grooves; forming a gate insulating layer and a semi-floating gate at the bottom of the groove of the substrate; one part of the semi-floating gate is in contact with the substrate, and the other part of the semi-floating gate is isolated from the substrate through a gate insulating layer; and forming an inter-gate dielectric layer and a first gate layer in the first groove, forming a control gate of the memory unit in the first groove of the memory region, and forming a lead-out wire of the memory unit in the first groove of the lead-out region, namely, enabling the lead-out region to be in contact with the outside, and solving the problem of voltage drop caused by large buried gate resistance.

Disclosed are compounds for use in organic optoelectronic devices, compositions for use in organic optoelectronic devices, organic optoelectronic devices, and display devices, wherein the compounds are represented by Chemical Formula 1, and the compositions comprise the compounds. Detailed description of Chemical Formula 1 is as described in the specification.

This invention proposes a method and system for capturing SO2 using a dual-cell system. The method involves a dual-cell system consisting of an acid cell and an alkaline cell connected in series. AgCl / Sb is used as the positive and negative electrodes of the acid cell, and SbOCl / Ag is used as the positive and negative electrodes of the alkaline cell. An aqueous solution containing 1-ethyl-3-methylimidazole chloride and sodium acetate is used as the electrolyte for a galvanic cell reaction. The electrolyte produced by the alkaline cell is continuously recycled back to the acid cell through an electrolyte storage tank. Then, the electrolyte produced by the acid cell is continuously recycled back to the alkaline cell through a vacuum stripper, thus achieving SO2 capture. This invention utilizes the electromotive force difference generated between the positive and negative electrodes of the dual-cell system to control the pH value of the electrolyte, thereby achieving selective adsorption and capture of SO2 in flue gas. It requires no chemical additives, is easy to implement, has no side reactions, no raw material waste or secondary pollution, low operating costs, and high electronic efficiency, showing promising application prospects.

The present invention discloses a method for manufacturing a floating gate TiN film of an ultra-fast flash memory, comprising: completing the preceding process according to the prior art until the groove etching is completed; depositing TiN; depositing a wrapping layer to wrap the TiN; photolithography to define a protection area and a non-protection area, forming a protective layer to protect the protection area, and exposing the non-protection area; etching to remove the wrapping layer of the non-protection area, exposing the TiN of the non-protection area; removing the protective layer of the protection area; etching to remove the TiN of the non-protection area; depositing a wrapping layer to wrap the TiN of the protection area; etching to remove the wrapping layer at the top of the protection area and the bottom of the groove, forming a wrapping layer sidewall; etching to remove the TiN at the top of the protection area and the bottom of the groove and the wrapping layer sidewall, and retaining the TiN of the groove sidewall. The present invention can effectively retain the ultra-fast flash memory sidewall floating gate TiN film, and improve the device performance and uniformity.

The invention belongs to the technical field of semiconductor devices, and more specifically relates to a biological voltage threshold conversion device, and a preparation method and application thereof. The biological voltage threshold conversion device provided by the invention comprises a bottom electrode, a top electrode and a resistive layer clamped between the two electrodes, wherein the resistive layer is made of oxyhydroxide. When the biological voltage threshold value conversion device is excited by voltage or electric pulse, the resistance state of the device can be converted from a high resistance state to a low resistance state, after an electric signal is removed, the device automatically returns to the high resistance state, the operation voltage in the whole process is smaller than 100 mV, the minimum operation voltage can reach 6.4 mV, and the programming power consumption of the device is greatly reduced. The threshold conversion device provided by the invention has a biological operating voltage, and has great application potential in constructing an ultra-low-power-consumption neuromorphic device in the field of brain-like computing.

The invention relates to a novel anthracene derivative and application thereof, and belongs to the technical field of photoelectric materials. The structure of the anthracene derivative is a compound as shown in a formula 1: # imgabs0 #, and the organic electroluminescent device containing the organic electroluminescent compound disclosed by the invention shows lower operating voltage, higher luminous efficiency and longer service life. In addition, the organic electroluminescent device can generate high-purity light, which helps to improve color presentation and visual experience of a display or a lighting fixture.

The invention provides a light emitting diode and a light emitting device. The light-emitting epitaxial layer comprises a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer which are stacked in sequence, the light-emitting epitaxial layer comprises a peripheral part and an inner side area surrounded by the peripheral part in a top view, the peripheral part is exposed out of a first surface of the first conductive type semiconductor layer, and the inner side area is exposed out of a second surface of the second conductive type semiconductor layer; the second conductive type semiconductor layer is arranged in an inner side area surrounded by the peripheral part; a conductive connection portion disposed on the outer peripheral portion and contacting the first conductive type semiconductor layer; the insulating layer is formed on the light-emitting epitaxial layer and is provided with a first opening part which exposes a part of the surface of the conductive connecting part; the first contact electrode is formed on the first conductive type semiconductor layer and is in contact with the surface of the conductive connecting part; the second contact electrode is formed on the second conductive type semiconductor layer; a first pad electrode formed over the first contact electrode; a second pad electrode is formed over the second contact electrode.

This application provides a semiconductor structure and its fabrication method, a memory, and an electronic device. The method includes: forming a stacked first active structure and a second active structure on a substrate; forming a transistor based on the first active structure; the transistor includes a source / drain structure, a first interlayer dielectric layer, a gate, and a first back-end interconnect layer; washing and thinning the substrate; depositing a dielectric material to form a second interlayer dielectric layer; performing photolithography on the second interlayer dielectric layer and the first interlayer dielectric layer to form a first groove and a first via; the first groove is located inside the second interlayer dielectric layer; the first via is located inside the first interlayer dielectric layer and exposes at least a portion of the surface of the source / drain structure; the first via communicates with the bottom of the first groove; filling the first via with metal to form a conductive via; forming a memory element in the first groove; the memory element is electrically connected to the transistor through the conductive via; and forming a second back-end interconnect layer on the memory element.