11results about How to "Reduce operating voltage" patented technology

The invention discloses a manufacturing method of a memory device and the memory device, and the manufacturing method comprises the steps: providing a semiconductor substrate which comprises a substrate and a hard mask layer on the substrate; a plurality of first grooves are formed in the active area of the substrate from the hard mask layer, one part of the first grooves are located in the storage area, the other part of the first grooves are located in the leading-out area, and the parts, in the substrate, of the first grooves are defined as base body grooves; forming a gate insulating layer and a semi-floating gate at the bottom of the groove of the substrate; one part of the semi-floating gate is in contact with the substrate, and the other part of the semi-floating gate is isolated from the substrate through a gate insulating layer; and forming an inter-gate dielectric layer and a first gate layer in the first groove, forming a control gate of the memory unit in the first groove of the memory region, and forming a lead-out wire of the memory unit in the first groove of the lead-out region, namely, enabling the lead-out region to be in contact with the outside, and solving the problem of voltage drop caused by large buried gate resistance.

The invention discloses a high-durability FeFET based on a ferroelectric semiconductor channel and an anti-ferroelectric gate dielectric and a preparation method of the high-durability FeFET. A back gate electrode layer, an anti-ferroelectric gate dielectric layer, a ferroelectric semiconductor channel layer, a top gate high-k gate dielectric layer and a top gate electrode layer are sequentially stacked in a FeFET structure, and the anti-ferroelectric gate dielectric layer serves as a back gate dielectric layer; the top gate high-k gate dielectric layer serves as a top gate dielectric layer, the thickness of the back gate dielectric layer is larger than that of the top gate dielectric layer, and an asymmetric double-gate structure is formed. According to the invention, the hafnium oxide-based anti-ferroelectric thin film is used for replacing a ferroelectric thin film as a gate medium of the FeFET, so that the operation voltage is effectively reduced; no interface layer is arranged between the ferroelectric semiconductor channel and the anti-ferroelectric gate dielectric, so that durability failure caused by charge trapping and defect generation associated with the traditional FeFET and the interface layer is inhibited; the out-of-plane spontaneous polarization continuous, precise and adjustable characteristic of a ferroelectric semiconductor channel and the gate storage mode and the channel storage mode which are switched mutually based on the asymmetric double-gate structure of the FeFET are hopeful to enable the FeFET to show higher durability.

Disclosed are compounds for use in organic optoelectronic devices, compositions for use in organic optoelectronic devices, organic optoelectronic devices, and display devices, wherein the compounds are represented by Chemical Formula 1, and the compositions comprise the compounds. Detailed description of Chemical Formula 1 is as described in the specification.

This invention proposes a method and system for capturing SO2 using a dual-cell system. The method involves a dual-cell system consisting of an acid cell and an alkaline cell connected in series. AgCl / Sb is used as the positive and negative electrodes of the acid cell, and SbOCl / Ag is used as the positive and negative electrodes of the alkaline cell. An aqueous solution containing 1-ethyl-3-methylimidazole chloride and sodium acetate is used as the electrolyte for a galvanic cell reaction. The electrolyte produced by the alkaline cell is continuously recycled back to the acid cell through an electrolyte storage tank. Then, the electrolyte produced by the acid cell is continuously recycled back to the alkaline cell through a vacuum stripper, thus achieving SO2 capture. This invention utilizes the electromotive force difference generated between the positive and negative electrodes of the dual-cell system to control the pH value of the electrolyte, thereby achieving selective adsorption and capture of SO2 in flue gas. It requires no chemical additives, is easy to implement, has no side reactions, no raw material waste or secondary pollution, low operating costs, and high electronic efficiency, showing promising application prospects.

The present invention discloses a method for manufacturing a floating gate TiN film of an ultra-fast flash memory, comprising: completing the preceding process according to the prior art until the groove etching is completed; depositing TiN; depositing a wrapping layer to wrap the TiN; photolithography to define a protection area and a non-protection area, forming a protective layer to protect the protection area, and exposing the non-protection area; etching to remove the wrapping layer of the non-protection area, exposing the TiN of the non-protection area; removing the protective layer of the protection area; etching to remove the TiN of the non-protection area; depositing a wrapping layer to wrap the TiN of the protection area; etching to remove the wrapping layer at the top of the protection area and the bottom of the groove, forming a wrapping layer sidewall; etching to remove the TiN at the top of the protection area and the bottom of the groove and the wrapping layer sidewall, and retaining the TiN of the groove sidewall. The present invention can effectively retain the ultra-fast flash memory sidewall floating gate TiN film, and improve the device performance and uniformity.

The invention belongs to the technical field of semiconductor devices, and more specifically relates to a biological voltage threshold conversion device, and a preparation method and application thereof. The biological voltage threshold conversion device provided by the invention comprises a bottom electrode, a top electrode and a resistive layer clamped between the two electrodes, wherein the resistive layer is made of oxyhydroxide. When the biological voltage threshold value conversion device is excited by voltage or electric pulse, the resistance state of the device can be converted from a high resistance state to a low resistance state, after an electric signal is removed, the device automatically returns to the high resistance state, the operation voltage in the whole process is smaller than 100 mV, the minimum operation voltage can reach 6.4 mV, and the programming power consumption of the device is greatly reduced. The threshold conversion device provided by the invention has a biological operating voltage, and has great application potential in constructing an ultra-low-power-consumption neuromorphic device in the field of brain-like computing.

The invention relates to a novel anthracene derivative and application thereof, and belongs to the technical field of photoelectric materials. The structure of the anthracene derivative is a compound as shown in a formula 1: # imgabs0 #, and the organic electroluminescent device containing the organic electroluminescent compound disclosed by the invention shows lower operating voltage, higher luminous efficiency and longer service life. In addition, the organic electroluminescent device can generate high-purity light, which helps to improve color presentation and visual experience of a display or a lighting fixture.

The invention provides a light emitting diode and a light emitting device. The light-emitting epitaxial layer comprises a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer which are stacked in sequence, the light-emitting epitaxial layer comprises a peripheral part and an inner side area surrounded by the peripheral part in a top view, the peripheral part is exposed out of a first surface of the first conductive type semiconductor layer, and the inner side area is exposed out of a second surface of the second conductive type semiconductor layer; the second conductive type semiconductor layer is arranged in an inner side area surrounded by the peripheral part; a conductive connection portion disposed on the outer peripheral portion and contacting the first conductive type semiconductor layer; the insulating layer is formed on the light-emitting epitaxial layer and is provided with a first opening part which exposes a part of the surface of the conductive connecting part; the first contact electrode is formed on the first conductive type semiconductor layer and is in contact with the surface of the conductive connecting part; the second contact electrode is formed on the second conductive type semiconductor layer; a first pad electrode formed over the first contact electrode; a second pad electrode is formed over the second contact electrode.

The memristor comprises a top electrode, a functional layer, a bottom electrode and a substrate, the top electrode, the functional layer, the bottom electrode and the substrate are arranged in sequence, and the top electrode, the functional layer, the bottom electrode and the substrate are perpendicular to one another; and the functional layer is composed of a p-type organic material PTAA and a p-type dopant F4-TCNQ. The structure is easy to design, the process is simple, the yield is high, universality is achieved, a new material strategy for stable operation of the reliable linear large-range conductance-adjustable artificial synapse in the air environment is developed, technical reserve is provided for constructing a high-stability and high-precision artificial neural network, and therefore development of artificial intelligence devices is promoted.

The invention belongs to the technical field of novel storage materials and microelectronic devices, and particularly discloses a novel ultra-low power consumption polymorphic lossless reading ferroelectric memory capacitor and a preparation method thereof. The ferroelectric memcapacitor comprises a first electrode, a second electrode and a ferroelectric layer, wherein the first electrode and the second electrode are oppositely arranged, the ferroelectric layer is arranged between the first electrode and the second electrode, and the ferroelectric layer is of a laminated structure formed by alternately arranging hafnium oxide (Hf02) layers and zirconium oxide (Zr02) layers. The multi-state memory which has the advantages of being simple in structure, compatible with the CMOS technology, capable of being miniaturized, low in power consumption, lossless, rapid in reading, good in durability and the like is obtained through combination of structural design and technology optimization. By utilizing the characteristic that the dielectric constant can be changed by the nonvolatile polarization effect of the hafnium zirconium oxide ferroelectric layer, a nonvolatile adjustable capacitance value is formed for data storage, a storage window is maximized, an operation voltage is minimized, and polymorphic storage is realized; the common problems of low read-write speed, high write-in power consumption, poor durability and the like of the conventional nonvolatile memory are effectively solved.

This application provides a semiconductor structure and its fabrication method, a memory, and an electronic device. The method includes: forming a stacked first active structure and a second active structure on a substrate; forming a transistor based on the first active structure; the transistor includes a source / drain structure, a first interlayer dielectric layer, a gate, and a first back-end interconnect layer; washing and thinning the substrate; depositing a dielectric material to form a second interlayer dielectric layer; performing photolithography on the second interlayer dielectric layer and the first interlayer dielectric layer to form a first groove and a first via; the first groove is located inside the second interlayer dielectric layer; the first via is located inside the first interlayer dielectric layer and exposes at least a portion of the surface of the source / drain structure; the first via communicates with the bottom of the first groove; filling the first via with metal to form a conductive via; forming a memory element in the first groove; the memory element is electrically connected to the transistor through the conductive via; and forming a second back-end interconnect layer on the memory element.