3results about How to "Reduce operating voltage" patented technology

Disclosed are compounds for use in organic optoelectronic devices, compositions for use in organic optoelectronic devices, organic optoelectronic devices, and display devices, wherein the compounds are represented by Chemical Formula 1, and the compositions comprise the compounds. Detailed description of Chemical Formula 1 is as described in the specification.

This invention proposes a method and system for capturing SO2 using a dual-cell system. The method involves a dual-cell system consisting of an acid cell and an alkaline cell connected in series. AgCl / Sb is used as the positive and negative electrodes of the acid cell, and SbOCl / Ag is used as the positive and negative electrodes of the alkaline cell. An aqueous solution containing 1-ethyl-3-methylimidazole chloride and sodium acetate is used as the electrolyte for a galvanic cell reaction. The electrolyte produced by the alkaline cell is continuously recycled back to the acid cell through an electrolyte storage tank. Then, the electrolyte produced by the acid cell is continuously recycled back to the alkaline cell through a vacuum stripper, thus achieving SO2 capture. This invention utilizes the electromotive force difference generated between the positive and negative electrodes of the dual-cell system to control the pH value of the electrolyte, thereby achieving selective adsorption and capture of SO2 in flue gas. It requires no chemical additives, is easy to implement, has no side reactions, no raw material waste or secondary pollution, low operating costs, and high electronic efficiency, showing promising application prospects.

This application provides a semiconductor structure and its fabrication method, a memory, and an electronic device. The method includes: forming a stacked first active structure and a second active structure on a substrate; forming a transistor based on the first active structure; the transistor includes a source / drain structure, a first interlayer dielectric layer, a gate, and a first back-end interconnect layer; washing and thinning the substrate; depositing a dielectric material to form a second interlayer dielectric layer; performing photolithography on the second interlayer dielectric layer and the first interlayer dielectric layer to form a first groove and a first via; the first groove is located inside the second interlayer dielectric layer; the first via is located inside the first interlayer dielectric layer and exposes at least a portion of the surface of the source / drain structure; the first via communicates with the bottom of the first groove; filling the first via with metal to form a conductive via; forming a memory element in the first groove; the memory element is electrically connected to the transistor through the conductive via; and forming a second back-end interconnect layer on the memory element.