Splitting grid memory cell and operation method thereof

Abstract

A splitting grid memory cell and an operation method thereof are disclosed. The memory cell comprises: a semiconductor substrate, a floating grid, a control grid and a selection grid, wherein a first doped region, a second doped region and a third doped region are successively formed on the semiconductor substrate; a first diffusion region and a second diffusion region are formed in the third doped region; the floating grid is formed on the semiconductor substrate between the first diffusion region and the second diffusion region; a first side of the floating grid is overlapped with parts of the first diffusion region; the control grid is formed on the semiconductor substrate between a second side of the floating grid and the second diffusion region; an insulating oxide layer is formed between the control grid and the second side of the floating grid; the selection grid is formed on the semiconductor substrate in the first diffusion region; a doped type of the first doped region is the same with the doped type of the third doped region and is opposite to the doped type of the second doped region. By using the memory cell and the method of the invention, a size of the memory cell can be effectively reduced; a quality of the memory cell can be improved and manufacturing costs can be reduced.

Description

technical field [0001] The invention relates to a semiconductor storage device, in particular to a split gate storage unit and an operation method thereof. Background technique [0002] Non-volatile memory refers to a storage device capable of retaining stored data even when power is turned off. Generally, nonvolatile memory devices include erasable and writable read only memory (EPROM), electrically erasable and writable read only memory (EEPROM), and flash EEPROM. There are currently two basic types of non-volatile memory cell structures: stacked gate and split gate structures, in which split gate memory cells are obtained because they can effectively avoid the over-erasing effect and have higher programming efficiency. widely used. [0003] figure 1 A schematic structural diagram of a split gate memory device in the prior art is shown, refer to figure 1 , the memory device includes two memory cells M1 and M2 formed on a P-type semiconductor substrate 100; an N-type fi...

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Problems solved by technology

However, due to the high cost of the photomask, the cost of manufacturing the split gate memory cell in the prior art is relatively high

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