Split gate type memory and formation method thereof

Abstract

The invention relates to a split gate type memory and a formation method thereof The split gate type memory comprises a substrate, an erasing gate, a floating gate, a word line and insulating layers;source and drain areas are formed on the substrate, and a source line in contact connection with the source area is formed on the source area; the erasing gate is arranged on the source line; the floating gate and word line are arranged horizontally adjacent to each other on the substrate between the source and drain areas, the floating gate is close to the source line, and the word line is far from the source line; and the insulating layers are formed between the source line, erasing gate, floating gate and word line. The source line higher than the upper surface of the substrate is arranged,so that the floating gate and the source area form an overlapped area in the vertical direction, and the height of the source line is adjustable, so that a coupling efficiency between the floating gate and the source area is ensured while the wafer size is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a split-gate memory and a forming method thereof. Background technique [0002] In existing split-gate memories, such as figure 1 As shown, the floating gate FG is partly located above the source region SL and is insulated from it, wherein the overlapping portion of the source region SL and the floating gate FG accounts for about 1 / 2 of the length of the floating gate FG, which is used for source region SL during programming. The coupling of the electrode to the floating gate FG generates a high voltage, which attracts electrons to tunnel to the floating gate FG, but the longer coupling area affects the reduction of the wafer size. [0003] Therefore, how to provide a split-gate memory and its forming method that can reduce the length of the floating gate FG on the plane under the premise of ensuring the coupling coefficient of the source to the floating gate...

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Problems solved by technology

[0002] In existing split-gate memories, such as figure 1 As shown, the floating gate FG is partly located above the source region SL and is insulated from it, wherein the overlapping portion of the source region SL and the floating gate FG accounts for about 1 / 2 of the length of the floating gate FG, which is used for source region SL during programming. The pole-to-floating gate FG coupling generates high voltage, which attracts electrons to tunnel to the floating gate FG, but the longer coupling area affects the reduction of wafer size

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