Memory and formation method thereof

A memory and storage area technology, applied in the direction of electric solid-state devices, semiconductor devices, electrical components, etc., can solve the problems of complex process and low production efficiency, and achieve the effect of simplifying and reducing the process flow

Active Publication Date: 2019-05-03
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, in the prior art, multiple patterning processes are required in the formati

Method used

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  • Memory and formation method thereof
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  • Memory and formation method thereof

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Example Embodiment

[0027] As mentioned in the background art, the performance of the prior art memory is poor.

[0028] A memory includes: a substrate, the substrate includes an erase area and a floating gate area, the floating gate area is adjacent to the erase area and located on both sides of the erase area; the erase area is located on the erase area of ​​the substrate In addition to the gate structure; the floating gate structure respectively located on the floating gate area of ​​the substrate; the first side wall, the second side wall and the control gate structure located on the floating gate structure, the second side wall is located in the control On the gate structure, the first sidewall spacer is parallel to the second sidewall spacer and the control gate structure.

[0029] In the formation process of the above-mentioned memory, the formation of the erase gate structure, the control gate structure and the floating gate structure each requires one mask, so at least three patterning proces...

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Abstract

A memory and a formation method thereof are disclosed. The method includes the following steps: a substrate is provided, the substrate includes erasure regions, floating gate regions and word line bitline regions, wherein the floating gate regions are located on both sides of the erasure regions, and the word line bit line regions are located on both sides of the erasure regions and the floatinggate regions; a floating grid electrode structure membrane and a dielectric layer located on the floating grid electrode structure membrane are formed on the substrate, and a first opening exposing the floating grid electrode structure membrane of the floating gate regions and the word line bit line regions are disposed in the dielectric layer; a first side wall is formed on the side wall of the first opening; a control grid electrode membrane is formed on the bottom of the first opening; a second side wall is formed on the side wall of the first side wall; the control grid electrode membraneand the floating grid electrode structure membrane exposed by the first side wall, the second side wall, and the dielectric layer are removed to form a floating gate structure layer, a control grid electrode layer and a second opening; the dielectric layer and the floating gate structure layer on the erasure regions are removed to form a third opening and a floating grid electrode structure; and an erasure grid electrode structure is formed in the third opening. The method enables the production efficiency of the memory to be improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a memory and a forming method thereof. Background technique [0002] Flash memory is an important device in integrated circuit products. The main feature of flash memory is that it can keep stored information for a long time without applying voltage. Flash memory has the advantages of high integration, fast access speed and easy erasing, so it is widely used. [0003] Flash memory is classified into two types: stack gate flash memory and split gate flash memory. The stacked gate flash memory has a floating gate and a control gate above the floating gate. The stacked gate flash memory has the problem of over-erasing. Different from the stacked gate flash memory, the split gate flash memory forms a word line as an erasing gate on one side of the floating gate. The split-gate flash memory can effectively avoid the over-erasing effect. [0004] However, in the prior a...

Claims

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Application Information

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IPC IPC(8): H01L27/11521H01L21/28H01L29/423
Inventor 李冰寒
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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