Non-volatile Memory And Erasing Method Thereof

Abstract

The present invention provides a non-volatile memory having a memory cell and an erasing method thereof. The memory cell includes a stacked structure, a floating gate, a tunneling dielectric layer, an erasing dielectric layer, a source, a drain, a control gate and an inter-gate dielectric layer. The stacked structure includes a gate dielectric layer, a gate and an insulation layer disposed in the order. The floating gate is disposed on a first sidewall of the stacked structure. The tunneling dielectric layer is disposed under the floating gate. The erasing dielectric layer is disposed between the gate and the floating gate. The erasing dielectric layer includes a first portion and a second portion with a thickness less than or equal to the first portion, and a corner portion of the floating gate is adjacent to the second portion. The source and the drain are separately disposed on the two sides of the stacked structure and the floating gate. The control gate is disposed on the source and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate, thereby being able to operate with a low operation voltage, and further increasing the reliability of a semiconductor element.

Description

technical field [0001] The present invention relates to a semiconductor element, and in particular to a non-volatile memory and its erasing method. Background technique [0002] Non-volatile memory has been widely used in personal computers and electronic devices due to its advantages that data can be stored, read, and erased multiple times, and the stored data will not disappear after power failure. [0003] A typical non-volatile memory is designed to have a stacked gate (Stack-Gate) structure, which includes a tunnel oxide layer, a floating gate (Floating gate), and an interleaving dielectric layer sequentially arranged on the substrate. And control grid (Control Gate). When programming or erasing the flash memory device, an appropriate voltage is applied to the source region, the drain region and the control gate respectively, so that electrons are injected into the polysilicon floating gate, or electrons are removed from the polysilicon floating gate. Set the gate to ...

AI Technical Summary

Problems solved by technology

However, the shortening of the gate length will shorten the channel length (Channel Length) under the tunnel oxide layer, which will easily cause abnormal electrical penetration (Punch Through) between the drain and the source, which will seriously affect the memory cell. electrical performance

Moreover, when programming and / or erasing memory cells, electrons repeatedly pass through the tunnel oxide layer, which will wear out the tunnel oxide layer, resulting in reduced reliability of the memory element.

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