Method for improving efficiency of erasing floating gate

Abstract

The invention discloses a method for improving the efficiency of erasing a floating gate, which comprises the following steps: sequentially forming a floating gate (FG) oxide layer, a FG polycrystalline silicon layer, an oxide layer-nitride layer-oxide layer (ONO) dielectric layer, a control gate (CG) polycrystalline silicon layer, a CG silicon nitride layer, a CG silicon oxide layer and a CG silicon nitride hard mask layer on a semiconductor substrate; coating photoresist on the CG silicon nitride hard mask layer, and patterning the photoresist; taking the patterned photoresist as a mask, and sequentially etching the CG silicon nitride hard mask layer, the CG silicon oxide layer, the CG silicon nitride layer, the CG polycrystalline silicon layer and the ONO dielectric layer to form two CGs; forming a CG side wall layer at two sides of each CG; forming a sacrificial layer at the outside of each CG side wall layer; taking the CG side wall layers, the sacrificial layer and the CG as masks, and etching the FG polycrystalline silicon layer to form FG; removing the sacrificial layer; and sequentially forming the oxide layer and depositing the polycrystalline silicon film outside the CG side wall layer and the FG, and finally forming the erasing gate EG by the polycrystalline silicon film. The method can effectively improve the efficiency of erasing the floating gate.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving the erasing efficiency of a floating gate. Background technique [0002] At present, in the development of 70nm split-gate flash (Split-Gate Flash) technology, the erasing efficiency of the floating gate (Floating Gate, FG) in the memory cell area is relatively low, such as having an erasing voltage of 13 volts and an erasing time of 5 seconds. except time. Improving erasing efficiency has increasingly become a key technology in the high-end split-gate flash memory manufacturing process. [0003] Figure 1a to Figure 1d A schematic cross-sectional view of a manufacturing process of a memory cell region in the prior art is shown. [0004] First, if Figure 1a As shown, a FG oxide layer 101, a FG polysilicon layer 102, an oxide layer-nitride layer-oxide layer (ONO) dielectric layer 103, a control gate (Control Gate, CG) polysilicon laye...

AI Technical Summary

Problems solved by technology

[0009] In view of this, the technical problem solved by the present invention is: the problem that the erasing efficiency of the existing floating gate is low

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