non-volatile memory

Abstract

The invention provides a non-volatile memory, which has a storage unit. The memory cell has a stacked structure, first and second floating gates, an erasure gate dielectric layer, an auxiliary gate dielectric layer, first and second doped regions, and first and second control gates. The stacked structure has a gate dielectric layer, an auxiliary gate, an insulation layer and an erasure gate arranged in sequence. The first and second floating gates are respectively disposed on sidewalls on both sides of the stacked structure. The erase gate dielectric layer is disposed between the erase gate and the first and second floating gates. The auxiliary gate dielectric layer is disposed between the auxiliary gate electrode and the first and second floating gate electrodes. The first and second doping regions are respectively disposed on both sides of the stack structure and the first and second floating gates. The first and second control gates are respectively disposed on the first and second floating gates. The present invention can operate at low operating voltage, thereby increasing the reliability of semiconductor components.

Description

technical field [0001] The invention relates to a semiconductor element, in particular to a nonvolatile memory. Background technique [0002] Non-volatile memory has been widely used in personal computers and electronic devices due to its advantages that data can be stored, read, and erased multiple times, and the stored data will not disappear after power failure. [0003] A typical non-volatile memory is designed to have a stacked gate (Stack-Gate) structure, which includes a tunnel oxide layer, a floating gate (Floating gate), and an inter-gate dielectric that are sequentially arranged on the substrate. layer and control gate (Control Gate). When programming or erasing the flash memory device, appropriate voltages are applied to the source region, the drain region, and the control gate, so that electrons are injected into the polysilicon floating gate, or electrons are removed from the polysilicon floating gate. Set the gate to pull out. [0004] In the operation of no...

AI Technical Summary

Problems solved by technology

However, the shortening of the gate length will shorten the channel length (Channel Length) under the tunnel oxide layer, which will easily cause abnormal electrical penetration (Punch Through) between the drain and the source, which will seriously affect the memory cell. electrical performance

Moreover, when programming and / or erasing memory cells, electrons repeatedly pass through the tunnel oxide layer, which will wear out the tunnel oxide layer, resulting in reduced reliability of the memory element.

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