Three-strained fully planar SOI (silicon on insulator) BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method
An integrated device, full-plane technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of low mechanical strength, high cost, incompatibility with wide application and development, etc.
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Embodiment 1
[0108] Embodiment 1: Preparation of conductive channel 22nm three-strain, full-plane SOI BiCMOS integrated device and circuit, the specific steps are as follows:
[0109] Step 1, epitaxial growth.
[0110] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 150nm, and the upper material is doped with a concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;
[0111] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 50nm on the upper Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 ;
[0112] (1c) Using chemical vapor deposition (CVD), grow a SiGe layer with a thickness of 20nm on the substrate at 600°C. As the base region, the Ge composition of this layer is 15%, and the doping concentration is 5×10 18 cm -3 ;
[0113] (1d) Using the method of chemi...
Embodiment 2
[0167] Embodiment 2: Prepare conductive channel 30nm three-strain, full-plane SOI BiCMOS integrated device and circuit, the specific steps are as follows:
[0168] Step 1, epitaxial growth.
[0169] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 300nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;
[0170] (1b) Using chemical vapor deposition (CVD), grow an N-type epitaxial Si layer with a thickness of 80nm on the upper Si material at 700°C as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 ;
[0171] (1c) Using chemical vapor deposition (CVD), grow a layer of SiGe layer with a thickness of 40nm on the substrate at 700°C. As the base region, the Ge composition of this layer is 20%, and the doping concentration is 1×10 19 cm -3 ;
[0172] (1d) Using the method of chemical vap...
Embodiment 3
[0226] Embodiment 3: Prepare a three-strain, full-plane SOI BiCMOS integrated device and circuit with a 45nm conductive channel, and the specific steps are as follows:
[0227]Step 1, epitaxial growth.
[0228] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;
[0229] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 ;
[0230] (1c) Using chemical vapor deposition (CVD), grow a layer of SiGe layer with a thickness of 60nm on the substrate at 750°C. As the base region, the Ge composition of this layer is 25%, and the doping concentration is 5×10 19 cm -3 ;
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