A strained SiGe planar Si-based Bicmos integrated device based on SOI substrate and its preparation method

A technology for integrating devices and substrate surfaces, which is applied in the field of strained SiGe planar Si-based BiCMOS integrated devices and fabrication, and can solve problems such as difficulty in design, reduction in lithography accuracy, and inability to meet low power consumption.

Inactive Publication Date: 2015-08-12
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For example, when the feature size is less than 100nm, due to problems such as tunneling leakage current and reliability, the traditional gate dielectric material SiO 2 Unable to meet the requirements of low power consumption; the short channel effect and narrow channel effect of nanometer devices are becoming more and more obvious, which seriously affects the device performance; traditional lithography technology cannot meet the shrinking lithography precision
Therefore, traditional Si-based process devices are increasingly difficult to meet the needs of design

Method used

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  • A strained SiGe planar Si-based Bicmos integrated device based on SOI substrate and its preparation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0113] Embodiment 1: Prepare a strained SiGe planar Si-based BiCMOS integrated device and circuit based on an SOI substrate with a channel length of 22 nm. The specific steps are as follows:

[0114] Step 1, epitaxial growth.

[0115] (1a) Select an SOI substrate, the lower support material of the substrate is Si, and the middle layer is SiO 2 , The thickness is 150nm, the upper layer material is doping concentration is 1×10 16 cm -3 N-type Si with a thickness of 100nm;

[0116] (1b) Using the chemical vapor deposition (CVD) method, at 600℃, grow a layer of 250nm thick N-type epitaxial Si layer on the upper Si material as a collector area, the doping concentration of this layer is 1× 10 16 cm -3 ;

[0117] (1c) Using chemical vapor deposition (CVD) method, at 600℃, deposit a layer of SiO with a thickness of 200nm on the surface of the substrate 2 Floor;

[0118] (1d) Using chemical vapor deposition (CVD) method, at 600℃, deposit a layer of SiN with a thickness of 100nm on the surface o...

Embodiment 2

[0176] Embodiment 2: Prepare a strained SiGe planar Si-based BiCMOS integrated device and circuit based on an SOI substrate with a channel length of 130 nm. The specific steps are as follows:

[0177] Step 1, epitaxial growth.

[0178] (1a) Select an SOI substrate, the lower support material of the substrate is Si, and the middle layer is SiO 2 , The thickness is 300nm, the upper material is doping concentration is 5×10 16 cm -3 N-type Si with a thickness of 120nm;

[0179] (1b) Using chemical vapor deposition (CVD) method, at 700℃, grow a layer of 250nm thick N-type epitaxial Si layer on the upper Si material as a collector area, the doping concentration of this layer is 5× 10 16 cm -3 ;

[0180] (1c) Using chemical vapor deposition (CVD), a layer of SiO with a thickness of 240nm is deposited on the surface of the substrate at 700°C 2 Floor;

[0181] (1d) Using chemical vapor deposition (CVD) method, at 700℃, deposit a layer of SiN with a thickness of 150nm on the surface of the subst...

Embodiment 3

[0239] Embodiment 3: Prepare a strained SiGe planar Si-based BiCMOS integrated device and circuit based on an SOI substrate with a channel length of 350 nm. The specific steps are as follows:

[0240] Step 1, epitaxial growth.

[0241] (1a) Select an SOI substrate, the lower support material of the substrate is Si, and the middle layer is SiO 2 , The thickness is 400nm, the upper layer material is doping concentration is 1×10 17 cm -3 N-type Si with a thickness of 150nm;

[0242] (1b) Using the method of chemical vapor deposition (CVD), at 750℃, grow an N-type epitaxial Si layer with a thickness of 300nm on the upper Si material as a collector area. The doping concentration of this layer is 1× 10 17 cm -3 ;

[0243] (1c) Using chemical vapor deposition (CVD) method, at 800℃, deposit a layer of SiO with a thickness of 300nm on the surface of the substrate 2 Floor;

[0244] (1d) Using chemical vapor deposition (CVD) method, at 800℃, deposit a layer of SiN with a thickness of 200nm on the...

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Abstract

The invention discloses a strain SiGe plane Si-based BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device on the basis of a SOI (Silicon On Insulator) substrate and a preparation method. The preparation method has the following preparation process of: growing an N-Si layer on the SOI substrate to form a bipolar device collector region, photoetching a base region, regionally growing a P-SiGe layer, an i-Si layer and an i-Poly-Si layer in the base region, preparing a deep-trench isolation, forming an emitting electrode, a base electrode and a collector electrode and forming a SiGe HBT (Heterojunction Bipolar Trthissistor) device; and growing a strain SiGe material on the substrate, forming active regions of NMOS (N-channel Metal Oxide Semiconductor) and PMOS (P-channel Metal Oxide Semiconductor) devices, preparing a pseudo-gate, carrying out self-aligning to generate source drain regions of the NMOS and PMOS devices, removing the pseudo-gate, preparing a grid electrode and photoetching leads to form the strain SiGe plane Si-based BiCMOS integrated device on the basis of the SOI substrate and a circuit. According to the method, the SOI SiGe BiCMOS integrated circuit is prepared by sufficiently utilizing the characteristic that the hole mobility of a SiGe material is higher than that of a common Si material, so that the performance of the existing analog and analog-digital mixed integrated circuit is greatly improved.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a strained SiGe planar Si-based BiCMOS integrated device based on an SOI substrate and a preparation method thereof. Background technique [0002] Semiconductor integrated circuit technology is the core technology of the high-tech and information industry. It has become an important indicator of a country's scientific and technological level, comprehensive national strength, and national defense strength. Microelectronics technology represented by integrated circuits is the key to semiconductor technology. The semiconductor industry is the country's basic industry. The reason why it has developed so fast is not only related to its huge contribution to economic development, but also to its wide range of applications. [0003] Gordon Moore, one of the founders of Intel, proposed "Moore's Law" in 1965. The theorem states that the number of transistors o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L21/84H01L21/28
Inventor 张鹤鸣周春宇宋建军舒斌胡辉勇宣荣喜戴显英郝跃
Owner XIDIAN UNIV
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