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Self-aligned-technology-based tri-polycrystal SOI (Silicon On Insulator), SiGe and HBT (Heterojunction Bipolar Transistor) integrated device and preparation method thereof

A self-alignment process and integrated device technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., and can solve the problems of low mechanical strength, high cost, incompatibility with wide application and development, etc.

Inactive Publication Date: 2012-10-10
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although GaAs and InP-based compound devices have superior frequency characteristics, their preparation process is more complicated than Si process, high cost, difficult to prepare large-diameter single crystal, low mechanical strength, poor heat dissipation performance, incompatibility with Si process and lack of SiO 2 Such passivation layer and other factors limit its wide application and development.

Method used

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  • Self-aligned-technology-based tri-polycrystal SOI (Silicon On Insulator), SiGe and HBT (Heterojunction Bipolar Transistor) integrated device and preparation method thereof
  • Self-aligned-technology-based tri-polycrystal SOI (Silicon On Insulator), SiGe and HBT (Heterojunction Bipolar Transistor) integrated device and preparation method thereof
  • Self-aligned-technology-based tri-polycrystal SOI (Silicon On Insulator), SiGe and HBT (Heterojunction Bipolar Transistor) integrated device and preparation method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0080] Embodiment 1: A self-aligned process is used to prepare a three-polycrystalline SOI SiGe HBT integrated device and a circuit method with a base thickness of 20 nm. The specific steps are as follows:

[0081] Step 1, epitaxial growth, as shown in Figure 2(a).

[0082] (1a) Select SOI substrate, the support material 1 of the substrate is Si, and the intermediate layer 2 is SiO 2 , The thickness is 150nm, the upper material 3 is doped with a concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;

[0083] (1b) Using chemical vapor deposition (CVD) method, at 600℃, grow a layer of N-type epitaxial Si layer 4 with a thickness of 50nm on the upper layer of Si material as a collector area, the doping concentration of this layer is 1 ×10 16 cm -3 .

[0084] Step 2, shallow trench isolation preparation, as shown in Figure 2 (b) and (c).

[0085] (2a) Using chemical vapor deposition (CVD) method, at 600℃, grow a layer of SiO with a thickness of 300nm on the surface of the epit...

Embodiment 2

[0116] Embodiment 2: Using a self-aligned process to prepare a three-polycrystalline SOI SiGe HBT integrated device and a circuit method with a base thickness of 40 nm, the specific steps are as follows:

[0117] Step 1, epitaxial growth, as shown in Figure 2(a).

[0118] (1a) Select an SOI substrate, the lower support material 1 of the substrate is Si, and the intermediate layer 2 is SiO 2 , The thickness is 300nm, the upper material 3 is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;

[0119] (1b) Using the chemical vapor deposition (CVD) method, at 700℃, grow a layer of N-type epitaxial Si layer 4 with a thickness of 80nm on the upper Si material as a collector area, the doping concentration of this layer is 5 ×10 16 cm -3 .

[0120] Step 2, shallow trench isolation preparation, as shown in Figure 2 (b) and (c).

[0121] (2a) Using chemical vapor deposition (CVD) method, at 700℃, grow a layer of SiO with a thickness of 400nm on the surface of the ep...

Embodiment 3

[0152] Embodiment 3: Using a self-aligned process to prepare a three-polycrystalline SOI SiGe HBT integrated device and circuit method with a base thickness of 60 nm, the specific steps are as follows:

[0153] Step 1, epitaxial growth, as shown in Figure 2(a).

[0154] (1a) Select an SOI substrate, the lower support material 1 of the substrate is Si, and the intermediate layer 2 is SiO 2 , The thickness is 400nm, and the upper material 3 is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;

[0155] (1b) Using the chemical vapor deposition (CVD) method, at 750℃, grow a layer of N-type epitaxial Si layer 4 with a thickness of 100nm on the upper Si material as a collector area, the doping concentration of this layer is 1 ×10 17 cm -3 .

[0156] Step 2, shallow trench isolation preparation, as shown in Figure 2 (b) and (c).

[0157] (2a) Using chemical vapor deposition (CVD), at 800℃, grow a layer of SiO with a thickness of 500nm on the surface of the epitax...

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Abstract

The invention is suitable for the technical field of semiconductor integrated circuits, and provides a self-aligned-technology-based tri-polycrystal SOI (Silicon On Chip), SiGe and HBT (Heterojunction Bipolar Transistor) integrated device and a preparation method of the device. The preparation process is as follows: growing N type Si epitaxy on an SOI substrate, conducting photoetching on shallow-trench isolation region, preparing a shallow-trench isolator, etching and implanting phosphorous ions so as to form an electrode contact region, sequentially depositing SiO2, P-Poly-Si, SiO2 and nitride, etching a window in a base region, selectively growing a SiGe base region, conducting photoetching on a collector electrode window, depositing N type Poly-Si, removing Poly-Si except an emitting electrode and the collector electrode to form an HBT device, and finally forming an HBT integrated circuit with the base region being 20-60nm in thickness. The process method provided by the invention is compatible with a conventional processing process of CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuit, so that the SOI-based SIGeBi CMOS device and an integrated circuit can be prepared, and furthermore, the performance of a conventional analogue and digital-analogue mixed integrated circuit is improved greatly.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a three-polycrystalline SOI SiGe HBT integrated device based on a self-aligned process and a preparation method. Background technique [0002] Integrated circuits are the cornerstone and core of the economic development of the information society. As the U.S. engineering technology community recently mentioned the fifth electronic technology among the 20 greatest engineering achievements in the world in the 20th century, “from vacuum tubes to semiconductors and integrated circuits, it has become the cornerstone of intelligent work in various industries today.” One of the typical products that best reflects the characteristics of the knowledge economy. At present, the electronic information industry based on integrated circuits has become the world's largest industry. With the development of integrated circuit technology, the clear boundaries bet...

Claims

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Application Information

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IPC IPC(8): H01L29/737H01L29/08H01L21/331
Inventor 张鹤鸣王斌宣荣喜胡辉勇宋建军王海栋周春宇郝跃
Owner XIDIAN UNIV
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