A kind of soi BJT dual-strain plane BiCMOS integrated device and its preparation method
An integrated device and double-strain technology, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of low mechanical strength, complex preparation process compared with Si process, and incompatibility
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Embodiment 1
[0096] Embodiment 1: Prepare SOI BJT, dual strain plane BiCMOS integrated device and circuit with conductive channel of 45nm, the specific steps are as follows:
[0097] Step 1, epitaxial growth.
[0098] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 150nm, and the upper material is doped with a concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;
[0099] (1b) Thermally oxidize a layer of SiO with a thickness of 300nm on the substrate surface 2 layer.
[0100] Step 2, isolation area preparation.
[0101] (2a) Epitaxially grow a layer with a doping concentration of 1×10 on the SOI substrate 16 cm -3 The Si layer, with a thickness of 200nm, serves as the collector area;
[0102] (2b) Thermally oxidize a layer of SiO with a thickness of 300nm on the substrate surface 2 layer;
[0103] (2c) In the photolithographic isolation area, a deep trench with a dept...
Embodiment 2
[0145] Embodiment 2: The preparation of SOI BJT with a conductive channel of 30nm, double strained plane BiCMOS integrated devices and circuits, the specific steps are as follows:
[0146] Step 1, epitaxial growth.
[0147] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 300nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;
[0148] (1b) Thermally oxidize a layer of SiO with a thickness of 400nm on the substrate surface 2 layer.
[0149] Step 2, isolation area preparation.
[0150] (2a) Epitaxially grow a layer with a doping concentration of 5×10 on the SOI substrate 16 cm -3 The Si layer, with a thickness of 350nm, serves as the collector area;
[0151] (2b) Thermally oxidize a layer of SiO with a thickness of 400nm on the surface of the substrate 2 layer;
[0152] (2c) In the photolithographic isolation area,...
Embodiment 3
[0194] Embodiment 3: prepare SOI BJT, dual strain plane BiCMOS integrated device and circuit with conductive channel of 22nm, the specific steps are as follows:
[0195] Step 1, epitaxial growth.
[0196] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;
[0197] (1b) Thermally oxidize a layer of SiO with a thickness of 500nm on the surface of the substrate 2 layer.
[0198] Step 2, isolation area preparation.
[0199] (2a) Epitaxially grow a layer with a doping concentration of 1×10 on the SOI substrate 17 cm -3 The Si layer, with a thickness of 400nm, serves as the collector area;
[0200] (2b) Thermally oxidize a layer of SiO with a thickness of 500nm on the substrate surface 2 layer;
[0201] (2c) In the photolithographic isolation area, a deep trench with...
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