A mixed crystal plane strain Si vertical channel Bicmos integrated device and its preparation method
A vertical channel, mixed crystal plane technology, used in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of limitation, low mobility of Si material carrier materials, etc.
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Embodiment 1
[0111] Embodiment 1: Prepare 22nm mixed crystal plane strained Si vertical channel BiCMOS integrated device and circuit, the specific steps are as follows:
[0112] Step 1, SOI substrate material preparation.
[0113] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0114] (1b) Select the N-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;
[0115] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0116] (1d) Put the oxide layer on the surface of the polished ...
Embodiment 2
[0169] Embodiment 2: Prepare 30nm mixed crystal plane strained Si vertical channel BiCMOS integrated device and circuit, the specific steps are as follows:
[0170] Step 1, SOI substrate material preparation.
[0171] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0172] (1b) Select the N-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;
[0173] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0174] (1d) Put the oxide layer on the surface of the polishe...
Embodiment 3
[0227] Embodiment 3: Preparation of 45nm mixed crystal plane strained Si vertical channel BiCMOS integrated device and circuit, the specific steps are as follows:
[0228] Step 1, SOI substrate material preparation.
[0229] (1a) Select the N-type doping concentration as 5×10 15 cm -3 Si wafers with a crystal plane of (100) are oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0230] (1b) Select the N-type doping concentration as 5×10 15 cm -3 The Si wafer, the crystal plane is (110), the surface is oxidized, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower active layer;
[0231] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0232] (1d) Put the oxide layer on the surface of the polis...
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