Crystal plane-based Tri-polycrystal-plane Bi CMOS (Complentary Metal-Oxide-Semiconductor) integrated device and preparation method thereof

A technology for integrating devices and devices, which is applied in the field of three-poly planar BiCMOS integrated devices and fabrication based on crystal plane selection, and can solve problems such as limitation and low mobility of Si material carrier materials.

Inactive Publication Date: 2012-10-10
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Due to the low mobility of Si material carrier materials, the performance of integrated circuits manufactured using Si BiCMOS technology, especially the frequency performance, is greatly limited; for SiGe BiCMOS technology, although SiGe HBT is used for bipolar transistors, However, Si CMOS is still used for unipolar devices that restrict the improvement of the frequency characteristics of BiCMOS integrated circuits, so these limit the further improvement of the performance of BiCMOS integrated circuits

Method used

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  • Crystal plane-based Tri-polycrystal-plane Bi CMOS (Complentary Metal-Oxide-Semiconductor) integrated device and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0133] Embodiment 1: Prepare 22nm three-polycrystalline planar BiCMOS integrated device and circuit based on crystal face selection, the specific steps are as follows:

[0134] Step 1, SOI substrate material preparation.

[0135] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0136] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;

[0137] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

[0138] (1d) SiO on the surface of the lower and upp...

Embodiment 2

[0205] Embodiment 2: Prepare 30nm three-polycrystalline planar BiCMOS integrated device and circuit based on crystal plane selection, the specific steps are as follows:

[0206] Step 1, SOI substrate material preparation.

[0207] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0208] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;

[0209] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;

[0210] (1d...

Embodiment 3

[0277] Embodiment 3: Prepare 45nm three-polycrystalline planar BiCMOS integrated device and circuit based on crystal face selection, the specific steps are as follows:

[0278] Step 1, SOI substrate material preparation.

[0279] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0280] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si wafer with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;

[0281] (1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;

[0282] (1d) SiO on the surface of the lower and upper substrate ...

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Abstract

The invention discloses a crystal plane-based tri-polycrystal-plane Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and a preparation method of the device. The preparation process is as follows: preparing an SOI (Silicon On Insulator) substrate; growing N type Si epitaxy and preparing a deep-trench isolator so as to form a collector electrode contact region and a nitride side wall, etching a window in a base region, growing a SiGe base region, conducting photoetching on a collector electrode window, depositing N type Poly-Si, and preparing an emitting electrode and the collector electrode to form an HBT (Heterojunction Bipolar Transistor) device; etching a deep trench in an NMOS (N-Channel Metal Oxide Semiconductor) device region, selectively growing a strain Si epitaxial layer with a crystal plane (100) to prepare an NMOS device with a Si channel; selectively growing a strain SiGe epitaxial layer with a crystal plane (110) to prepare a PMOS (P-Channel Metal Oxide Semiconductor) device with a SiGe channel, and thus forming the crystal plane-based tri-polycrystal-plane Bin CMOS integrated device and a circuit. According to the crystal plane-based tri-polycrystal-plane Bi CMOS integrated device and the preparation method, the characteristics that the electronic mobility of tensile strain Si material is higher than that of Si material, the electronic mobility of strain SiGe material is higher than of that of body Si material, and the electronic mobility is anisotropic are utilized, and based on the SOI substrate, the plane Bi CMOS integrated circuit is prepared, and the performance of the Bi CMOS integrated device is enhanced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a three-polycrystalline plane BiCMOS integrated device and a preparation method based on crystal plane selection. Background technique [0002] In the contemporary era of highly developed information technology, microelectronic technology represented by integrated circuits is the key to information technology. As the fastest-growing, most influential and most widely used technology in human history, integrated circuits have become an important symbol to measure a country's scientific and technological level, comprehensive national strength and national defense strength. [0003] "Moore's Law", which has had a huge impact on the development of the microelectronics industry, states that the number of transistors on an integrated circuit chip doubles approximately every 18 months, and the performance also doubles. For more than 40 years, the wo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/84
Inventor 胡辉勇张鹤鸣李妤晨宋建军宣荣喜舒斌戴显英郝跃
Owner XIDIAN UNIV
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