Crystal plane-based Tri-polycrystal-plane Bi CMOS (Complentary Metal-Oxide-Semiconductor) integrated device and preparation method thereof
A technology for integrating devices and devices, which is applied in the field of three-poly planar BiCMOS integrated devices and fabrication based on crystal plane selection, and can solve problems such as limitation and low mobility of Si material carrier materials.
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Embodiment 1
[0133] Embodiment 1: Prepare 22nm three-polycrystalline planar BiCMOS integrated device and circuit based on crystal face selection, the specific steps are as follows:
[0134] Step 1, SOI substrate material preparation.
[0135] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0136] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;
[0137] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0138] (1d) SiO on the surface of the lower and upp...
Embodiment 2
[0205] Embodiment 2: Prepare 30nm three-polycrystalline planar BiCMOS integrated device and circuit based on crystal plane selection, the specific steps are as follows:
[0206] Step 1, SOI substrate material preparation.
[0207] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0208] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;
[0209] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;
[0210] (1d...
Embodiment 3
[0277] Embodiment 3: Prepare 45nm three-polycrystalline planar BiCMOS integrated device and circuit based on crystal face selection, the specific steps are as follows:
[0278] Step 1, SOI substrate material preparation.
[0279] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0280] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si wafer with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;
[0281] (1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;
[0282] (1d) SiO on the surface of the lower and upper substrate ...
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