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16 results about "Semiconductor wafer fabrication" patented technology

Semiconductor wafer fabrication is defined as process for production of photonic and electrical circuits which include LEDs, RF (radio frequency) amplifiers, and, optical computer components.

A preparation process for simultaneously obtaining an ultrathin lithium niobate piezoelectric single crystal wafer and a hetero thin film bonded substrate

PendingCN122270032AWaferPhysical chemistry
This application discloses a fabrication process for simultaneously obtaining an ultrathin lithium niobate piezoelectric single crystal wafer and a heterogeneous thin-film bonding substrate, belonging to the field of semiconductor wafer fabrication technology. The process includes the following steps: (1) ion implantation of a rotated tangential lithium niobate wafer, with the ion implantation dose gradually increasing from the center of the wafer outwards; pre-annealing of the substrate wafer; (2) activation and bonding of the ion implantation surface of the lithium niobate wafer obtained in step (1) to the substrate wafer to obtain a bond; (3) a two-step thinning process to reduce the thickness of the lithium niobate wafer to 40-200 μm; (4) annealing of the bond after thinning in step (3) to obtain an ultrathin lithium niobate piezoelectric single crystal wafer and a heterogeneous thin-film bonding substrate. This process, by processing the substrate wafer and the lithium niobate wafer, can simultaneously obtain a non-destructive ultrathin lithium niobate piezoelectric single crystal wafer and a heterogeneous thin-film bonding substrate, meeting the current demand for ultrathin lithium niobate piezoelectric single crystal wafers.
Owner:DABO TECHNOLOGY (SHANGHAI) CO LTD

Matchless plasma source for semiconductor wafer fabrication

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.
Owner:LAM RES CORP

Silica sol and its manufacturing method, polishing composition, polishing method, semiconductor wafer manufacturing method, and semiconductor device manufacturing method

PendingJP2026060294AOther chemical processesSilicon compoundsPulse nuclear magnetic resonanceDevice material
This invention provides a silica sol and polishing composition that has a large amount of water trapped on the surface of silica particles, can maintain this state of trapped water even under high-temperature conditions, and exhibits high dispersion stability even when the temperature is increased. [Solution] A silica sol containing silica particles, wherein the transverse relaxation time of nuclide 1H at a temperature of 25°C, as measured by the CPMG method using a pulsed NMR spectrometer, is 400 ms or less, and the temperature dependence of the transverse relaxation time obtained by subtracting the transverse relaxation time at 25°C from the transverse relaxation time at 40°C is less than 100 ms.
Owner:MITSUBISHI CHEM CORP

Method for manufacturing semiconductor wafers for bonding, method for manufacturing composite substrates, and semiconductor wafers for bonding

PendingJP2026084948ACrystallographyWafering
The present invention provides a method for manufacturing semiconductor wafers for bonding and a method for manufacturing composite substrates that allow for easy removal of knife edges. [Solution] An annular groove 12 is formed on one side of a flattened wafer 11, concentric with the outer circumference of the wafer 11 and having a predetermined width and depth. Subsequently, the inside of the groove 12 is filled with oxide to obtain a bonding semiconductor wafer 21 for bonding to a support substrate 22. Then, the side of the bonding semiconductor wafer 21 with the groove 21 formed thereon is bonded to the support substrate 22, and subsequently, the unnecessary portion is removed using the annular groove 22 (oxide) as a boundary to obtain a composite substrate 41 from which the knife edge has been easily removed.
Owner:GLOBALWAFERS JAPAN

Silica particle, production method for silica particle, silica sol, polishing composition, polishing method, manufacturing method for semiconductor wafer, and manufacturing method for semiconductor device

An object of the present invention is to provide a silica particle in which a metal content, particularly a content of a specific metal, has been significantly reduced. The gist of the present invention is as follows. A silica particle satisfying at least one of the following characteristics (a) to (c). (a) A content of sodium is 15 ppb by mass or less. (b) A content of potassium is 5 ppb by mass or less. (c) A content of calcium is 9 ppb by mass or less.
Owner:MITSUBISHI CHEM CORP

Polishing head, polishing apparatus, and method for manufacturing semiconductor wafers

To provide a two-zone membrane head which can improve in-plane uniformity of a polished amount of a surface to be polished of a workpiece.SOLUTION: A polishing head includes a first annular member, a closing member which closes an upper surface side opening of an opening part of the first annular member, a membrane which closes a lower surface side opening of the opening part of the first annular member, and a second annular member which is positioned below the membrane and has an opening part for holding a workpiece to be polished. When a direction toward a center of the opening part of the first annular member is an inner side and the other direction is an outer side, a space formed by closing the opening part of the first annular member by the closing member and the membrane is partitioned into an inner side space and an outer side space by an annular partitioning wall of which an upper annular connection part is connected to the closing member and of which a lower annular connection part is connected to the membrane. An inner diameter of the lower annular connection part of the annular partitioning wall is larger than an inner diameter of the second annular member. A radius of the upper annular connection part of the annular partitioning wall is 33%-90% when a radius of the workpiece to be polished at an installation position is 100%.SELECTED DRAWING: Figure 1
Owner:SUMCO CORP

Finishing assembly and method of making same

PendingCN122274847ASemiconductor wafer fabricationMechanical engineering
This invention discloses a trimming component and its manufacturing method, belonging to the field of semiconductor wafer fabrication technology. The trimming component includes a base and a grinding structure disposed on the base. The grinding structure includes: a first porous metal layer disposed on one side of the base; multiple grinding particles; the multiple grinding particles are embedded into the first porous metal layer through a first surface, with the tip of each grinding particle protruding from a second surface to form a grinding part; each drum-shaped part is covered by the first porous metal layer and mechanically held to form a support part; a solder layer is used to bond the first porous metal layer and the multiple grinding particles. A manufacturing method is also disclosed. This invention allows the drum-shaped part to be covered inside the first porous metal layer, forming a mechanical self-locking mechanism. At the same time, the metal solder directly enters from the first surface side and fully fills the deformation area caused by the insertion, achieving a deep fusion of mechanical holding and metallurgical bonding of the metal solder in the key areas of the drum-shaped part, forming a double reinforcement.
Owner:TIANJIN JINGXIN TECH DEV CO LTD

Matchless plasma source for semiconductor wafer fabrication

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.
Owner:LAM RES CORP

Standby energy-saving structure system and energy-saving method thereof

PendingCN122039211APolycrystalline material growthFrom chemically reactive gasesSemiconductor wafer fabricationHeat energy
The invention belongs to the technical field of semiconductor wafer manufacturing, and particularly relates to a standby energy-saving structure system and an energy-saving method thereof. The invention provides a standby energy-saving structure system which comprises a reaction cavity, a base, a heater, a control system, a gas inlet and a multi-layer coaxial nozzle, and the multi-layer coaxial nozzle comprises a first gas channel used for conveying a metal organic source, an isolation channel, a second gas channel used for conveying a hydride source, a heating resistance wire and a phase change heat storage layer. According to the structure system, the splitting decomposition efficiency of NH3 can be improved by utilizing heat energy in a standby stage, and the splitting decomposition efficiency is quickly released when production is recovered, so that the energy consumption is reduced, the preheating time is shortened, the production efficiency is improved, a heat flow path is naturally switched only by putting in / moving out a wafer, and the structure is simplified and reliable.
Owner:SHANGHAI UNIV OF ENG SCI

Matchless plasma source for semiconductor wafer fabrication

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.
Owner:LAM RES CORP

Semiconductor sample evaluation method, semiconductor sample evaluation device, and semiconductor wafer manufacturing method

PendingEP4672307A1Semiconductor/solid-state device testing/measurementCurrent density measurementsWaferingPhotoconductive decay
Provided is a semiconductor sample evaluation method including acquiring, a plurality of times, a decay curve by performing measurement on a semiconductor sample which is an evaluation target in accordance with a photoconductive decay method while changing a surface charge density; performing signal data processing using a model expression including an exponential decay term and a constant term on at least one decay curve among decay curves obtained through the plurality of measurements; obtaining a recombination lifetime τeff of the semiconductor sample from an exponential decay expression obtained through the signal data processing; obtaining a quadratic function, in which a surface charge density related value is represented by a variable x and a value related to the constant term is represented by a variable y, from measurement results obtained through the plurality of measurements; and obtaining a surface recombination lifetime τs of the semiconductor sample from the quadratic function.
Owner:SUMCO CORP

Lot delivery control method, system and lot delivery drone

This application provides a method, system, and drone for LOT (Local Object) transport control, relating to the field of semiconductor wafer fabrication technology. The method is applied to a first LOT transport drone, which is equipped with a fixing device for securing the LOT. First, the target endpoint position and transport route are acquired, and the drone flies according to the transport route. Then, obstacle information is detected in real time. If an obstacle is detected, obstacle avoidance is performed in three-dimensional space, and after obstacle avoidance, the drone returns to the transport route until the target endpoint position is reached. The LOT transport control method, system, and drone provided in this application have the advantage of improved transport efficiency.
Owner:捷捷微电(南通)科技有限公司

Silica sol and its manufacturing method, polishing composition, polishing method, semiconductor wafer manufacturing method, and semiconductor device manufacturing method

PendingJP2026060295AOther chemical processesSilicon compoundsPulse nuclear magnetic resonanceSilica particle
The present invention provides a silica sol and polishing composition in which the amount of water confined to the surface of silica particles does not change even when the temperature is changed, thereby suppressing the decrease in dispersion stability due to the reduction of surface hydration water and the occurrence of scratches on the workpiece when used for polishing. [Solution] A silica sol containing silica particles in which the absolute value of the rate of change of the specific relaxation rate at 40°C relative to the specific relaxation rate at 25°C, as measured by the CPMG method using a pulsed NMR spectrometer, is 30% or less.
Owner:MITSUBISHI CHEM CORP

Matchless plasma source for semiconductor wafer fabrication

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.
Owner:LAM RES CORP

Process for manufacturing a micro-electro-mechanical device from a single semiconductor wafer and related MEMS device

The present disclosure is directed to a process for manufacturing a micro-electro-mechanical system (MEMS) device. The process includes, in part, forming a first sacrificial dielectric region on a semiconductor wafer; forming a structural layer of semiconductor material on the first sacrificial dielectric region; forming a plurality of first openings through the structural layer; forming a second sacrificial dielectric region on the structural layer; forming a ceiling layer of semiconductor material on the second sacrificial dielectric region; forming a plurality of second openings through the ceiling layer; forming on the ceiling layer a permeable layer; selectively removing the first and the second sacrificial dielectric regions; and forming on the permeable layer a sealing layer of semiconductor material.
Owner:STMICROELECTRONICS SRL

A semiconductor wafer chucking device for thin film deposition

PendingCN122428246ACharge injectionWafering
This invention relates to the field of semiconductor wafer fabrication and discloses a semiconductor wafer clamping device for thin film deposition, including a chuck substrate and a controller. An adsorption electrode is embedded inside the chuck substrate. A pin channel extending along the thickness direction is formed within the chuck substrate. The clamping device also includes a wafer desorption and lifting module, which comprises: a high-frequency power supply for applying radio frequency voltage to the adsorption electrode; a gas introduction unit for introducing ionized gas into the pin channel; and a pin assembly. The pin assembly is disposed within the pin channel and includes a pin body and a drive mechanism for driving the pin body to rise and fall. A pre-charging unit, electrically connected to the pin body, is used to apply a voltage with the opposite polarity to the residual charge of the electrostatic chuck to the pin body before the pin body performs a lifting action. This invention, through the cooperation of the pre-charging unit, the high-frequency power supply, and the gas introduction unit, forms a dual electrostatic elimination process of pre-charging injection of reverse charge and plasma neutralization.
Owner:WUXI SHENGTENG SEMICON TECH CO LTD