307 results about "Wafer fabrication" patented technology

The invention provides a wafer-level test yield prediction and process optimization method and system based on big data, and relates to the technical field of wafer-level tests.The wafer-level test yield prediction and process optimization method comprises the steps that wafer manufacturing process data is obtained, a time-sequence-sensitive multi-modal data fusion network is constructed, a LSTM and GNN combined mixed architecture is adopted, and a multi-modal data fusion network is constructed; self-adaptive weight distribution is carried out through an attention mechanism to predict the yield; and when the predicted yield is lower than a threshold value, triggering a layered progressive process optimization system, and adjusting process parameters through an equipment parameter optimization layer and a process level optimization layer. According to the invention, the accurate prediction of the wafer test yield and the automatic optimization of the process parameters are realized, the production efficiency is improved, and the manufacturing cost is reduced.

The invention discloses an automatic identification method and system for a wafer internal defect image of a 3D stacked chip, and belongs to the technical field of semiconductor manufacturing and detection. According to the method, optical, X-ray and ultrasonic image data are synchronously acquired based on a multi-modal imaging technology, imaging parameters are dynamically adjusted to adapt to different wafer levels and material characteristics, multi-modal features are extracted in combination with layered filtering and denoising, multi-resolution registration and a self-supervised deep learning method, and micron-sized defects are positioned by using an attention mechanism. And further constructing a defect-process parameter correlation model through reinforcement learning, generating a closed-loop process optimization instruction, and transmitting the closed-loop process optimization instruction to an execution system. The system comprises a multi-modal imaging module, a noise suppression module, a deep learning analysis module and a process optimization module, and supports edge computing deployment. According to the invention, the internal defect detection efficiency and precision of the multi-layer stacked chip are significantly improved, real-time closed-loop control of detection-analysis is realized, the wafer manufacturing quality risk is reduced, and the method is suitable for intelligent defect detection of an advanced packaging production line.

The invention belongs to the field of industrial automation, focuses on industrial robots in the field of semiconductor wafer manufacturing, and provides a system based on multi-mode sensing and intelligent decision making. A plurality of sensors are integrated on a robot and equipment, technologies of multi-sensor fusion, multi-modal data fusion, multi-physical field monitoring and the like are applied, and algorithms of dynamic trajectory planning, deep learning, adaptive control, reinforcement learning, digital twinning and virtual simulation and the like are combined; high-precision wafer carrying, rapid surface defect detection, thin film deposition process optimization, multi-robot collaborative scheduling and manufacturing process overall optimization are achieved, and the problems of precision, efficiency and quality in wafer manufacturing in the prior art are solved.

The invention discloses a wafer process data analysis method based on Ftest inspection, and belongs to the technical field of wafer process data analysis. The method is realized based on a wafer process data analysis system, and the system comprises a data acquisition module, a database, a data processing module, a critical value confirmation module, a calculation and analysis module and an intelligent adjustment module. According to the method, logic grouping is carried out on detection parameters after wafer processing is finished, and Ftest inspection analysis is carried out, so that the problem of accurately identifying and analyzing a complex relationship between groups in massive wafer processing data is effectively solved, and the integrity and comprehensiveness of wafer processing data analysis are reflected; according to specific requirements of the wafer manufacturing industry, the variance of different detection parameter groups and the F statistical magnitude between the variance of the different detection parameter groups are calculated, abnormal setting parameters influencing the wafer performance can be rapidly identified, a wafer processing machine table is controlled to automatically correct the abnormal setting parameters, and the production and processing quality of wafers is improved.

The invention provides a semiconductor test structure and a test method thereof. The semiconductor test structure is arranged on a scribing channel of a wafer, and comprises a transistor which comprises a substrate, a source electrode, a drain electrode and a grid electrode; the electric fuse comprises a first end and a second end; wherein the source electrode is electrically connected to the first bonding pad through a first metal wire, the second end of the electric fuse is electrically connected to the second bonding pad through a second metal wire, the drain electrode, the substrate and the first end of the electric fuse are electrically connected to the third bonding pad through corresponding third metal wires, and the grid electrode is electrically connected to the fourth bonding pad through a fourth metal wire. Voltage is applied to the first bonding pad, the second bonding pad, the third bonding pad and the fourth bonding pad by adopting a preset rule so as to test the resistance of the electric fuse and the performance of the transistor. According to the technical scheme, the resistance of the electric fuse and the performance of the transistor can be simultaneously monitored in the line in the wafer manufacturing process, the process is rapidly adjusted, and the flexibility of the process is improved.

The invention provides a scheduling method, device and equipment of a wafer manufacturing system. The method comprises the following steps: constructing a time Petri net model by adopting a Petri net model according to a wafer processing route and constraint conditions; the constraint condition is the time delay added on the transition or library; an incidence matrix of the time Petri net model is calculated, and the incidence matrix is used for calculation to obtain the number of times of emission; the emission times are emission times corresponding to each transition from the initial identifier to the target identifier under the time Petri network model; operating the time Petri net model by using the launching times in combination with the shortest process time priority strategy, and processing the deadlock problem by adopting multi-step rollback in the operation process of the time Petri net model to obtain a scheduling result of the wafer manufacturing system; wherein the shortest process time priority strategy only reserves a preset number of enabling transitions under each identifier. And the generation efficiency of the scheduling result is improved on the basis of stable operation of the wafer manufacturing system.

The invention provides a fuzzy knowledge graph construction method related to a wafer manufacturing process, and relates to the technical field of fuzzy knowledge graphs, and the method comprises the steps: employing a three-dimensional convolutional network to extract a spatial defect feature X of a scanning electron microscope image, carrying out the coding of sensor time series data through a bidirectional LSTM, and obtaining a feature set Y, obtaining electrical performance parameters of the wafer based on impedance spectroscopy analysis from the text to obtain a feature set Z; building fuzzy knowledge based on the text to reinforce the feature sets X, Y and Z, building a fuzzy feature set and a time sequence feature set, building a weighted scoring model, and screening a candidate set from the text according to the weighted scoring model; information is extracted from the candidate set, and a tetrad structure G = (entities, relationships, time attributes and fuzzy rules) is constructed; and taking G as input, generating a time sequence fuzzy rule through a recursive reconstruction contribution method, and incrementally updating the knowledge graph. According to the method, the characterization bottleneck of space-time coupling and uncertainty correlation in a traditional method is broken through.

The invention relates to the technical field of wafer processing, in particular to a wafer positioning and clamping concentricity clamping device and method, and the device comprises at least three groups of clamping units. The clamping unit comprises a driving module, a transmission module and a sensing module; the driving module comprises a cylinder and an independent gas circuit for driving the cylinder; the transmission module comprises a multi-connecting-rod mechanism connected with a piston rod of the air cylinder. The movable end of the multi-connecting-rod mechanism is provided with a clamping column used for making contact with the edge of the wafer. The sensing module comprises a position sensor and a thin film pressure sensor. Each clamping unit is provided with an independent electromagnetic valve and an independent gas circuit, closed-loop feedback of a position sensor is introduced, and accurate and synchronous control over the movement tracks of the multiple clamping columns is completed; and a thin film pressure sensor is arranged at a force bearing point of the clamping column, and a self-adaptive force control module of the control system is combined, so that the technical effect that the clamping force is always stabilized in a preset safety range is achieved.

The invention relates to a multi-operation-area collaborative pre-scheduling method for a wafer manufacturing system, and the method comprises the following steps: constructing a constrained multi-target mathematical model, taking the minimization of total tardiness and total production cost as a target function, and fully considering the influence of multi-time-window constraints; and designing a double-population evolutionary algorithm, wherein the double-population evolutionary algorithm comprises a normal population responsible for exploring diversity of a solution space and a convergence population of a solution space. In the evolutionary process, the two populations dynamically cooperate with each other. And designing a mixed agent auxiliary model based on the RBF and the SVM. An agent model is updated through an online learning strategy, the prediction precision of the model is improved, and it is ensured that the algorithm can explore more feasible regions; and the multi-operation-area pre-scheduling controller of the wafer manufacturing system receives the new order information, triggers algorithm execution and generates a scheduling scheme. The problem of low scheduling efficiency and solution quality in multi-target pre-scheduling of the wafer manufacturing system is solved, the convergence and uniformity of a population and the number of feasible solutions are enhanced, and the total tardiness and the total production cost are effectively balanced.

The invention relates to the technical field of wafer manufacturing, and discloses a wafer clamp, semiconductor equipment and an electroplating method. The wafer clamp comprises a base, a sealing ring and a pressure head; the base is annular, the sealing ring is installed on the base, the pressing head can cover the base and exert sealed external pressure on the back face of the wafer so that the wafer can abut against the sealing ring, and at the moment, an annular space is formed between the base and the pressing head. The external non-electroplating surface of the wafer limited by the outermost contact boundary defined by the pressing head and the sealing ring after the pressing head and the sealing ring are in contact with the wafer is located in the annular space; the wafer clamp is further provided with an air inlet structure, one end of the air inlet structure is communicated with an air source, the other end of the air inlet structure is communicated with the annular space, and the air inlet structure is used for blow-drying the external non-electroplating surface of the wafer before the wafer is electroplated. Even in an electroplating process with relatively long process time, the wafer clamp can effectively prevent electroplating liquid from entering the wafer clamp, so that the non-electroplating surface outside the wafer is prevented from being corroded; and the clamp and the sealing ring are prevented from being polluted by electroplating liquid.

The embodiment of the invention provides a wafer-level lithium niobate heterogeneous bonding method, which relates to the technical field of silicon optical heterogeneous integration, and comprises the following steps: respectively preparing a silicon optical wafer, a circuit wafer and a lithium niobate wafer; bonding the first SiO2 cladding of the silicon optical wafer with the first side of the lithium niobate film of the lithium niobate wafer; and bonding the second SiO2 cladding of the circuit wafer with the second side of the lithium niobate film of the lithium niobate wafer. According to the scheme, the problems that the wafer is difficult to process and the bonding difficulty is increased due to the fact that an optical / electric functional structure intersects in the wafer manufacturing process are solved, photoelectric separation in the silicon optical-lithium niobate heterogeneous integrated wafer manufacturing process is achieved, and efficient bonding is achieved.

The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer manufacturing sign-off method and system. By constructing an agile sign-off framework combining chip design and production process data and fusing high-level abstract analysis and high-precision process modeling capability, efficient verification, real-time verification and rapid optimization of a manufacturing process are realized, so that manufacturability, performance and quality of a chip are guaranteed, and production yield and sign-off efficiency are improved.

The invention discloses a wafer grinding disc structure detection method and a related device. The method comprises the following steps: applying a constant friction load to the surface of a wafer grinding disc to obtain a micro-area thermal response parameter; fitting to obtain a micro-area thermal diffusion reference parameter; real-time thermal diffusion parameters are recorded in the machining process, deviation values of the real-time thermal diffusion parameters and the reference parameters are calculated, and a thermal response deviation matrix is obtained; analyzing thermal diffusion characteristic differences of adjacent micro-regions, constructing thermal coupling network parameters, and determining thermal islands and thermal barrier regions; cooling liquid flow parameters of the areas are recorded, and cooling efficiency decline indexes are obtained; and through collaborative analysis of thermal field evolution and cooling liquid response, the physical performance degradation degree of the grinding disc surface micro-area is judged. According to the method, the dynamic change of the micro-area temperature field on the surface of the grinding disc can be accurately captured in real time in a high-speed rotating wet environment, the surface performance degradation trend of the grinding disc is recognized in advance through multi-dimensional correlation analysis of a thermal response track, a thermal coupling network and cooling liquid behaviors, and the wafer manufacturing yield and quality consistency are effectively improved.

The invention relates to the technical field of SiC wafer manufacturing, in particular to a platform and method for stripping a SiC wafer after laser implicit cutting of a SiC crystal ingot, and the platform comprises an upper force application fixing part which is used for connecting the to-be-stripped SiC wafer of the SiC crystal ingot; the lower force application fixing part is used for connecting the remaining SiC crystal ingots of the SiC crystal ingots; the shearing force driving part is connected with the upper force application fixing part and the lower force application fixing part, and after the interior of the to-be-stripped SiC wafer is modified by laser, and the interface of the to-be-stripped SiC wafer and the remaining SiC crystal ingot is modified to form a laser scribing modified trace, the shearing force driving part drives the upper force application fixing part and the lower force application fixing part to move in a staggered manner, so that the to-be-stripped SiC wafer is stripped. And the to-be-stripped SiC wafer and the residual SiC crystal ingot are staggered and separated. The platform and the method for stripping the SiC wafer after the laser implicit cutting of the SiC crystal ingot have the advantages of high efficiency, high precision, low cost and the like.

The invention belongs to the field of wafer manufacturing, and discloses a knowledge reasoning method and device for an integrated circuit wafer process and a medium, and the method comprises the steps: carrying out the extraction of multi-modal features of a wafer image; performing wafer knowledge retrieval; sorting the documents; and generating a query answer. Dynamic decomposition and high-precision solution of complex query are realized step by step through three core stages. An introduced multi-modal chain reasoning framework enables the model to combine logical reasoning and multi-modal information, and a coherent solution chain is constructed to cope with complex tasks.

The present invention provides a reactive collaborative scheduling optimization method and system for material distribution in multiple work areas of a wafer manufacturing system based on predictive self-collaborative reinforcement learning, comprising the following steps: constructing a total return prediction model for collaborative scheduling of material distribution in multiple work areas based on a deep neural network and training it; defining and designing a collaborative scheduling environment for material distribution in multiple work areas; constructing an intelligent agent for scheduling work areas; interacting with multiple agents and the collaborative scheduling environment for material distribution in multiple work areas to form and collect historical experience data for training multiple agents to learn optimal decision strategies and maximize total returns; integrating the intelligent agent model for scheduling wafer multi-work areas into the collaborative scheduling system for material distribution in multiple work areas of a wafer manufacturing system. The present invention realizes the collaborative scheduling optimization of material distribution in multiple work areas of a wafer manufacturing system through a predictive self-collaborative reinforcement learning method, which can effectively improve the collaborative scheduling performance of intelligent agents, and greatly reduces the production cycle of a wafer manufacturing system and reduces the number of times a wafer lot violates the residence time constraint of an work area through real-time collaborative scheduling of multiple work areas.

The purpose of the present invention is to provide an optical resin wafer manufacturing method which can obtain an optical resin wafer having an improved flatness property. An optical resin wafer having an improved flatness property can be obtained by said optical resin wafer manufacturing method comprising: a mold preparation step for preparing a mold that satisfies the following (a) or (b); and a curing step for obtaining an optical resin wafer precursor by casting and curing a curable composition serving as a raw material for the wafer in the mold.　(a) The mold has one or more spacers in the center of a cavity space.　(b) The relationship between the thickness tm0 at the center of the cavity space of the mold and the thickness tm1 at a position 5 mm from the outer circumference toward the center of the cavity space of the mold satisfies tm0>tm1.

The invention discloses a wafer cutting method, and relates to the technical field of wafer manufacturing, and the method comprises the steps: fixing a wafer, cutting a first layer of the wafer through a first cutter, forming a first cutting groove in the surface of the first layer, and enabling the depth of the first cutting groove to be smaller than the thickness of the first layer; the wafer is turned over, a second cutter is used for cutting a second layer of the wafer, a second cutting groove is formed in the surface of the second layer, the depth of the second cutting groove is smaller than the thickness of the second layer, and the projection of the first cutting groove and the projection of the second cutting groove on the surface of the wafer at least partially coincide; and sequentially cutting through the second layer and the first layer along the second cutting groove by using a third cutter. According to the invention, the first layer and the second layer are not cut through at the same time, the partial structures of the first layer and the second layer are reserved, and the wafer is cut through the third time of cutting. Therefore, when the wafer is cut in the prior art, the problems of damage and edge breakage are reduced, and the cutting quality and the processing precision of a subsequent module are improved.

This invention relates to a method for remote epitaxial growth of single-crystal lead-free perovskite microsheets on germanium, comprising the following steps: using CsBr and SnBr2 as source materials placed in a reaction region, using argon as a carrier gas, placing germanium-based graphene in a deposition region, and then heating to react the source materials, followed by evaporation and deposition onto the germanium-based graphene to form single-crystal lead-free perovskite microsheets. The method of this invention can obtain perovskite microsheets with good orientation and is environmentally friendly. Furthermore, germanium is a mature semiconductor material with well-established wafer fabrication, cleaning, and surface treatment processes, making large-scale production possible and providing a new path for perovskite to move from the laboratory to high-performance, multifunctional integrated optoelectronic devices.

This application relates to a method and product for preparing indium antimonide heterostructures that can reduce annealing thermal stress, belonging to the field of indium antimonide heterostructure manufacturing technology. The method includes: providing a donor indium antimonide substrate; forming an ion implantation layer, a weakening layer, and a residual substrate layer by ion implantation; providing a carrier indium antimonide substrate; depositing an Al2O3 passivation layer on the surfaces of the carrier indium antimonide substrate and the donor indium antimonide substrate; further depositing a SiO2 layer on the carrier indium antimonide substrate; bonding the SiO2 layer on the carrier indium antimonide substrate to the Al2O3 passivation layer on the donor indium antimonide substrate; annealing at a low temperature of ≤200℃ for 10~20h; peeling off the donor indium antimonide substrate; providing a SiC / Si substrate; bonding the peeled surface of the ion implantation layer to the SiC / Si substrate; and wet etching using BOE / DHF etching solution to obtain the heterostructure wafer.

The invention discloses a display device hard mask planarization method, which comprises the following steps of: 1, sequentially depositing an anode, an ITO (Indium Tin Oxide) layer and a hard mask layer on a substrate by using a CMOS (Complementary Metal Oxide Semiconductor) Wafer as the substrate; 2, yellow light gluing, exposure and development are carried out, a PR mask is left, PR removal is carried out after etching, then a film layer on the bottom layer of a PR covering area is left, and film layer protrusions caused by tungsten holes appear; 3, yellow light gluing, exposure and development are carried out, a concave PR mask structure is formed, a convex mask part is subjected to etching treatment, and a convex part is leveled; and if the PR mask still remains, processing the PR mask to remove the redundant PR. The display device hard mask planarization method is reasonable in design, pixel Hard Mask film planarization is achieved mainly through yellow light and the etching technology, equipment and cost input can be reduced, and the wafer manufacturing efficiency is improved by 20%; and the quality of the display device can be ensured.

A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

A wire electrical discharge machining (EDM) device comprises the following: a pair of wire parallel guide rollers arranged on both sides of a workpiece to hold the workpiece between them, each of these rollers having a plurality of wire guide grooves formed at equal intervals on an outer circumferential surface, the plurality of wire guide grooves causing a plurality of running cutting wire sections to fit into them and constraining the movement of the plurality of cutting wire sections; parallel wire extension position measuring units (52a, 52b) which measure a distance between a measuring reference surface set parallel to a virtual plane containing the plurality of cutting wire sections and a wire electrode forming the plurality of cutting wire sections;a wire guide groove detachment detection unit (53) that detects the occurrence of a change in distance based on a measurement result obtained from the parallel wire extension position measuring units (52a, 52b); and a wire condition determination unit (54) that determines, based on the detection result obtained from the wire guide groove detachment detection unit (53), whether it is a wire detachment condition in which at least one of the cutting wire sections has detached from the wire guide groove, or a wire contact condition in which all cutting wire sections are in contact with the wire guide grooves.

The embodiment of the invention provides a wafer acceptance test substrate, which mainly comprises an upper ceramic substrate and a lower ceramic substrate, and a circuit substrate is arranged between the upper ceramic substrate and the lower ceramic substrate to form a test substrate; therefore, the substrate is applied to a semiconductor process and a leakage current test in a wafer acceptance test process before a wafer enters the process, the flatness of the ceramic substrate is high, impedance and leakage current generated during detection can be reduced, wafer quality detection is improved, and the quality and stability of the wafer manufacturing process are ensured.

This invention relates to the field of wafer fabrication technology, and proposes a robotic arm and wafer cleaning process for testing various types of wafer products. The robotic arm includes side grippers, a middle gripper, a first power component, and a second power component. Two side grippers are provided, each with both elastic and rigid gripping portions. The middle gripper is positioned between the two side grippers and also has a rigid gripping portion. The first power component adjusts the Y-axis distance between the two side grippers and simultaneously adjusts the X-axis distance between the side grippers and the middle gripper. The second power component drives the side grippers to rotate about the Z-axis. By incorporating a first power component, this invention allows adjustment of the distance between the two side grippers, thus accommodating the gripping of wafers of different sizes and specifications, and enabling the removal of wafers from stacking containers, making it highly convenient to use. Furthermore, it facilitates adjustment of the gripping direction of the side grippers, further improving the ease of application.

The invention discloses a polishing method and system for controlling LTV at a marking hole of a SiC wafer, and relates to the technical field of semiconductor manufacturing. A polishing solution is adopted to carry out chemical mechanical polishing on the SiC wafer with the laser marking hole under the polishing process parameters; the polishing solution comprises a KMnO4 oxidizing agent with the mass fraction of 10% + / -3% and a mixed grinding material of Al2O3 and CeO2, the particle size of the Al2O3 grinding material is 250-350 nm, the particle size of the CeO2 grinding material is 80-120 nm, the mass ratio of Al2O3 to CeO2 is 1: 1, the mass fraction of Al2O3 and CeO2 in the polishing solution is 5%-6%, and the polishing solution is maintained to be acidic. The material removal rate of the marking hole area and the material removal rate of the wafer body area are highly consistent, the SiC wafer surface with the ultrahigh flatness is obtained, local thickness changes, caused by laser marking, around the marking hole are restrained, and the overall quality and yield of SiC wafer manufacturing are improved.

Semiconductor (SC) chip devices and associated methods of making are presented. The SC chips are designed to include enlarged extension semiconductor areas next to functional integrated circuit (IC) dies on these SC chips. Some variations include designing semiconductor wafers prior to fabrication so that the resultant IC dies are surrounded by the extension semiconductor areas. Other variations include processing post manufactured semiconductor wafers to expand the size of the available extension areas by including truncated pieces of IC dies that are immediately adjacent to functional working primary IC dies. These variations provide additional room for redistribution layers to fan-out from the IC dies outwards onto the extension areas.

A method for modeling a wafer profile by a function is provided, in which the function is used to calculate a displacement z in a thickness direction of a wafer and is a sum of multiple functions including a first function g(r), a second function Ar×h(Nθ), and a third function Br×i(M(θ-φ)). The first function g(r) indicates a first-order or higher-order polynomial with a distance r from the center of the wafer as a variable. The second function Ar×h(Nθ) indicates multiplying a sine or cosine function h(Nθ) by a first angle θ with respect to a predetermined position in a circumferential direction of the wafer as a variable and an integer N as a constant with a coefficient A and the distance r.The third function Br×i(M(θ-φ)) indicates multiplying a sine or cosine function i(M(θ-φ)) with the first angle θ as a variable, a second angle φ with respect to the predetermined position as a constant, and an integer M as a constant with a coefficient B and the distance r.

The invention relates to the technical field of wafer manufacturing, and discloses a high-pressure wafer bonding system in order to solve the technical problems that a temporary bonding adhesive layer is poor in uniformity extension and large in bonding thickness deviation, and the system comprises a bonding lower platform assembly which is used for bearing a wafer to be bonded; the bonding upper platform assembly is arranged above the bonding lower platform assembly, is arranged opposite to the bonding lower platform assembly and is used for applying bonding pressure; the vacuum system is arranged below the bonding lower platform assembly and used for providing a vacuum environment for a bonding cavity between the upper platform and the lower platform in the bonding process; wherein the bonding upper platform assembly realizes movement in the Z-axis direction through a lifting mechanism, and can apply bonding lower pressure not less than 50kN so as to realize high-uniformity bonding between a wafer and a carrier wafer. The upper bonding platform and the lower bonding platform are controlled by using the high-pressure bonding system, and the wafer and the carrier wafer are bonded together through the bonding layer in a downward flat pressing manner, so that the subsequent de-bonding process is simplified, and the wafer manufacturing cost is reduced.

The present invention is a temporary adhesive for wafer processing, which is used for temporarily bonding a wafer to a support. This temporary adhesive for wafer processing is composed of a curable silicone resin composition which can be cured by a hydrosilylation reaction. This curable silicone resin composition is a temporary adhesive for wafer processing, which characteristically contains an organopolysiloxane that has in each molecule only one alkenyl group or only one silicon atom-bonded hydrogen atom (SiH group). It is thereby possible to provide a temporary adhesive for wafer processing, a wafer laminate, and a method for producing thin wafers using same, which support an improved productivity for thin wafers, wherein, inter alia, an adequate substrate retention is exhibited post-bonding even when a substrate with high level differences is used; a high process compatibility is exhibited with wafer backside grinding processes, TSV formation processes, and wafer backside wiring processes; facile peeling is exhibited in peeling processes even after passage post-bonding through a lengthy high-temperature heating process in air; and the residue on the substrate post-peeling exhibits an excellent cleanability.