401 results about "Wafer fabrication" patented technology

The invention provides a method and system for analyzing defects in wafer manufacturing based on big data, and relates to the technical field of big data, and the method comprises the steps: collecting technological parameter information, defect scanning images and manufacturing process data information, and carrying out multi-scale feature pyramid network processing and fusion to obtain fusion features; the fusion features are analyzed through a deep learning network, the deep learning network adopts a multi-task learning framework to complete a defect classification task, a defect segmentation task and a defect evolution prediction task at the same time, consistency loss based on graph matching is introduced, and a defect type recognition result and a feature map of defect space distribution are obtained; based on the characteristic spectrum, when it is detected that the process parameters are abnormal, analyzing historical defect data by using a graph neural network containing a time sequence attention mechanism; technological parameter constraint conditions are set in combination with an expert knowledge base, and technological parameters are adaptively adjusted through a reinforcement learning method. According to the invention, the accuracy of defect detection and classification is improved.

The invention provides a wafer-level test yield prediction and process optimization method and system based on big data, and relates to the technical field of wafer-level tests.The wafer-level test yield prediction and process optimization method comprises the steps that wafer manufacturing process data is obtained, a time-sequence-sensitive multi-modal data fusion network is constructed, a LSTM and GNN combined mixed architecture is adopted, and a multi-modal data fusion network is constructed; self-adaptive weight distribution is carried out through an attention mechanism to predict the yield; and when the predicted yield is lower than a threshold value, triggering a layered progressive process optimization system, and adjusting process parameters through an equipment parameter optimization layer and a process level optimization layer. According to the invention, the accurate prediction of the wafer test yield and the automatic optimization of the process parameters are realized, the production efficiency is improved, and the manufacturing cost is reduced.

The invention discloses an automatic identification method and system for a wafer internal defect image of a 3D stacked chip, and belongs to the technical field of semiconductor manufacturing and detection. According to the method, optical, X-ray and ultrasonic image data are synchronously acquired based on a multi-modal imaging technology, imaging parameters are dynamically adjusted to adapt to different wafer levels and material characteristics, multi-modal features are extracted in combination with layered filtering and denoising, multi-resolution registration and a self-supervised deep learning method, and micron-sized defects are positioned by using an attention mechanism. And further constructing a defect-process parameter correlation model through reinforcement learning, generating a closed-loop process optimization instruction, and transmitting the closed-loop process optimization instruction to an execution system. The system comprises a multi-modal imaging module, a noise suppression module, a deep learning analysis module and a process optimization module, and supports edge computing deployment. According to the invention, the internal defect detection efficiency and precision of the multi-layer stacked chip are significantly improved, real-time closed-loop control of detection-analysis is realized, the wafer manufacturing quality risk is reduced, and the method is suitable for intelligent defect detection of an advanced packaging production line.

The invention provides an AI edge computing platform, method, terminal and system for a Fab system, and the platform is specially designed for the Fab system, is customized and developed according to the business data processing task requirements in each Fab system, is deployed at the edge side of a plurality of machine equipment of a wafer manufacturing plant, and is in communication connection with each machine equipment. The platform can collect and screen process parameter data meeting high-quality wafer standards, perform analysis processing by using a specific algorithm model, dynamically adjust machine equipment process parameters and compensate Fab system indexes according to an analysis result, and optimize machine equipment performance, a production process and the algorithm model. By combining edge calculation and the AI technology, low-delay processing and real-time analysis of semiconductor manufacturing equipment process parameters are achieved, the system processing efficiency and response speed are improved, meanwhile, full-process automatic management of equipment data processing is integrated, the manual intervention requirement is reduced, and the workload of developers is relieved.

The invention belongs to the field of industrial automation, focuses on industrial robots in the field of semiconductor wafer manufacturing, and provides a system based on multi-mode sensing and intelligent decision making. A plurality of sensors are integrated on a robot and equipment, technologies of multi-sensor fusion, multi-modal data fusion, multi-physical field monitoring and the like are applied, and algorithms of dynamic trajectory planning, deep learning, adaptive control, reinforcement learning, digital twinning and virtual simulation and the like are combined; high-precision wafer carrying, rapid surface defect detection, thin film deposition process optimization, multi-robot collaborative scheduling and manufacturing process overall optimization are achieved, and the problems of precision, efficiency and quality in wafer manufacturing in the prior art are solved.

The invention belongs to the technical field of semiconductor equipment calibration, and particularly relates to a wafer position error detection method and a wafer position error detection device, which are characterized in that a single position detection sensor is arranged on the side of a wafer transmission path so as to record and scan the non-circle center chord length and the endpoint position of the non-circle center chord length on a wafer; meanwhile, the position of the standard wafer is used as a reference standard system, so that the position coordinates of the end point positions, scanned by the position detection sensor, of the standard wafer and the to-be-detected wafer in the reference coordinate system are restored, and the deviation value of the circle center of the to-be-detected wafer in the second cavity and the circle center of the standard wafer is obtained; the position of the wafer to be measured is calibrated according to the deviation value, so that the process quality of wafer manufacturing can be improved; compared with a multi-sensor detection scheme, the wafer position calibration can be realized only by adopting a single position detection sensor, the calibration cost is lower, and replacement and maintenance are easy.

The invention relates to the technical field of wafer manufacturing, in particular to wafer character OCR (Optical Character Recognition) equipment. The first driving part and the second driving part are both loaded by the rack. Power sources for the wafer edge data pickup unit and the OCR recognition unit to execute translational motion are first driving parts, and the first driving parts and the wafer edge data pickup unit and the OCR recognition unit are oppositely arranged. The power source for the wafer bearing table to execute the planar motion is the second driving part. The wafer edge data pick-up unit can easily and effectively judge whether a wafer circle center and a notch thereof meet expected design requirements or not by picking up edge contour data of a wafer, the controller sends a control signal to the second driving part accordingly, the wafer bearing table can execute planar motion, and meanwhile, the wafer edge data pick-up unit can be used for driving the wafer bearing table to move. The controller synchronously sends a control signal to the wafer bearing table, and the wafer follows the wafer bearing table to perform a micro-speed circumferential rotation motion until the center and the gap of the wafer circle meet the expected design requirements, so that a subsequent OCR (Optical Character Recognition) unit can accurately and quickly recognize wafer characters.

The invention discloses a wafer process data analysis method based on Ftest inspection, and belongs to the technical field of wafer process data analysis. The method is realized based on a wafer process data analysis system, and the system comprises a data acquisition module, a database, a data processing module, a critical value confirmation module, a calculation and analysis module and an intelligent adjustment module. According to the method, logic grouping is carried out on detection parameters after wafer processing is finished, and Ftest inspection analysis is carried out, so that the problem of accurately identifying and analyzing a complex relationship between groups in massive wafer processing data is effectively solved, and the integrity and comprehensiveness of wafer processing data analysis are reflected; according to specific requirements of the wafer manufacturing industry, the variance of different detection parameter groups and the F statistical magnitude between the variance of the different detection parameter groups are calculated, abnormal setting parameters influencing the wafer performance can be rapidly identified, a wafer processing machine table is controlled to automatically correct the abnormal setting parameters, and the production and processing quality of wafers is improved.

The invention provides a semiconductor test structure and a test method thereof. The semiconductor test structure is arranged on a scribing channel of a wafer, and comprises a transistor which comprises a substrate, a source electrode, a drain electrode and a grid electrode; the electric fuse comprises a first end and a second end; wherein the source electrode is electrically connected to the first bonding pad through a first metal wire, the second end of the electric fuse is electrically connected to the second bonding pad through a second metal wire, the drain electrode, the substrate and the first end of the electric fuse are electrically connected to the third bonding pad through corresponding third metal wires, and the grid electrode is electrically connected to the fourth bonding pad through a fourth metal wire. Voltage is applied to the first bonding pad, the second bonding pad, the third bonding pad and the fourth bonding pad by adopting a preset rule so as to test the resistance of the electric fuse and the performance of the transistor. According to the technical scheme, the resistance of the electric fuse and the performance of the transistor can be simultaneously monitored in the line in the wafer manufacturing process, the process is rapidly adjusted, and the flexibility of the process is improved.

The invention provides a scheduling method, device and equipment of a wafer manufacturing system. The method comprises the following steps: constructing a time Petri net model by adopting a Petri net model according to a wafer processing route and constraint conditions; the constraint condition is the time delay added on the transition or library; an incidence matrix of the time Petri net model is calculated, and the incidence matrix is used for calculation to obtain the number of times of emission; the emission times are emission times corresponding to each transition from the initial identifier to the target identifier under the time Petri network model; operating the time Petri net model by using the launching times in combination with the shortest process time priority strategy, and processing the deadlock problem by adopting multi-step rollback in the operation process of the time Petri net model to obtain a scheduling result of the wafer manufacturing system; wherein the shortest process time priority strategy only reserves a preset number of enabling transitions under each identifier. And the generation efficiency of the scheduling result is improved on the basis of stable operation of the wafer manufacturing system.

The present invention discloses a machine learning-assisted wafer manufacturing process evaluation and anomaly detection method, comprising: constructing a text prompt library based on domain expert knowledge, including morphological descriptions of all possible defects, and obtaining a text feature vector through a CLIP text encoder; extracting customized image features to obtain original image features and new image features; converting the original image features based on a conversion layer fine-tuned by a small number of samples to obtain converted original image features, and using the converted original image features to calculate similarity with text features to obtain a defect map A F ; The new image features and text features are used to calculate the similarity of the redundant features to obtain the defect map A V ; Defect map A F and A V The final defect segmentation map is obtained by adding them together; based on the SEM defect image, the original image features are used to classify the defects, and the classification results are output. The method of the application can effectively reduce background interference and realize efficient and accurate classification and segmentation of nano-scale wafer surface defects.

The invention relates to the technical field of wafer manufacturing, in particular to a wafer sorting and code reading all-in-one machine which has a wafer sorting function and an ID identification code reading function. In the wafer sorting process, the outer edge of the wafer continuously performs circumferential rotation motion due to the friction force from the circumferential plectrum assembly, the orientation of the positioning gap is changed, and the subsequent wafer is skillfully locked by the circumferential limiting assembly by means of the gravity of the wafer, and at the moment, the positioning gap is automatically locked by the circumferential plectrum assembly. According to the technical scheme, the positioning notch is used as the correcting reference, namely, one or more wafers are corrected, the other wafers continue to perform circumferential rotation motion, the positioning notch is also used as the correcting reference until all the wafers are corrected, the whole wafer correcting process is rapid, and good posture consistency is kept between the corrected wafers of the same batch. Furthermore, after the wafers are arranged, station transfer is not needed, and the code reading unit can read and identify the ID identification codes of the wafers in the same batch one by one.

The invention provides a fuzzy knowledge graph construction method related to a wafer manufacturing process, and relates to the technical field of fuzzy knowledge graphs, and the method comprises the steps: employing a three-dimensional convolutional network to extract a spatial defect feature X of a scanning electron microscope image, carrying out the coding of sensor time series data through a bidirectional LSTM, and obtaining a feature set Y, obtaining electrical performance parameters of the wafer based on impedance spectroscopy analysis from the text to obtain a feature set Z; building fuzzy knowledge based on the text to reinforce the feature sets X, Y and Z, building a fuzzy feature set and a time sequence feature set, building a weighted scoring model, and screening a candidate set from the text according to the weighted scoring model; information is extracted from the candidate set, and a tetrad structure G = (entities, relationships, time attributes and fuzzy rules) is constructed; and taking G as input, generating a time sequence fuzzy rule through a recursive reconstruction contribution method, and incrementally updating the knowledge graph. According to the method, the characterization bottleneck of space-time coupling and uncertainty correlation in a traditional method is broken through.

To reduce a loss of a material in a processed material as compared with the case where a second modified layer is formed to between first modified layers arranged in parallel each other in a liner shape when forming a peeling layer.SOLUTION: A manufacturing method of a wafer, comprises: a peeling layer formation step of forming a plurality of peeling layers by alternately repeating a processing feeding that alternately moving a processed material and a focal point of a laser beam along a first direction orthogonal to a thickness direction of the processed material by positioning the focal point of the plus-like laser beam having a wavelength penetrating the processed material to a predetermined depth, and an indexing feeding that relatively moves the processed material and the focal lens along a thickness direction and the second direction orthogonal to the first direction; a clacking progressing step of irradiating a laser beam to a modified layer in at least one peeling layer of a plurality of peeling layers formed in the peeling layer formation step; and a peeling step of peeling a wafer from the processing material by using the plurality of peeling layers as a start point.SELECTED DRAWING: Figure 1

The invention relates to the technical field of wafer processing, in particular to a wafer positioning and clamping concentricity clamping device and method, and the device comprises at least three groups of clamping units. The clamping unit comprises a driving module, a transmission module and a sensing module; the driving module comprises a cylinder and an independent gas circuit for driving the cylinder; the transmission module comprises a multi-connecting-rod mechanism connected with a piston rod of the air cylinder. The movable end of the multi-connecting-rod mechanism is provided with a clamping column used for making contact with the edge of the wafer. The sensing module comprises a position sensor and a thin film pressure sensor. Each clamping unit is provided with an independent electromagnetic valve and an independent gas circuit, closed-loop feedback of a position sensor is introduced, and accurate and synchronous control over the movement tracks of the multiple clamping columns is completed; and a thin film pressure sensor is arranged at a force bearing point of the clamping column, and a self-adaptive force control module of the control system is combined, so that the technical effect that the clamping force is always stabilized in a preset safety range is achieved.

The invention relates to the technical field of PCB and wafer manufacturing, and discloses a multi-stage film residue filtering and collecting device which comprises a first-stage spraying device, a second-stage spraying device, a soaking device and a filtering device, the filtering device can filter impurities in film stripping liquid medicine, the first-stage spraying device and the second-stage spraying device are in linkage, and the soaking device is used for soaking the impurities in the film stripping liquid medicine. Graded spraying can be achieved according to the film stripping requirement of the surface of a PCB or a wafer and the purity of film stripping liquid medicine, the arranged soaking device can conduct soaking and film stripping on the PCB or the wafer, and the arranged first-stage spraying device, the arranged second-stage spraying device, the arranged soaking device and the arranged filtering device are in linkage. The recycling defects of the first-stage spraying device and the second-stage spraying device can be complemented with the recycling defects of the soaking device, so that the film stripping liquid medicine used in a spraying manner can be repeatedly used by the soaking device after impurities are filtered; meanwhile, after impurities in the film stripping liquid used in the soaking mode are filtered, the film stripping liquid can be reused by the device in the spraying mode.

Provided are optical transformer devices having a high power efficiency. The device architecture provides uniform current spreading to minimize efficiency droop. The quantum well designs are optimized for both light-emitting diode (LED) and photo diode (PD) operation. A low-loss optical cavity allows efficient transfer of light from the LED junction to the PD junction. The architecture provides a low-loss voltage up- and down-conversion and provides compatibility with production-grade epitaxial growth and wafer fabrication processes.

The invention relates to a multi-operation-area collaborative pre-scheduling method for a wafer manufacturing system, and the method comprises the following steps: constructing a constrained multi-target mathematical model, taking the minimization of total tardiness and total production cost as a target function, and fully considering the influence of multi-time-window constraints; and designing a double-population evolutionary algorithm, wherein the double-population evolutionary algorithm comprises a normal population responsible for exploring diversity of a solution space and a convergence population of a solution space. In the evolutionary process, the two populations dynamically cooperate with each other. And designing a mixed agent auxiliary model based on the RBF and the SVM. An agent model is updated through an online learning strategy, the prediction precision of the model is improved, and it is ensured that the algorithm can explore more feasible regions; and the multi-operation-area pre-scheduling controller of the wafer manufacturing system receives the new order information, triggers algorithm execution and generates a scheduling scheme. The problem of low scheduling efficiency and solution quality in multi-target pre-scheduling of the wafer manufacturing system is solved, the convergence and uniformity of a population and the number of feasible solutions are enhanced, and the total tardiness and the total production cost are effectively balanced.

The invention relates to the technical field of wafer manufacturing, and discloses a wafer clamp, semiconductor equipment and an electroplating method. The wafer clamp comprises a base, a sealing ring and a pressure head; the base is annular, the sealing ring is installed on the base, the pressing head can cover the base and exert sealed external pressure on the back face of the wafer so that the wafer can abut against the sealing ring, and at the moment, an annular space is formed between the base and the pressing head. The external non-electroplating surface of the wafer limited by the outermost contact boundary defined by the pressing head and the sealing ring after the pressing head and the sealing ring are in contact with the wafer is located in the annular space; the wafer clamp is further provided with an air inlet structure, one end of the air inlet structure is communicated with an air source, the other end of the air inlet structure is communicated with the annular space, and the air inlet structure is used for blow-drying the external non-electroplating surface of the wafer before the wafer is electroplated. Even in an electroplating process with relatively long process time, the wafer clamp can effectively prevent electroplating liquid from entering the wafer clamp, so that the non-electroplating surface outside the wafer is prevented from being corroded; and the clamp and the sealing ring are prevented from being polluted by electroplating liquid.

The invention provides an A * path optimization method for dynamic node reservation under a wafer scheduling system, which comprises the following steps of: selecting a current node from an open table according to a manufacturing requirement, sequentially expanding a new node to the last node for the current node based on a preset A * algorithm, and forming an optimal scheduling path by all nodes according to an expansion sequence; and judging whether the evaluation function value of the expanded new node reaches a dynamic threshold value or not, and if so, storing the evaluation function value into an open table. According to the dynamic evaluation and node reservation method provided by the invention, the evaluation function values of all the nodes in the open table are recorded when each current node is explored, and the dynamic threshold value is set to determine node reservation, so that the heap overflow risk during large-scale scheduling processing is solved, the system stability is ensured, and the system calculation complexity is reduced. The method is more suitable for large-scale wafer manufacturing scheduling, efficient and stable path optimization and resource scheduling can be achieved in a high-complexity environment, and the application effect in an actual production scene is improved.

The embodiment of the invention provides a wafer-level lithium niobate heterogeneous bonding method, which relates to the technical field of silicon optical heterogeneous integration, and comprises the following steps: respectively preparing a silicon optical wafer, a circuit wafer and a lithium niobate wafer; bonding the first SiO2 cladding of the silicon optical wafer with the first side of the lithium niobate film of the lithium niobate wafer; and bonding the second SiO2 cladding of the circuit wafer with the second side of the lithium niobate film of the lithium niobate wafer. According to the scheme, the problems that the wafer is difficult to process and the bonding difficulty is increased due to the fact that an optical / electric functional structure intersects in the wafer manufacturing process are solved, photoelectric separation in the silicon optical-lithium niobate heterogeneous integrated wafer manufacturing process is achieved, and efficient bonding is achieved.

The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer manufacturing sign-off method and system. By constructing an agile sign-off framework combining chip design and production process data and fusing high-level abstract analysis and high-precision process modeling capability, efficient verification, real-time verification and rapid optimization of a manufacturing process are realized, so that manufacturability, performance and quality of a chip are guaranteed, and production yield and sign-off efficiency are improved.

The invention discloses a wafer grinding disc structure detection method and a related device. The method comprises the following steps: applying a constant friction load to the surface of a wafer grinding disc to obtain a micro-area thermal response parameter; fitting to obtain a micro-area thermal diffusion reference parameter; real-time thermal diffusion parameters are recorded in the machining process, deviation values of the real-time thermal diffusion parameters and the reference parameters are calculated, and a thermal response deviation matrix is obtained; analyzing thermal diffusion characteristic differences of adjacent micro-regions, constructing thermal coupling network parameters, and determining thermal islands and thermal barrier regions; cooling liquid flow parameters of the areas are recorded, and cooling efficiency decline indexes are obtained; and through collaborative analysis of thermal field evolution and cooling liquid response, the physical performance degradation degree of the grinding disc surface micro-area is judged. According to the method, the dynamic change of the micro-area temperature field on the surface of the grinding disc can be accurately captured in real time in a high-speed rotating wet environment, the surface performance degradation trend of the grinding disc is recognized in advance through multi-dimensional correlation analysis of a thermal response track, a thermal coupling network and cooling liquid behaviors, and the wafer manufacturing yield and quality consistency are effectively improved.

The invention relates to the technical field of SiC wafer manufacturing, in particular to a platform and method for stripping a SiC wafer after laser implicit cutting of a SiC crystal ingot, and the platform comprises an upper force application fixing part which is used for connecting the to-be-stripped SiC wafer of the SiC crystal ingot; the lower force application fixing part is used for connecting the remaining SiC crystal ingots of the SiC crystal ingots; the shearing force driving part is connected with the upper force application fixing part and the lower force application fixing part, and after the interior of the to-be-stripped SiC wafer is modified by laser, and the interface of the to-be-stripped SiC wafer and the remaining SiC crystal ingot is modified to form a laser scribing modified trace, the shearing force driving part drives the upper force application fixing part and the lower force application fixing part to move in a staggered manner, so that the to-be-stripped SiC wafer is stripped. And the to-be-stripped SiC wafer and the residual SiC crystal ingot are staggered and separated. The platform and the method for stripping the SiC wafer after the laser implicit cutting of the SiC crystal ingot have the advantages of high efficiency, high precision, low cost and the like.

The invention belongs to the field of wafer manufacturing, and discloses a knowledge reasoning method and device for an integrated circuit wafer process and a medium, and the method comprises the steps: carrying out the extraction of multi-modal features of a wafer image; performing wafer knowledge retrieval; sorting the documents; and generating a query answer. Dynamic decomposition and high-precision solution of complex query are realized step by step through three core stages. An introduced multi-modal chain reasoning framework enables the model to combine logical reasoning and multi-modal information, and a coherent solution chain is constructed to cope with complex tasks.

In examples, a method for manufacturing a semiconductor die comprises, prior to forming circuitry on a semiconductor wafer, forming a horizontal array of cracks in an interior of the wafer using a laser. The method also includes, after forming the horizontal array of cracks, forming circuitry on a device side of the wafer. The method includes forming conductive bumps on the device side of the wafer.

The present invention provides a reactive collaborative scheduling optimization method and system for material distribution in multiple work areas of a wafer manufacturing system based on predictive self-collaborative reinforcement learning, comprising the following steps: constructing a total return prediction model for collaborative scheduling of material distribution in multiple work areas based on a deep neural network and training it; defining and designing a collaborative scheduling environment for material distribution in multiple work areas; constructing an intelligent agent for scheduling work areas; interacting with multiple agents and the collaborative scheduling environment for material distribution in multiple work areas to form and collect historical experience data for training multiple agents to learn optimal decision strategies and maximize total returns; integrating the intelligent agent model for scheduling wafer multi-work areas into the collaborative scheduling system for material distribution in multiple work areas of a wafer manufacturing system. The present invention realizes the collaborative scheduling optimization of material distribution in multiple work areas of a wafer manufacturing system through a predictive self-collaborative reinforcement learning method, which can effectively improve the collaborative scheduling performance of intelligent agents, and greatly reduces the production cycle of a wafer manufacturing system and reduces the number of times a wafer lot violates the residence time constraint of an work area through real-time collaborative scheduling of multiple work areas.

The purpose of the present invention is to provide an optical resin wafer manufacturing method which can obtain an optical resin wafer having an improved flatness property. An optical resin wafer having an improved flatness property can be obtained by said optical resin wafer manufacturing method comprising: a mold preparation step for preparing a mold that satisfies the following (a) or (b); and a curing step for obtaining an optical resin wafer precursor by casting and curing a curable composition serving as a raw material for the wafer in the mold.　(a) The mold has one or more spacers in the center of a cavity space.　(b) The relationship between the thickness tm0 at the center of the cavity space of the mold and the thickness tm1 at a position 5 mm from the outer circumference toward the center of the cavity space of the mold satisfies tm0>tm1.

The invention discloses a wafer cutting method, and relates to the technical field of wafer manufacturing, and the method comprises the steps: fixing a wafer, cutting a first layer of the wafer through a first cutter, forming a first cutting groove in the surface of the first layer, and enabling the depth of the first cutting groove to be smaller than the thickness of the first layer; the wafer is turned over, a second cutter is used for cutting a second layer of the wafer, a second cutting groove is formed in the surface of the second layer, the depth of the second cutting groove is smaller than the thickness of the second layer, and the projection of the first cutting groove and the projection of the second cutting groove on the surface of the wafer at least partially coincide; and sequentially cutting through the second layer and the first layer along the second cutting groove by using a third cutter. According to the invention, the first layer and the second layer are not cut through at the same time, the partial structures of the first layer and the second layer are reserved, and the wafer is cut through the third time of cutting. Therefore, when the wafer is cut in the prior art, the problems of damage and edge breakage are reduced, and the cutting quality and the processing precision of a subsequent module are improved.

This invention relates to a method for remote epitaxial growth of single-crystal lead-free perovskite microsheets on germanium, comprising the following steps: using CsBr and SnBr2 as source materials placed in a reaction region, using argon as a carrier gas, placing germanium-based graphene in a deposition region, and then heating to react the source materials, followed by evaporation and deposition onto the germanium-based graphene to form single-crystal lead-free perovskite microsheets. The method of this invention can obtain perovskite microsheets with good orientation and is environmentally friendly. Furthermore, germanium is a mature semiconductor material with well-established wafer fabrication, cleaning, and surface treatment processes, making large-scale production possible and providing a new path for perovskite to move from the laboratory to high-performance, multifunctional integrated optoelectronic devices.