256 results about "Wafer fabrication" patented technology

The invention provides a wafer-level test yield prediction and process optimization method and system based on big data, and relates to the technical field of wafer-level tests.The wafer-level test yield prediction and process optimization method comprises the steps that wafer manufacturing process data is obtained, a time-sequence-sensitive multi-modal data fusion network is constructed, a LSTM and GNN combined mixed architecture is adopted, and a multi-modal data fusion network is constructed; self-adaptive weight distribution is carried out through an attention mechanism to predict the yield; and when the predicted yield is lower than a threshold value, triggering a layered progressive process optimization system, and adjusting process parameters through an equipment parameter optimization layer and a process level optimization layer. According to the invention, the accurate prediction of the wafer test yield and the automatic optimization of the process parameters are realized, the production efficiency is improved, and the manufacturing cost is reduced.

The invention discloses an automatic identification method and system for a wafer internal defect image of a 3D stacked chip, and belongs to the technical field of semiconductor manufacturing and detection. According to the method, optical, X-ray and ultrasonic image data are synchronously acquired based on a multi-modal imaging technology, imaging parameters are dynamically adjusted to adapt to different wafer levels and material characteristics, multi-modal features are extracted in combination with layered filtering and denoising, multi-resolution registration and a self-supervised deep learning method, and micron-sized defects are positioned by using an attention mechanism. And further constructing a defect-process parameter correlation model through reinforcement learning, generating a closed-loop process optimization instruction, and transmitting the closed-loop process optimization instruction to an execution system. The system comprises a multi-modal imaging module, a noise suppression module, a deep learning analysis module and a process optimization module, and supports edge computing deployment. According to the invention, the internal defect detection efficiency and precision of the multi-layer stacked chip are significantly improved, real-time closed-loop control of detection-analysis is realized, the wafer manufacturing quality risk is reduced, and the method is suitable for intelligent defect detection of an advanced packaging production line.

The invention provides a fuzzy knowledge graph construction method related to a wafer manufacturing process, and relates to the technical field of fuzzy knowledge graphs, and the method comprises the steps: employing a three-dimensional convolutional network to extract a spatial defect feature X of a scanning electron microscope image, carrying out the coding of sensor time series data through a bidirectional LSTM, and obtaining a feature set Y, obtaining electrical performance parameters of the wafer based on impedance spectroscopy analysis from the text to obtain a feature set Z; building fuzzy knowledge based on the text to reinforce the feature sets X, Y and Z, building a fuzzy feature set and a time sequence feature set, building a weighted scoring model, and screening a candidate set from the text according to the weighted scoring model; information is extracted from the candidate set, and a tetrad structure G = (entities, relationships, time attributes and fuzzy rules) is constructed; and taking G as input, generating a time sequence fuzzy rule through a recursive reconstruction contribution method, and incrementally updating the knowledge graph. According to the method, the characterization bottleneck of space-time coupling and uncertainty correlation in a traditional method is broken through.

The invention relates to the technical field of wafer processing, in particular to a wafer positioning and clamping concentricity clamping device and method, and the device comprises at least three groups of clamping units. The clamping unit comprises a driving module, a transmission module and a sensing module; the driving module comprises a cylinder and an independent gas circuit for driving the cylinder; the transmission module comprises a multi-connecting-rod mechanism connected with a piston rod of the air cylinder. The movable end of the multi-connecting-rod mechanism is provided with a clamping column used for making contact with the edge of the wafer. The sensing module comprises a position sensor and a thin film pressure sensor. Each clamping unit is provided with an independent electromagnetic valve and an independent gas circuit, closed-loop feedback of a position sensor is introduced, and accurate and synchronous control over the movement tracks of the multiple clamping columns is completed; and a thin film pressure sensor is arranged at a force bearing point of the clamping column, and a self-adaptive force control module of the control system is combined, so that the technical effect that the clamping force is always stabilized in a preset safety range is achieved.

The invention relates to a multi-operation-area collaborative pre-scheduling method for a wafer manufacturing system, and the method comprises the following steps: constructing a constrained multi-target mathematical model, taking the minimization of total tardiness and total production cost as a target function, and fully considering the influence of multi-time-window constraints; and designing a double-population evolutionary algorithm, wherein the double-population evolutionary algorithm comprises a normal population responsible for exploring diversity of a solution space and a convergence population of a solution space. In the evolutionary process, the two populations dynamically cooperate with each other. And designing a mixed agent auxiliary model based on the RBF and the SVM. An agent model is updated through an online learning strategy, the prediction precision of the model is improved, and it is ensured that the algorithm can explore more feasible regions; and the multi-operation-area pre-scheduling controller of the wafer manufacturing system receives the new order information, triggers algorithm execution and generates a scheduling scheme. The problem of low scheduling efficiency and solution quality in multi-target pre-scheduling of the wafer manufacturing system is solved, the convergence and uniformity of a population and the number of feasible solutions are enhanced, and the total tardiness and the total production cost are effectively balanced.

The invention relates to the technical field of wafer manufacturing, and discloses a wafer clamp, semiconductor equipment and an electroplating method. The wafer clamp comprises a base, a sealing ring and a pressure head; the base is annular, the sealing ring is installed on the base, the pressing head can cover the base and exert sealed external pressure on the back face of the wafer so that the wafer can abut against the sealing ring, and at the moment, an annular space is formed between the base and the pressing head. The external non-electroplating surface of the wafer limited by the outermost contact boundary defined by the pressing head and the sealing ring after the pressing head and the sealing ring are in contact with the wafer is located in the annular space; the wafer clamp is further provided with an air inlet structure, one end of the air inlet structure is communicated with an air source, the other end of the air inlet structure is communicated with the annular space, and the air inlet structure is used for blow-drying the external non-electroplating surface of the wafer before the wafer is electroplated. Even in an electroplating process with relatively long process time, the wafer clamp can effectively prevent electroplating liquid from entering the wafer clamp, so that the non-electroplating surface outside the wafer is prevented from being corroded; and the clamp and the sealing ring are prevented from being polluted by electroplating liquid.

The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer manufacturing sign-off method and system. By constructing an agile sign-off framework combining chip design and production process data and fusing high-level abstract analysis and high-precision process modeling capability, efficient verification, real-time verification and rapid optimization of a manufacturing process are realized, so that manufacturability, performance and quality of a chip are guaranteed, and production yield and sign-off efficiency are improved.

The invention discloses a wafer grinding disc structure detection method and a related device. The method comprises the following steps: applying a constant friction load to the surface of a wafer grinding disc to obtain a micro-area thermal response parameter; fitting to obtain a micro-area thermal diffusion reference parameter; real-time thermal diffusion parameters are recorded in the machining process, deviation values of the real-time thermal diffusion parameters and the reference parameters are calculated, and a thermal response deviation matrix is obtained; analyzing thermal diffusion characteristic differences of adjacent micro-regions, constructing thermal coupling network parameters, and determining thermal islands and thermal barrier regions; cooling liquid flow parameters of the areas are recorded, and cooling efficiency decline indexes are obtained; and through collaborative analysis of thermal field evolution and cooling liquid response, the physical performance degradation degree of the grinding disc surface micro-area is judged. According to the method, the dynamic change of the micro-area temperature field on the surface of the grinding disc can be accurately captured in real time in a high-speed rotating wet environment, the surface performance degradation trend of the grinding disc is recognized in advance through multi-dimensional correlation analysis of a thermal response track, a thermal coupling network and cooling liquid behaviors, and the wafer manufacturing yield and quality consistency are effectively improved.

The invention belongs to the field of wafer manufacturing, and discloses a knowledge reasoning method and device for an integrated circuit wafer process and a medium, and the method comprises the steps: carrying out the extraction of multi-modal features of a wafer image; performing wafer knowledge retrieval; sorting the documents; and generating a query answer. Dynamic decomposition and high-precision solution of complex query are realized step by step through three core stages. An introduced multi-modal chain reasoning framework enables the model to combine logical reasoning and multi-modal information, and a coherent solution chain is constructed to cope with complex tasks.

This invention relates to a method for remote epitaxial growth of single-crystal lead-free perovskite microsheets on germanium, comprising the following steps: using CsBr and SnBr2 as source materials placed in a reaction region, using argon as a carrier gas, placing germanium-based graphene in a deposition region, and then heating to react the source materials, followed by evaporation and deposition onto the germanium-based graphene to form single-crystal lead-free perovskite microsheets. The method of this invention can obtain perovskite microsheets with good orientation and is environmentally friendly. Furthermore, germanium is a mature semiconductor material with well-established wafer fabrication, cleaning, and surface treatment processes, making large-scale production possible and providing a new path for perovskite to move from the laboratory to high-performance, multifunctional integrated optoelectronic devices.

This application relates to a method and product for preparing indium antimonide heterostructures that can reduce annealing thermal stress, belonging to the field of indium antimonide heterostructure manufacturing technology. The method includes: providing a donor indium antimonide substrate; forming an ion implantation layer, a weakening layer, and a residual substrate layer by ion implantation; providing a carrier indium antimonide substrate; depositing an Al2O3 passivation layer on the surfaces of the carrier indium antimonide substrate and the donor indium antimonide substrate; further depositing a SiO2 layer on the carrier indium antimonide substrate; bonding the SiO2 layer on the carrier indium antimonide substrate to the Al2O3 passivation layer on the donor indium antimonide substrate; annealing at a low temperature of ≤200℃ for 10~20h; peeling off the donor indium antimonide substrate; providing a SiC / Si substrate; bonding the peeled surface of the ion implantation layer to the SiC / Si substrate; and wet etching using BOE / DHF etching solution to obtain the heterostructure wafer.

The invention discloses a display device hard mask planarization method, which comprises the following steps of: 1, sequentially depositing an anode, an ITO (Indium Tin Oxide) layer and a hard mask layer on a substrate by using a CMOS (Complementary Metal Oxide Semiconductor) Wafer as the substrate; 2, yellow light gluing, exposure and development are carried out, a PR mask is left, PR removal is carried out after etching, then a film layer on the bottom layer of a PR covering area is left, and film layer protrusions caused by tungsten holes appear; 3, yellow light gluing, exposure and development are carried out, a concave PR mask structure is formed, a convex mask part is subjected to etching treatment, and a convex part is leveled; and if the PR mask still remains, processing the PR mask to remove the redundant PR. The display device hard mask planarization method is reasonable in design, pixel Hard Mask film planarization is achieved mainly through yellow light and the etching technology, equipment and cost input can be reduced, and the wafer manufacturing efficiency is improved by 20%; and the quality of the display device can be ensured.

A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

A wire electrical discharge machining (EDM) device comprises the following: a pair of wire parallel guide rollers arranged on both sides of a workpiece to hold the workpiece between them, each of these rollers having a plurality of wire guide grooves formed at equal intervals on an outer circumferential surface, the plurality of wire guide grooves causing a plurality of running cutting wire sections to fit into them and constraining the movement of the plurality of cutting wire sections; parallel wire extension position measuring units (52a, 52b) which measure a distance between a measuring reference surface set parallel to a virtual plane containing the plurality of cutting wire sections and a wire electrode forming the plurality of cutting wire sections;a wire guide groove detachment detection unit (53) that detects the occurrence of a change in distance based on a measurement result obtained from the parallel wire extension position measuring units (52a, 52b); and a wire condition determination unit (54) that determines, based on the detection result obtained from the wire guide groove detachment detection unit (53), whether it is a wire detachment condition in which at least one of the cutting wire sections has detached from the wire guide groove, or a wire contact condition in which all cutting wire sections are in contact with the wire guide grooves.

This invention relates to the field of wafer fabrication technology, and proposes a robotic arm and wafer cleaning process for testing various types of wafer products. The robotic arm includes side grippers, a middle gripper, a first power component, and a second power component. Two side grippers are provided, each with both elastic and rigid gripping portions. The middle gripper is positioned between the two side grippers and also has a rigid gripping portion. The first power component adjusts the Y-axis distance between the two side grippers and simultaneously adjusts the X-axis distance between the side grippers and the middle gripper. The second power component drives the side grippers to rotate about the Z-axis. By incorporating a first power component, this invention allows adjustment of the distance between the two side grippers, thus accommodating the gripping of wafers of different sizes and specifications, and enabling the removal of wafers from stacking containers, making it highly convenient to use. Furthermore, it facilitates adjustment of the gripping direction of the side grippers, further improving the ease of application.

The invention discloses a polishing method and system for controlling LTV at a marking hole of a SiC wafer, and relates to the technical field of semiconductor manufacturing. A polishing solution is adopted to carry out chemical mechanical polishing on the SiC wafer with the laser marking hole under the polishing process parameters; the polishing solution comprises a KMnO4 oxidizing agent with the mass fraction of 10% + / -3% and a mixed grinding material of Al2O3 and CeO2, the particle size of the Al2O3 grinding material is 250-350 nm, the particle size of the CeO2 grinding material is 80-120 nm, the mass ratio of Al2O3 to CeO2 is 1: 1, the mass fraction of Al2O3 and CeO2 in the polishing solution is 5%-6%, and the polishing solution is maintained to be acidic. The material removal rate of the marking hole area and the material removal rate of the wafer body area are highly consistent, the SiC wafer surface with the ultrahigh flatness is obtained, local thickness changes, caused by laser marking, around the marking hole are restrained, and the overall quality and yield of SiC wafer manufacturing are improved.

Semiconductor (SC) chip devices and associated methods of making are presented. The SC chips are designed to include enlarged extension semiconductor areas next to functional integrated circuit (IC) dies on these SC chips. Some variations include designing semiconductor wafers prior to fabrication so that the resultant IC dies are surrounded by the extension semiconductor areas. Other variations include processing post manufactured semiconductor wafers to expand the size of the available extension areas by including truncated pieces of IC dies that are immediately adjacent to functional working primary IC dies. These variations provide additional room for redistribution layers to fan-out from the IC dies outwards onto the extension areas.

A method for modeling a wafer profile by a function is provided, in which the function is used to calculate a displacement z in a thickness direction of a wafer and is a sum of multiple functions including a first function g(r), a second function Ar×h(Nθ), and a third function Br×i(M(θ-φ)). The first function g(r) indicates a first-order or higher-order polynomial with a distance r from the center of the wafer as a variable. The second function Ar×h(Nθ) indicates multiplying a sine or cosine function h(Nθ) by a first angle θ with respect to a predetermined position in a circumferential direction of the wafer as a variable and an integer N as a constant with a coefficient A and the distance r.The third function Br×i(M(θ-φ)) indicates multiplying a sine or cosine function i(M(θ-φ)) with the first angle θ as a variable, a second angle φ with respect to the predetermined position as a constant, and an integer M as a constant with a coefficient B and the distance r.

The invention relates to the technical field of wafer manufacturing, and discloses a high-pressure wafer bonding system in order to solve the technical problems that a temporary bonding adhesive layer is poor in uniformity extension and large in bonding thickness deviation, and the system comprises a bonding lower platform assembly which is used for bearing a wafer to be bonded; the bonding upper platform assembly is arranged above the bonding lower platform assembly, is arranged opposite to the bonding lower platform assembly and is used for applying bonding pressure; the vacuum system is arranged below the bonding lower platform assembly and used for providing a vacuum environment for a bonding cavity between the upper platform and the lower platform in the bonding process; wherein the bonding upper platform assembly realizes movement in the Z-axis direction through a lifting mechanism, and can apply bonding lower pressure not less than 50kN so as to realize high-uniformity bonding between a wafer and a carrier wafer. The upper bonding platform and the lower bonding platform are controlled by using the high-pressure bonding system, and the wafer and the carrier wafer are bonded together through the bonding layer in a downward flat pressing manner, so that the subsequent de-bonding process is simplified, and the wafer manufacturing cost is reduced.

The present invention is a temporary adhesive for wafer processing, which is used for temporarily bonding a wafer to a support. This temporary adhesive for wafer processing is composed of a curable silicone resin composition which can be cured by a hydrosilylation reaction. This curable silicone resin composition is a temporary adhesive for wafer processing, which characteristically contains an organopolysiloxane that has in each molecule only one alkenyl group or only one silicon atom-bonded hydrogen atom (SiH group). It is thereby possible to provide a temporary adhesive for wafer processing, a wafer laminate, and a method for producing thin wafers using same, which support an improved productivity for thin wafers, wherein, inter alia, an adequate substrate retention is exhibited post-bonding even when a substrate with high level differences is used; a high process compatibility is exhibited with wafer backside grinding processes, TSV formation processes, and wafer backside wiring processes; facile peeling is exhibited in peeling processes even after passage post-bonding through a lengthy high-temperature heating process in air; and the residue on the substrate post-peeling exhibits an excellent cleanability.

A surface treatment composition of the present invention is a surface treatment composition that are supplied as a vapor to a surface of a wafer having an uneven pattern on the surface and used to form a water-repellent protective film on the surface, the surface treatment composition containing a silylating agent and a solvent, in which the silylating agent contains a trialkylsilylamine, the solvent contains at least one or more selected from the group consisting of glycol ether acetate and glycol acetate, and a total content of the glycol ether acetate and the glycol acetate is 50% by mass or more in 100% by mass of a total amount of the solvent.

The invention relates to the field of wafer manufacturing, in particular to wafer adsorption equipment. The wafer suction device is used for sucking a wafer below a rotating tower and rotating the wafer to a next station, and is characterized by comprising the rotating tower, the rotating tower is provided with a rotating axis which is horizontally arranged, and a plurality of suction nozzles are installed around the rotating axis; an adsorption mechanism is arranged corresponding to any suction nozzle and comprises an adsorption hole formed in the end part of any suction nozzle, and an air ring and an air shaft which are communicated with the adsorption hole and are coaxial with the rotating axis; the multiple gas rings are arranged corresponding to the suction nozzles, the multiple gas rings are arranged on the outer wall of the gas shaft in a sleeving mode in the axial direction and can rotate relative to the gas shaft, the outer wall of any gas ring is provided with a first adsorption connector in the radial direction and used for being connected with external vacuum equipment, and the inner wall of each gas ring is provided with a gas groove of an annular structure communicated with the first adsorption connector; the suction nozzle is installed at one end of the air shaft, an air channel is formed in the air shaft, and the two ends of the air channel communicate with the air groove and the adsorption hole correspondingly. Any first adsorption connector is correspondingly communicated with the only air groove, the only air channel and the only adsorption hole.

The present invention discloses a metalens wafer, a metalens wafer manufacturing process, and a manufacturing device thereof, which are used in the field of optical imaging equipment technology. The metalens wafer of the present invention includes a carrier substrate and a metalens wafer connected and fixed to the carrier substrate. The manufacturing process of the present invention includes the following steps: using reactive ions to etch preset exposed positions of the metalens wafer to form grooves in a target oxide layer of the metalens wafer, wherein the grooves penetrate the target oxide layer along a preset direction; cutting along the grooves toward the carrier substrate until the carrier substrate is cut through. Since the target oxide layer is divided by etching, the problems of edge collapse and in-plane cracks caused by mechanical cutting of the target oxide layer can be effectively avoided, thereby effectively improving the product yield of the metalens wafer.

The invention relates to a solid-state battery production device, a solid-state battery production method and solid-state battery preparation equipment. The solid-state battery piece making device comprises a composite mechanism which comprises a pole piece unwinding assembly, a rubber frame unwinding assembly and a material belt composite assembly, and the pole piece unwinding assembly and the rubber frame unwinding assembly are both arranged on the upstream of the material belt composite assembly; and the flaking mechanism comprises a tab cutting assembly and a cutting assembly, the tab cutting assembly is arranged at the downstream of the material belt compounding assembly, and the cutting assembly is arranged at the downstream of the tab cutting assembly. Therefore, the material belt compounding assembly is used for compounding the pole piece material belt and the rubber frame material belt, then the pole lug cutting assembly is used for cutting the composite material belt to form the pole lug, and the cutting assembly is used for cutting off the composite material belt to form the pole piece material, so that the situation that the pole piece, the solid electrolyte layer and the rubber frame are independently cut and flaked is avoided, and the flaking efficiency is improved; and therefore, the production efficiency of the whole machine is improved, and the capacity requirement is better met.

The invention discloses a permanent magnet water pump system for wafer manufacturing temperature control equipment and a control method, and belongs to the technical field of semiconductor manufacturing. The system comprises a permanent magnet synchronous motor, a magnetic coupler, an impeller, a pump cavity and a controller. The magnetic coupler achieves non-contact torque transmission through the driving half shaft, the driven half shaft and the isolation sleeve, heat conduction is isolated, and motor parameters are prevented from being affected by temperature. The controller estimates magnetic coupling angle deviation by utilizing a nonlinear elastic angle-torque relation based on a position-sensorless algorithm, realizes high-precision rotor angle estimation in combination with current information, and has intelligent protection functions of slipping, locking, idling and the like. The problems that a traditional alternating current asynchronous motor is narrow in speed regulation range and poor in low-speed load and a permanent magnet motor parameter temperature excursion are solved, and the alternating current asynchronous motor has the advantages of being wide in speed range, high in precision, high in reliability, high in adaptability and the like and is suitable for high-cleanliness and high-precision temperature control scenes in wafer manufacturing.

The present invention provides a wafer manufacturing method that reliably forms a separation layer capable of discharging gas generated inside the workpiece in the outer peripheral region of the workpiece, while reducing the power of the laser beam irradiated during the formation of the separation layer. [Solution] A wafer manufacturing method comprises a holding step S1 of holding an ingot 11; a first separation layer formation step S2 of forming a separation layer 15 in the outer peripheral region of the ingot 11 by irradiating the outer peripheral region of the ingot 11 with a laser beam; a second separation layer formation step S3 of forming a separation layer 15 in the inner region of the ingot 11 by irradiating the inner region of the ingot 11 with a laser beam; and a separation step S4 of separating the wafer W from the ingot 11. The first separation layer formation step S2 includes an inner processing step S21 of forming a separation layer 15 at an inner position in the outer peripheral region, and an outer processing step S22 of forming a separation layer 15 at a position outside the inner position.

A processing apparatus includes a chuck table configured to hold a wafer and rotate on a chuck shaft; a processing mechanism to rotate a spindle, to which an annular processing tool is attached, and process the wafer with a lower surface of the processing tool; a process-feeding mechanism to lift or lower the processing mechanism; at least three load sensors arranged at equal intervals along a circle centered on a rotation axis of the spindle or the chuck table and configured to measure a force pressing the processing tool against the wafer; and a controller to control pressing of the processing tool against the wafer such that a sum of values from the load sensors corresponds to a set load and control a rotation speed of the spindle or the chuck shaft such that a ratio of the values from the load sensors is maintained at a set ratio.

The application provides a wafer three-dimensional model circuit connectivity test method, device, medium and program product. The wafer three-dimensional model includes a plurality of structure units. The method includes: establishing a material attribute mapping table to record conductive attribute information; identifying the constituent material of each structure unit based on the material attribute mapping table and adding a label reflecting the conductive attribute; setting at least two virtual probes to establish a contact relationship with different structure units of the wafer three-dimensional model; selecting one of the virtual probes as a starting probe, taking the structure unit where the starting probe is located as a starting point, acquiring a test result of the connectivity state between the virtual probes according to the conductive path propagation, and comparing the test result with a design expectation to determine whether the wafer three-dimensional model meets the circuit connectivity requirement. Through the establishment of the material conductive attribute mapping, the virtual probe layout and the connectivity judgment mechanism, the wafer three-dimensional model circuit connectivity can be accurately detected before wafer manufacturing.

The invention discloses a vacuum pump for semiconductor manufacturing, and relates to the technical field of semiconductor manufacturing, and the vacuum pump comprises a water tank, the top end of the water tank is provided with a driving motor, one end of the water tank close to the driving motor is provided with an exhaust pipe, the output end of the driving motor is in transmission connection with a pump body, the top end of the pump body is connected with a connecting pipe, and one end of the pump body is connected with an air inlet; according to the air pipe, external heating air is added along the air pipe body, so that the external heating air can circularly flow in the air circulating pipe, heating is achieved after electrification through the heating wire in the sleeving ring, drying and heating of the air inlet are achieved, and the air inlet is heated through the heating wire in the sleeving ring. According to the vacuum pump for semiconductor manufacturing, solid dust is prevented from entering the pump body to cause blockage and influence on normal use, dust accumulation in the pump body is prevented from occurring easily, and rapid treatment of the vacuum pump for semiconductor manufacturing on various vacuum process chamber gases in the whole process of wafer manufacturing, chip packaging testing and the like can be improved.

The application discloses a kind of surface self-cleaning spray disc automation spraying device, the present application relates to the technical field of injection device, the spraying device includes box, general control module, heating module, handling mechanical arm, coating mechanism, rotating mechanism and chuck, cabinet door and rotating hole are equipped on the box, coating mechanism includes three-axis displacement module and cleaning mechanism, rotating mechanism includes bottom column and driving motor, cabinet door is equipped with two groups, general control module, heating module, handling mechanical arm, three-axis displacement module, base, driving motor are all fixedly connected with the box, chuck is fixedly connected with handling mechanical arm, bottom column is rotatably connected with rotating hole, heating module, handling mechanical arm, coating mechanism, driving motor are all connected with general control module by electric signal;The application automatically coats glue and develops wafer, and millisecond level is covered by developing solution, avoids line width deviation and large droplet impact wafer to destroy pattern, avoids developing spot and comet tail defect, improves wafer manufacturing precision.