Wafer manufacturing sign-off method and system

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer manufacturing sign-off method and system. By constructing an agile sign-off framework combining chip design and production process data and fusing high-level abstract analysis and high-precision process modeling capability, efficient verification, real-time verification and rapid optimization of a manufacturing process are realized, so that manufacturability, performance and quality of a chip are guaranteed, and production yield and sign-off efficiency are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a wafer manufacturing signature method and system. BACKGROUND

[0002] In the field of semiconductor chip manufacturing, the traditional chip manufacturing process generally adopts the mode of "design-manufacturing separation". In the chip design stage, engineers mainly perform circuit architecture design, layout, etc. according to functional requirements and performance indicators; and the manufacturing link is executed by the foundry according to the preset process parameters to perform wafer processing, lithography, etching, etc. This mode has promoted the large-scale development of the semiconductor industry in the past few decades.

[0003] From the specific technical means, the existing design process relies on electronic design automation (EDA) tools to complete circuit simulation and layout verification, but these tools are often based on idealized process parameter models for analysis, lacking real-time interaction with complex process changes in actual manufacturing processes; the manufacturing link mainly collects production data such as lithography exposure dose, etching rate, etc. through the process monitoring system, but these data cannot be effectively fed back to the design end. This separation architecture leads to "information islands" of design and manufacturing data, making it difficult to achieve cross-link optimization.

[0004] The core defect of the prior art is the data separation between the design and manufacturing links, which directly leads to a series of technical problems: in terms of yield loss, the design stage fails to fully consider the impact of actual process fluctuations such as lithography offset, etching non-uniformity, etc. on chip performance, resulting in a narrow process window during mass production, producing a large number of unqualified products. According to industry statistics, the yield loss caused by design-manufacturing mismatch in advanced processes can reach 15%-20%; cost escalation follows, repeated design iteration and manufacturing process adjustment significantly increase research and development costs and time costs, for example, the single flow cost of a 7nm chip exceeds one million dollars, and repeated flow caused by design defects will significantly prolong the product launch cycle; performance bottlenecks are also prominent, static design verification methods cannot adapt to the dynamic changes of process parameters in advanced processes, resulting in a significant difference between actual chip performance and design target, making it difficult to meet the needs of high-performance application scenarios such as 5G and artificial intelligence. To trace the root cause, these problems are due to the lack of data-driven closed-loop feedback mechanism in the traditional design-manufacturing process, which fails to integrate real-time process data from the manufacturing end back into the design optimization process.

[0005] In the semiconductor chip manufacturing process, with the increasing complexity of chip design and the continuous shrinking of process nodes, it is a great challenge to ensure the manufacturability, performance and quality of the chip. In the traditional chip manufacturing process, there is a certain degree of disconnection between the design and manufacturing links, which leads to the problem that the chip performance is not as expected and the yield is low in the actual production process due to the failure to fully consider the influence of production process parameters and other factors on the chip yield, which not only increases the production cost, but also prolongs the product's listing cycle. Therefore, it is urgent to develop a technology that can effectively integrate chip design and production process parameters and other data, comprehensively analyze, verify and optimize the chip manufacturing process, so as to improve the manufacturability, performance and quality of the chip and improve the yield in the production process. SUMMARY

[0006] The present application aims at the problem that the existing signing process is subject to the traditional static process angle model, only relies on simulation verification, cannot cope with the dynamic drift of process parameters, and due to the lack of structured processing and design data association mechanism, the signing link is difficult to realize accurate optimization, and proposes a wafer manufacturing signing method and system; by constructing an agile signing framework combining chip design and production process data, integrating high-level abstract analysis and high-precision process modeling capability, efficient verification, real-time checking and rapid optimization of the manufacturing process are realized, so as to ensure the manufacturability, performance and quality of the chip and improve the production yield and signing efficiency.

[0007] The specific implementation content of the present application is as follows: A wafer manufacturing signing method, specifically comprising the following steps: Step S1: integrate the collected chip design data and production process parameters, and store the integrated chip design data and production process parameters according to the constructed multi-level cache mechanism; Step S2: according to the integrated chip design data and production process parameters, deploy a special hardware monitor and configure a data checker, compare the design target parameters with the actual production data in real time, and generate a debugging report according to the captured snapshot data; Step S3: according to the generated debugging report, call a gradient descent local optimization algorithm for optimization, and feed back the optimization result to the design and manufacturing system.

[0008] In order to better realize the present application, further, the step S1 specifically comprises the following steps: Step S11: call a standardized data packaging template to obtain a hardware-data interface template, collect chip design data and production process parameters, and integrate them; Step S12: according to the unified hardware-data interface template, a first-level cache mechanism is constructed, a second-level cache mechanism of unit-level test data and production-level verification excitation is constructed, a third-level cache mechanism is constructed by calling a wafer manufacturing simulation platform, and the integrated chip design data and production process parameters are stored.

[0009] To better implement the present application, further, the step S11 specifically includes the following steps: Step S111: according to the standardized data packaging template, a hardware-data interface template is obtained, and a standardized mapping rule is called to connect the chip design data and the production process parameters; Step S112: an automatic test data conversion tool flow is called to convert the unit-level test data at the design end into production-level verification excitation, and test vectors covering key process nodes are generated; Step S113: a heterogeneous data mapping platform is called, based on a wafer manufacturing simulation platform, to map the chip design model, the process physical model and the corresponding C / C++ simulation model to the same verification environment, to synchronously run the design reference model and the process simulation model, and to realize real-time correlation analysis of cross-level data.

[0010] To better implement the present application, further, the step S12 specifically includes the following steps: Step S121: a first-level cache mechanism based on the unified hardware-data interface template is constructed, a standardized data packaging cache layer is constructed, and the standardized mapping rule of the chip design data and the production process parameters is pre-stored; Step S122: a second-level cache mechanism of unit-level test data and production-level verification excitation is established, an automatic test data conversion cache layer is established, and a development tool flow is called to generate key process node test vectors and cache them; Step S123: a third-level cache mechanism is constructed by calling a wafer manufacturing simulation platform, and the mapping relationship of the chip design model, the process physical model and the C / C++ simulation model is stored in the cache.

[0011] To better implement the present application, further, the step S2 specifically includes the following steps: Step S21: a special hardware monitor is deployed and a data checker is configured, real-time comparison between the design target parameters and the actual production data is performed, and according to the constructed dynamic threshold model, parameter deviation caused by process offset is automatically identified and an abnormal alarm is triggered; Step S22: if the design target parameters and the actual production data are inconsistent, a snapshot problem capture is started, a hardware state snapshot of a key process node is captured, and the corresponding design parameter configuration is recorded; Step S23: importing the captured snapshot data into an external simulator, constructing a manufacturing process simulation environment under abnormal conditions, accurately locating the problem source through time sequence backtracking analysis, and generating a debugging report containing integrated design modification suggestions and process adjustment schemes.

[0012] To better implement the present application, further, the step S21 specifically comprises the following steps: Step S211: deploying a dedicated hardware monitor to collect actual production data in real time and obtain design target parameters; Step S212: constructing a dynamic threshold model according to the obtained historical production data and process specifications; Step S213: calculating a deviation value according to the collected actual production data and design target parameters; Step S214: judging whether an abnormality occurs according to the deviation value and the dynamic threshold model, and triggering an abnormality alarm if yes.

[0013] To better implement the present application, further, the step S22 specifically comprises the following steps: Step S221: calculating a yield deviation according to the yield prediction value and the yield measured value obtained through real-time monitoring; Step S222: triggering a capture mechanism if the yield deviation is greater than a set yield deviation threshold; Step S223: obtaining hardware state snapshot data of a key process node according to the triggered capture mechanism, and recording corresponding design parameter configurations.

[0014] To better implement the present application, further, the step S23 specifically comprises the following steps: Step S231: importing the hardware state snapshot data and the design parameter configurations into an external simulator to construct a manufacturing process simulation environment under abnormal conditions; Step S232: calling a time sequence backtracking analysis algorithm to reversely track data changes from an abnormal point, analyze design rule constraints and process parameter change trends, and locate the problem source; Step S233: generating a debugging report containing design modification suggestions and process adjustment schemes according to the problem source analysis results, in combination with design rules and process specifications.

[0015] To better implement the present application, further, the step S3 specifically comprises the following steps: Step S31: calling a gradient descent local optimization algorithm according to the generated debugging report, the yield, and the process parameter vector to calculate the gradient of the objective function with respect to the parameters, and constantly iteratively updating according to the gradient until the yield is locally optimal; Step S32: calling a reinforcement learning algorithm, taking the local optimal yield as a target function, searching for an optimal process parameter combination, and combining historical optimization cases to dynamically adjust the parameter adjustment step to obtain a wafer manufacturing signature optimization result; Step S33: feeding back the signature optimization result to a design tool and a manufacturing execution system in real time, triggering design iteration or process reconfiguration through an API interface, and forming a closed loop cycle of "signature-optimization-reverification".

[0016] Based on the wafer manufacturing signature method proposed above, in order to better realize the present application, further, a wafer manufacturing signature system is proposed for executing the wafer manufacturing signature method described above; comprising a collaborative data integration module, a real-time signature verification module, and an agile optimization iteration module; The collaborative data integration module is used for integrating collected chip design data and production process parameters, and storing the integrated chip design data and production process parameters according to a constructed multi-level cache mechanism; The real-time signature verification module is used for deploying a special hardware monitor and configuring a data checker according to the integrated chip design data and production process parameters, comparing design target parameters with actual production data in real time, and generating a debugging report according to captured snapshot data; The agile optimization iteration module is used for calling a gradient descent local optimization algorithm according to the generated debugging report, and feeding back the optimization result to a design and manufacturing system.

[0017] The present application has the following beneficial effects: (1) The present application reduces data format adaptation time through a standardized data interface and automatic test conversion; a partial reconfiguration mechanism avoids full-process repeated verification, and the signature efficiency is improved by 300%-500% compared with traditional methods.

[0018] (2) The present application realizes accurate reproduction of abnormal conditions by snapshot capture and simulation reconstruction technology, and the problem positioning time is shortened from several days to hours, and the root cause analysis accuracy is improved to more than 90%.

[0019] (3) The real-time collaborative verification and intelligent optimization engine of the present application shortens the process parameter adjustment period by 40%, and combined with a closed loop feedback mechanism, the yield can be improved from the initial value to more than 90% of the target value within 3 production batches.

[0020] (4) The present application breaks the design and manufacturing data barrier, realizes end-to-end collaboration from design verification to manufacturing signature, and reduces the yield loss caused by information asymmetry by 10%-15%. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 The wafer manufacturing signature method flowchart provided by the present application is shown. DETAILED DESCRIPTION

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be understood that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Therefore, they should not be regarded as limiting the scope of protection. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0023] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "set", "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0024] Embodiment 1 The present embodiment proposes a wafer manufacturing signature method, which specifically comprises the following steps.

[0025] Step S1: integrate the collected chip design data and production process parameters, and store the integrated chip design data and production process parameters according to the constructed multi-level cache mechanism; The step S1 specifically comprises the following steps: Step S11: call the standardized data packaging template to obtain the hardware-data interface template, collect the chip design data and production process parameters, and integrate them; The step S11 specifically comprises the following steps: Step S111: obtain the hardware-data interface template according to the standardized data packaging template, and call the standardized mapping rule to connect the chip design data and the production process parameters; Step S112: call the automatic test data conversion tool stream to convert the unit-level test data at the design end into production-level verification excitation to generate test vectors covering key process nodes; Step S113: call the heterogeneous data mapping platform to map the chip design model, the process physical model and the corresponding C / C++ simulation model to the same verification environment based on the wafer manufacturing simulation platform, synchronously run the design reference model and the process simulation model, and realize real-time correlation analysis of cross-level data.

[0026] The embodiment provides a unified hardware-data interface template through a standardized data packaging template, connects chip design data (such as GDSII layout, netlist file) and production process parameters (lithography dose, etching rate, etc.) by using a standardized mapping rule, solves the design and manufacturing data format heterogeneity problem, automatically converts unit-level test data at the design end into production-level verification excitation by means of an automatic test data conversion tool flow, generates test vectors covering key process nodes, and achieves seamless connection from design verification to manufacturing sign-off; and by relying on a heterogeneous data mapping platform and based on a wafer manufacturing simulation platform, the chip design model, the process physical model and the corresponding C / C++ simulation model are mapped to the same verification environment, the design reference model and the process simulation model are synchronously run, and real-time correlation analysis of cross-level data is realized.

[0027] Step S12: According to the unified hardware-data interface template, a first-level cache mechanism is constructed, a second-level cache mechanism of unit-level test data and production-level verification excitation is constructed, and a third-level cache mechanism is constructed by calling a wafer manufacturing simulation platform, and the integrated chip design data and production process parameters are stored.

[0028] The step S12 specifically includes the following steps: Step S121: A first-level cache mechanism based on the unified hardware-data interface template is constructed, a standardized data packaging cache layer is constructed, and standardized mapping rules of the chip design data and the production process parameters are pre-stored; Step S122: A second-level cache mechanism of unit-level test data and production-level verification excitation is established, an automatic test data conversion cache layer is established, and a development tool flow is called to generate key process node test vectors and cache; Step S123: A third-level cache mechanism is constructed by calling a wafer manufacturing simulation platform, and mapping relationships of the chip design model, the process physical model and the C / C++ simulation model are stored in the cache.

[0029] The embodiment maintains a multi-level cache mechanism according to the needs of process steps. First, a first-level cache based on the unified hardware-data interface template is constructed for a standardized data packaging cache layer, and standardized mapping rules of the chip design data (such as GDSII layout, netlist file) and the production process parameters (lithography dose, etching rate, etc.) are pre-stored; second, a second-level cache mechanism of unit-level test data and production-level verification excitation is established for an automatic test data conversion cache layer, and key process node test vectors generated after processing of data such as device reliability simulation results at the design end by a development tool flow are cached; and finally, a third-level cache network is constructed based on a wafer manufacturing simulation platform, that is, a heterogeneous data mapping cache network, and mapping relationships of the chip design model, the process physical model and the C / C++ simulation model are stored in the cache.

[0030] Take two independent cache areas, cache A and cache B, as an example. In the data collection stage, the newly collected data is first written to cache A. When cache A is full or reaches a preset time threshold, it immediately switches to cache B for data writing, while the data in cache A is encapsulated, verified, and written to the time series database through a stable transmission channel. After the transmission of cache A is completed, if cache B is not full, it switches back to cache A for data collection, and this cycle continues to ensure the continuity and reliability of data transmission. Finally, the data of the EDA tool and the process monitoring system are connected, and the collected data is stored in the time series database, supporting millisecond-level data query response.

[0031] Step S2: According to the integrated chip design data and production process parameters, deploy a special hardware monitor and configure a data checker to compare the design target parameters with the actual production data in real time, and generate a debugging report according to the captured snapshot data; The step S2 specifically includes the following steps: Step S21: Deploy a special hardware monitor and configure a data checker to compare the design target parameters with the actual production data in real time, and automatically identify the parameter deviation caused by process deviation and trigger an abnormal alarm according to the constructed dynamic threshold model; The step S21 specifically includes the following steps: Step S211: Deploy a special hardware monitor to collect actual production data in real time, and obtain design target parameters; Collect actual production data in real time through a special hardware monitor (wafer surface topography sensor, process parameter acquisition module) At the same time, obtain the design target parameters .

[0032] Step S212: Construct a dynamic threshold model according to the obtained historical production data and process specifications; Based on historical production data and process specifications, construct a dynamic threshold model Wherein is a set of process parameters, is a historical data feature, and the dynamic threshold is used to define the normal fluctuation range of the parameter.

[0033] Step S213: Calculate the deviation value according to the collected actual production data and design target parameters; Threshold model establishment. Deviation calculation. Calculate the deviation value of the actual production data and the design target parameters .

[0034] Step S214: Determine whether an abnormality occurs according to the deviation value and the dynamic threshold model, and trigger an abnormal alarm if so.

[0035] If If so, it is determined that a process deviation occurs, and an abnormal alarm is triggered.

[0036] In the wafer manufacturing sign-off process, the embodiment realizes problem positioning and solving through three links of process-design collaborative verification, snapshot problem capture and simulation reconstruction and debugging. First, a special hardware monitor, such as a wafer surface topography sensor and a process parameter acquisition module, is deployed, and a data checker is configured to compare design target parameters (such as line width, device threshold voltage) with actual production data in real time, automatically identify parameter deviations caused by process deviation by using a dynamic threshold model, and trigger an abnormal alarm. When it is detected that the design and manufacturing data are inconsistent, for example, the deviation between the yield prediction value and the measured value is more than 5%, snapshot problem capture is started, the system automatically captures the hardware state snapshot of the key process node, covering three-dimensional topography data such as lithography pattern and etching depth, and synchronously records the corresponding design parameter configuration. Finally, the captured snapshot data is imported into an external simulator to build a manufacturing process simulation environment under abnormal conditions, accurately locates the problem source such as design rule conflict or process parameter drift through time sequence backtracking analysis, and generates a debugging report integrating design modification suggestions and process adjustment schemes.

[0037] To better realize the present application, further, the step S22 specifically comprises the following steps: Step S221: calculating the yield deviation according to the yield prediction value and the yield measured value obtained by real-time monitoring; Real-time monitoring of yield prediction value and measured value .

[0038] Step S222: if the yield deviation is greater than the set yield deviation threshold, triggering the capture mechanism; Calculating the yield deviation When ΔY> 5% (set threshold), the capture mechanism is triggered.

[0039] Step S223: obtaining the hardware state snapshot data of the key process node according to the triggered capture mechanism, and recording the corresponding design parameter configuration; Step S22: if the design target parameter and the actual production data are inconsistent, starting snapshot problem capture, capturing the hardware state snapshot of the key process node, and recording the corresponding design parameter configuration; Automatically capturing the hardware state snapshot data of the key process node , including three-dimensional topography data such as lithography pattern and etching depth, and recording the corresponding design parameter configuration .

[0040] Step S23: importing the captured snapshot data into an external simulator, building a manufacturing process simulation environment under abnormal conditions, time backtracking analysis accurately locating the problem source, and generating a debugging report integrating design modification suggestions and process adjustment schemes.

[0041] The step S23 specifically includes the following steps: Step S231: importing hardware state snapshot data and design parameter configurations into an external simulator, building a manufacturing process simulation environment under abnormal conditions; The captured snapshot data and design parameter configurations are imported into an external simulator, building a manufacturing process simulation environment under abnormal conditions .

[0042] Step S232: calling a time backtracking analysis algorithm, starting from the abnormal point to trace data changes in reverse, analyzing design rule constraints and process parameter change trends, and locating the problem source; The time backtracking analysis algorithm is used to trace data changes in reverse from the abnormal point, analyze design rule constraints and process parameter change trends, and locate the problem source .

[0043] Step S233: according to the problem source analysis result, combining design rules and process specifications, generating a debugging report containing design modification suggestions and process adjustment schemes.

[0044] Based on the problem source analysis result, combining design rules and process specifications, a debugging report containing design modification suggestions and process adjustment schemes is generated .

[0045] Step S3: calling a gradient descent local optimization algorithm according to the generated debugging report, and feeding back the optimization result to the design and manufacturing system.

[0046] The step S3 specifically includes the following steps: Step S31: calling a gradient descent local optimization algorithm according to the generated debugging report, yield, and process parameter vector, calculating the gradient of the objective function with respect to the parameters, and constantly iterating and updating according to the gradient until the yield is locally optimal; Partial reconfiguration optimization. For local process problems found in the signing process, such as low yield in a certain photolithography area, only related process parameter subsets (such as exposure dose, focus value) or local design modules (such as layout wiring) are adjusted, without restarting the full flow signing, and rapid iteration verification is realized through parameter reconfiguration. In the specific implementation process, a local optimization algorithm based on gradient descent is used, assuming that the objective function is yield , process parameter vector , the gradient of the objective function with respect to the parameters is calculated , the iterative update is performed according to the formula , where is the learning rate, used to control the step size of each parameter update; , the number of iterations, through continuous iteration, until the yield reaches the local optimum.

[0047] Step S32: Call the reinforcement learning algorithm to improve the local optimal yield as the target function, search for the optimal process parameter combination, and dynamically adjust the parameter adjustment step size combined with historical optimization cases to obtain the wafer manufacturing signature optimization result; Intelligent optimization engine. Based on the reinforcement learning algorithm, the yield improvement is taken as the target function, and the optimal process parameter combination is automatically searched. A Markov decision process (MDP) is constructed, the state space S is the set of process parameter combinations and production environment parameters, the action space A is the parameter adjustment scheme, and the reward function is defined as the yield improvement amplitude. The algorithm performs Q value iterative update through the formula , where is the learning rate, consistent with the algorithm mentioned above, controls the parameter update step size, and determines the degree of updating the original Q value with the newly obtained information; is the discount factor, ranging from [0, 1], used to measure the importance of future rewards, the closer to 0, the more the algorithm focuses on short-term rewards, and the closer to 1, the more it focuses on long-term rewards; is the immediate reward obtained after performing action from state to new state ; represents the expected cumulative reward obtained after performing action in state ; represents the expected cumulative reward after performing action in new state . Combined with historical optimization cases, the parameter adjustment step size is dynamically adjusted (such as optimizing the lithography dose adjustment precision from ±5mJ / cm2 to ±1mJ / cm2), and the parameter convergence period is shortened.

[0048] Step S33: Real-time feedback of the signature optimization result to the design tool and manufacturing execution system, triggering design iteration or process reconfiguration through API interface, forming a closed loop cycle of "signature-optimization-reverification".

[0049] Closed-loop feedback channel. The approved optimization results (such as process parameter corrections and design modification suggestions) are fed back to the Design Tools and Manufacturing Execution System (MES) in real time. This triggers design iterations or process reconfiguration via API interfaces, forming a closed-loop cycle of "approval-optimization-re-verification". Within the closed-loop system, the Kalman filter algorithm is used to process and predict the feedback data. Assuming the system state equation is... The observation equation is ,in: express The system state vector at time t; The state transition matrix describes the system's transition from state to state. Time's up The transition relationship between states at different times; The control input matrix reflects the control input. Impact on system state; yes The control input vector at each time step; The process noise vector represents unpredictable disturbances in the system, and is usually assumed to follow a Gaussian distribution with a mean of 0. for The observation vector at time; The observation matrix describes the mapping relationship between the system state and the observed values; Let be the observation noise vector, representing the error introduced during the observation process, also assumed to follow a Gaussian distribution with a mean of 0. This is then analyzed using Kalman gain. Perform optimal estimation and update of the state, where It is the prior estimation error covariance matrix. It observes the noise covariance matrix to ensure the accuracy and effectiveness of the feedback data, thereby optimizing the entire closed-loop process.

[0050] Agile optimization and iteration process: During the approval process, if local process issues such as low yield in a certain lithography area are found, partial reconfiguration optimization can be achieved by adjusting only a subset of relevant process parameters such as exposure dose and focus value, or local design modules such as layout and routing, without restarting the entire approval process, thus enabling rapid iterative verification; The intelligent optimization engine is based on reinforcement learning algorithms, with yield improvement as the objective function, automatically searches for the optimal combination of process parameters, and dynamically adjusts the parameter adjustment step size by combining historical optimization cases, shortening the parameter convergence cycle; The closed-loop feedback channel feeds back the approval optimization results (process parameter correction values, design modification suggestions) to the design tools and manufacturing execution system (MES) in real time through the API interface, triggering design iteration or process reconfiguration, forming a closed loop of "approval-optimization-re-verification".

[0051] Working principle: This embodiment constructs an agile signing framework combined with chip design and production process data, integrates high-level abstract analysis and high-precision process modeling capabilities, realizes efficient verification, real-time checking and rapid optimization of the manufacturing process, thereby ensuring the manufacturability, performance and quality of the chip, and improving the production yield and signing efficiency.

[0052] Embodiment 2: This embodiment is based on the above-mentioned embodiment 1, as shown in a specific embodiment, and specifically includes the following steps. Figure 1

[0053] Step S1: Construct a collaborative data integration framework.

[0054] By introducing a time sequence acquisition mechanism, setting a periodic acquisition interval, and using a multi-level cache strategy, the stability and reliability of the data in the acquisition and transmission process are ensured, while the continuity of the original data docking, storage and query functions is maintained. The reliable transmission of data is realized through the following time sequence acquisition mechanism and double cache strategy: Step S11: Time sequence acquisition strategy. The system is based on a time-driven acquisition strategy, and sets a configurable acquisition period (such as minute or second level). Through a timing task, the design-process associated data acquisition of EDA tools (such as Cadence Virtuoso) and process monitoring systems is triggered. At the beginning of each acquisition period, the system automatically scans the data to be synchronized, ensuring that 1000+ batches of data are automatically synchronized every day.

[0055] Step S12: Process collaborative data integration step based on multi-level cache strategy (taking etching process as an example).

[0056] Step S121: Construct a multi-level cache architecture. Taking the two-level cache of the etching step process as an example, in the data docking process of EDA tools (such as Cadence Virtuoso) and process monitoring systems, a primary buffer (Primary Buffer) and a secondary buffer (Secondary Buffer) are introduced. The primary buffer is used to temporarily store the original data of the etching step obtained from the EDA tool and the process monitoring system in real time, and the secondary buffer is used as a data processing transit station to store the data to be stored after preliminary cleaning and conversion.

[0057] Step S122: Data acquisition and shunting. Through a customized data interface, real-time acquisition of key data in the etching step is realized, including etching time, etching rate, etching depth, equipment parameters, etc. The collected data is written into the primary buffer and the secondary buffer according to the preset rules, ensuring the integrity and redundancy of the data.

[0058] ​Step S123: Parallel processing mechanism. The main cache area continuously receives newly collected data, while the auxiliary cache area starts a data processing thread. This thread cleans up the data in the auxiliary cache area, removing noise data and invalid records; formats and maps the data according to the data storage format of the time series database; and performs preliminary quality assessment and anomaly detection on the data based on the quality control model of the etching process.

[0059] Step S124: Data synchronization and persistence. When the data processing in the auxiliary cache area is complete, the data synchronization mechanism is triggered. The processed data is written in batches to the time series database InfluxDB, ensuring that 1000+ batches of etching step design-process related data are automatically synchronized daily. During the data synchronization process, an asynchronous writing method is used to reduce the blocking of the data collection and processing process, achieving millisecond-level data query response.

[0060] Step S125: Cache switching and data updating. To ensure the continuity of data processing, when the data synchronization of the auxiliary cache area is complete, the roles of the main cache area and the auxiliary cache area are switched. The original main cache area becomes the auxiliary cache area for data processing, and the original auxiliary cache area becomes the main cache area to continue receiving newly collected data. At the same time, version management is performed on the processed data, and if data anomalies are found or need to be updated later, the cache area can be quickly located and corrected.

[0061] Step S13: Algorithm steps of multi-level cache strategy.

[0062] Step S131: Initialization phase. First, start the data collection module, establish a stable connection with the EDA tool and process monitoring system, and ensure the reliability of the data source. Then initialize the main cache area, auxiliary cache area, and newly added temporary cache area, and set the cache capacity and data storage structure reasonably according to the actual data flow and processing capacity. At the same time, start the data processing thread, data synchronization thread, and cache scheduling thread to prepare for subsequent data processing.

[0063] Step S132: Data collection and storage. Collect etching step data from the EDA tool and process monitoring system at fixed time intervals such as seconds. The collected data is first stored in the temporary cache area, which serves as the first station for data entering the system, performing preliminary screening and temporary storage to avoid a large amount of data directly impacting the main cache area and auxiliary cache area. When the data volume in the temporary cache area reaches a certain threshold, the data is written into the main cache area and auxiliary cache area at the same time, and the data collection timestamp is recorded.

[0064] Step S133: data processing. The data processing process is based on multi-level cache expansion. When the data volume of the auxiliary cache area reaches 80% of the cache capacity or reaches a fixed processing time interval, the data processing thread is started. The data in the auxiliary cache area is cleaned up, and invalid data records are filtered out according to the preset rules. Then, according to the data model of the time series database, the data is format-converted, and the data fields are accurately mapped to the corresponding database table structure. Based on the quality control algorithm of the etching process, the data is quality-evaluated, and abnormal data is marked. At the same time, the temporary cache area also periodically pre-processes the temporary data, reducing the processing pressure of the main and auxiliary cache areas.

[0065] Step S134: data synchronization. After data processing is completed, the data synchronization thread is triggered. The processed data in the auxiliary cache area is written in batches to the time series database, and the data synchronization timestamp is recorded. During the data synchronization process, the write state is monitored in real time, and if the write fails, the failed data is temporarily stored in the error queue for subsequent retry. In addition, if the temporary cache area has pre-processed data that meets the write-in conditions, it will also be synchronized and written into the time series database.

[0066] Step S135: cache switching strategy. After data synchronization is completed, the roles of the main cache area and the auxiliary cache area are exchanged, the data in the original auxiliary cache area (now the new main cache area) is emptied, and new collected data is prepared to be received. The data in the original main cache area (now the new auxiliary cache area) is backed up for subsequent auditing and tracing. At the same time, the temporary cache area will also adjust the data flow and storage strategy in a timely manner according to the data processing situation.

[0067] Step S136: exception handling. Exception handling runs through the entire multi-level cache strategy. During data collection, processing and synchronization, if network interruption, data format error and other exceptions occur, detailed exception logs are recorded, and corresponding recovery measures are taken according to the exception type. For data synchronization failure, the write operation is periodically retried to ensure that the data can be finally stored completely in the time series database. At the same time, different recovery strategies are developed for the data state of the temporary cache area, the main cache area and the auxiliary cache area in abnormal conditions, to ensure the stability of the system and the integrity of the data.

[0068] Step S2: real-time signing verification.

[0069] The checker module uses FPGA to realize hardware acceleration comparison, and triggers snapshot scanning and generates a report when the deviation exceeds the limit. The following details the technical scheme and algorithm process from the aspects of monitor deployment, parameter collection, algorithm execution, and exception handling.

[0070] Step S21: monitor deployment and parameter collection.

[0071] 50+ distributed monitors are deployed in the wafer manufacturing line, a distributed deployment scheme based on edge computing architecture is adopted, high-precision sensor array is built-in the monitor, and the monitor is connected with the central data processing unit through PCIe4.0 high-speed interface, ensuring that the data transmission bandwidth is not less than 16GB / s. The sampling frequency is set to 1kHz, time-triggered protocol (TTP) is used for multi-node synchronous sampling, and the sampling time synchronization accuracy of ±1μs level is realized through the hardware timer, and 200+ process parameters such as photoresist thickness and ion implantation dose can be collected in real time, among which the key parameters are designed with double-channel redundant sampling to improve data reliability.

[0072] Step S22: algorithm execution.

[0073] The checker module is implemented by FPGA, specifically using Xilinx UltraScale+ series chips, and the comparison algorithm is designed by pipeline architecture. The algorithm is based on parallel hash check mechanism, and 32-bit hash fingerprints of design parameters are pre-generated and stored in BRAM. The measured data is compared by calculating hash values in parallel through an 8-stage pipeline, and the overall delay is <10ns after timing optimization. At the same time, a dynamic threshold adaptive algorithm is used to establish a parameter fluctuation model according to historical process data, realizing dynamic adjustment of abnormal detection sensitivity.

[0074] Step S221: process-design co-verification step. 50+ distributed monitors are deployed in the wafer manufacturing line, with a sampling frequency of 1kHz, real-time collection of 200+ process parameters such as photoresist thickness and ion implantation dose, and these actual production data are compared with the design target parameters obtained by the special hardware monitor (wafer surface topography sensor, process parameter acquisition module) to complete data acquisition. The checker module is implemented by FPGA, and uses a hardware-accelerated comparison algorithm (delay <10ns) based on a dynamic threshold model built from historical production data and process specifications to calculate the deviation value of actual production data from design target parameters in real time and make abnormality judgment. When the lithography line width deviation of a batch of wafers exceeds 3nm, it is determined that there is a process deviation, triggering an abnormal alarm.

[0075] Step S222: snapshot problem capture step.

[0076] The system monitors the yield prediction value in real time and compares it with the measured value When the lithography line width deviation exceeds the threshold, i.e. the yield deviation ΔY > 5% (set threshold), the capture mechanism is triggered. At this time, the system completes the three-dimensional topography scanning of the region within 0.5 seconds (resolution 5 nm), automatically captures the hardware state snapshot data S of the key process node, including the three-dimensional topography data such as lithography pattern and etching depth, records the corresponding design parameter configuration C, and generates an abnormal report containing design layout coordinates and process parameter curves.

[0077] Step S223: simulation reconstruction and debugging step.

[0078] The captured snapshot data S and design parameter configuration C are imported into an external simulator to build a manufacturing process simulation environment E under abnormal conditions to complete the environment building. Then, a time sequence backtracking algorithm is used to track the data changes in reverse from the abnormal point, analyze the design rule constraints R and process parameter variation trend, and locate the problem root cause Time sequence backtracking is performed. Finally, based on the problem root cause analysis result, a debugging report containing design modification suggestions and process adjustment scheme is generated .

[0079] Step S23: abnormality handling.

[0080] When the lithography line width deviation of a batch of wafers is detected to exceed 3 nm, the system triggers the snapshot mechanism based on FPGA: Step S231: trigger response. The deviation signal is directly connected to the high-speed IO pin of the FPGA through interruption, triggering the highest priority interruption service program, with a response time < 100 ns Step S232: three-dimensional scanning control. Drive the self-developed nanoscale displacement table to complete the three-dimensional topography scanning of the region within 0.5 seconds by cooperating with the five-axis linkage control system. A laser interferometer with a wavelength of 405 nm is used for measurement, and a phase shift interference algorithm is used to realize a spatial resolution of 5 nm Step S233: report generation. Automatically associate the design layout coordinate information, quickly retrieve the design parameters of the corresponding region through database indexing technology; use a sliding window algorithm to perform curve fitting on the process parameters of the last 100 sampling periods, and finally generate an abnormal report containing design layout coordinates, process parameter curves, and three-dimensional scanning point cloud data. The report is stored in the EDIF format conforming to the SEMI standard, which is convenient for subsequent analysis.

[0081] Step S3: agile optimization iteration mechanism.

[0082] Aiming at the problem of low yield of SRAM area of a 7nm chip (initial yield 82%), the system adopts a model-based closed-loop optimization algorithm to realize precise adjustment of lithography parameters. The specific technical scheme is as follows: Step S31: Parameter reconfiguration based on closed-loop optimization algorithm realizes fast iteration verification.

[0083] Step S311: Data acquisition and feature extraction. The system collects key parameters in the SRAM area lithography process in real time through a sensor network, including 12 indicators such as exposure dose, focus value, and photoresist thickness, and uses principal component analysis (PCA) algorithm to reduce dimension of the data and extract 5 core features strongly related to yield.

[0084] Step S312: Yield prediction model construction. Based on historical process data and yield results, a yield prediction model based on deep learning is established. Using convolutional neural network (CNN) architecture, the extracted core features are used as input, and after 3 convolutional layers and 2 fully connected layers, the predicted value of the area yield is output. During the training process, mean square error (MSE) is used as the loss function, and stochastic gradient descent (SGD) algorithm is used for optimization, achieving 98% prediction accuracy on the validation set.

[0085] Step S313: Partial reconfiguration and parameter optimization. Using partial reconfiguration technology of field programmable gate array (FPGA), only the lithography control module corresponding to the SRAM area is adjusted. Genetic algorithm (GA) is used to optimize the lithography parameters globally, and the output of the yield prediction model is used as the fitness function. In the first iteration, the exposure dose is adjusted from 200mJ / cm² to 205mJ / cm², and the focus value is adjusted from 0.5μm to 0.48μm. After actual production verification, the yield is improved to 90%. Based on this result, in the second iteration, the exposure dose is further optimized to 210mJ / cm², and the focus value is adjusted to 0.45μm, finally making the SRAM area yield improve to 97%.

[0086] Step S314: Verification and efficiency improvement. Using Markov decision process and Kalman filtering technology, a yield intelligent optimization model and closed-loop feedback system are constructed. First, the optimization strategy is formulated through Markov decision process, and then the Kalman filter is used for real-time feedback adjustment to realize efficient yield improvement. Compared with the traditional full-process optimization method, through this model-based closed-loop optimization algorithm and partial reconfiguration technology, the total time is shortened by 65% compared with the full-process optimization.

[0087] Step S32: Intelligent optimization based on Markov decision process.

[0088] The system models the lithography parameter adjustment process as a Markov Decision Process (MDP), defining the state space as the lithography parameter combinations (exposure dose, focus value, etc.) of the SRAM area and their corresponding yield states. The action space includes discrete adjustment operations for exposure dose and focus value, such as adjusting the exposure dose in steps of 1 mJ / cm² and the focus value in steps of 0.01 μm. The reward function is set to the yield improvement amplitude, giving a high positive reward when the yield reaches or exceeds the target threshold, and a negative reward to punish ineffective adjustments.

[0089] The system uses the Q-learning algorithm to solve the optimal strategy, learning the optimal lithography parameter adjustment strategy by constantly exploring state transitions and reward feedback under different parameter combinations. In the initial state (exposure dose 200 mJ / cm², focus value 0.5 μm, yield 82%), according to the learned strategy, the exposure dose is adjusted to 205 mJ / cm² and the focus value to 0.48 μm as the first optimization action.

[0090] Step S33: Closed-loop feedback method based on Kalman filtering.

[0091] After each parameter adjustment, the system uses the Kalman filtering algorithm to process the yield data, achieving closed-loop feedback optimization. The yield after lithography parameter adjustment is taken as the observation value, while considering the influence of process noise and measurement noise, a state space model is constructed.

[0092] The system predicts the yield state at the next time according to the current state, and combines the actual measured yield data to estimate the more accurate yield state and error covariance through the prediction and update steps of Kalman filtering. For example, after the first parameter adjustment, the measured yield is 87%, and the Kalman filtering algorithm is used to process the data to correct the estimation of the yield state and determine whether the current adjustment direction is correct.

[0093] If the yield improvement trend after filtering meets the expectation, continue to adjust the parameters along the current strategy; if there is deviation, re-call the Markov Decision Process to update the optimization strategy. After two rounds of parameter adjustment based on Markov Decision Process and feedback correction by Kalman filtering, the exposure dose is optimized to 210 mJ / cm², the focus value is adjusted to 0.45 μm, and the yield of the SRAM area is improved to 97%. Since this method only dynamically optimizes and adjusts the SRAM area, it does not need to re-verify other process steps, and the total time consumption is shortened by 65% compared with full-flow optimization.

[0094] Working principle: The signature efficiency of this embodiment is greatly improved. Through standardized data interface and automatic test conversion, the data format adaptation time is reduced. The partial reconfiguration mechanism avoids full-process repeated verification, and the signature efficiency is improved by 300%-500% compared with the traditional method. The problem positioning accuracy is improved: the snapshot capture and simulation reconstruction technology realizes the accurate reproduction of abnormal working conditions, the problem positioning time is shortened from several days to hours, and the root cause analysis accuracy is improved to more than 90%. The yield optimization speed is accelerated: real-time collaborative verification and intelligent optimization engine shorten the process parameter adjustment period by 40%, combined with the closed-loop feedback mechanism, the yield can be improved from the initial value to more than 90% of the target value within 3 production batches. Cross-linkage cooperation is enhanced: breaking the design and manufacturing data barrier, realizing end-to-end cooperation from design verification to manufacturing signature, reducing the yield loss of 10%-15% caused by information asymmetry.

[0095] The other parts of this embodiment are the same as those of Embodiment 1 described above, and will not be described again.

[0096] Embodiment 3 On the basis of any one of Embodiments 1-2 described above, this embodiment proposes a wafer manufacturing signature system for executing the wafer manufacturing signature method described above; comprising a collaborative data integration module, a real-time signature verification module, and an agile optimization iteration module. The collaborative data integration module is configured to integrate the collected chip design data and production process parameters, and store the integrated chip design data and production process parameters according to the constructed multi-level cache mechanism. The real-time signature verification module is configured to deploy a special hardware monitor and configure a data checker according to the integrated chip design data and production process parameters, compare the design target parameters with the actual production data in real time, and generate a debugging report according to the captured snapshot data. The agile optimization iteration module is configured to optimize the generated debugging report by calling a gradient descent local optimization algorithm, and feed back the optimization result to the design and manufacturing system.

[0097] Working principle: This embodiment realizes real-time comparison and verification, captures abnormalities and locates problems by the real-time signature verification module, realizes local rapid optimization, intelligent parameter search and closed-loop feedback by the agile optimization iteration module, so as to ensure the efficient operation of wafer manufacturing from data interaction, abnormal detection to optimization iteration.

[0098] The other parts of this embodiment are the same as those of any one of Embodiments 1-2 described above, and will not be described again.

[0099] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification or equivalent change of the above embodiment according to the technical essence of the present application falls within the protection scope of the present application.

Claims

1. A wafer manufacturing approval method, characterized in that, Specifically, the following steps are included: Step S1: Integrate the collected chip design data and manufacturing process parameters, and store the integrated chip design data and manufacturing process parameters according to the constructed multi-level caching mechanism; Step S2: Based on the integrated chip design data and manufacturing process parameters, deploy a dedicated hardware monitor and configure a data checker to compare the design target parameters with the actual production data in real time, and generate a debug report based on the captured snapshot data; Step S3: Based on the generated debugging report, call the local optimization algorithm of gradient descent to optimize, and feed the optimization results back to the design and manufacturing system.

2. The wafer manufacturing approval method according to claim 1, characterized in that, Step S1 specifically includes the following steps: Step S11: Call the standardized data encapsulation template to obtain the hardware-data interface template, collect chip design data and manufacturing process parameters, and integrate them; Step S12: Construct a first-level cache mechanism based on the unified hardware-data interface template, construct a second-level cache mechanism for unit-level test data and production-level verification incentives, and call the wafer manufacturing simulation platform to construct a third-level cache mechanism to store the integrated chip design data and manufacturing process parameters.

3. The wafer manufacturing approval method according to claim 2, characterized in that, Step S11 specifically includes the following steps: Step S111: Obtain the hardware-data interface template according to the standardized data encapsulation template, and call the standardized mapping rules to connect the chip design data and manufacturing process parameters; Step S112: Call the automatic test data conversion tool flow to convert the unit-level test data from the design end into production-level verification stimuli and generate test vectors covering key process nodes; Step S113: Call the heterogeneous data mapping platform. Based on the wafer manufacturing simulation platform, map the chip design model, process physical model and their corresponding C / C++ simulation model to the same verification environment, and run the design reference model and process simulation model synchronously to realize real-time correlation analysis of cross-level data.

4. The wafer manufacturing approval method according to claim 3, characterized in that, Step S12 specifically includes the following steps: Step S121: Construct a first-level cache mechanism based on a unified hardware-data interface template, standardize the data encapsulation cache layer, and pre-store standardized mapping rules between chip design data and manufacturing process parameters; Step S122: Establish a two-level caching mechanism for unit-level test data and production-level verification stimuli, automatically convert test data into a caching layer, and call the development tool flow to generate test vectors for key process nodes and cache them; Step S123: Call the wafer manufacturing simulation platform to build a three-level cache mechanism and store the mapping relationship between the chip design model, process physics model and C / C++ simulation model in the cache.

5. The wafer manufacturing approval method according to claim 1, characterized in that, Step S2 specifically includes the following steps: Step S21: Deploy a dedicated hardware monitor and configure a data inspector to compare the design target parameters with the actual production data in real time. Based on the constructed dynamic threshold model, automatically identify parameter deviations caused by process offsets and trigger abnormal alarms. Step S22: If the design target parameters are inconsistent with the actual production data, start snapshot-style problem capture, capture hardware status snapshots of key process nodes, and record the corresponding design parameter configurations. Step S23: Import the captured snapshot data into an external simulator to build a manufacturing process simulation environment under abnormal operating conditions. Perform time-series backtracking analysis to accurately locate the root cause of the problem and generate a debugging report with integrated design modification suggestions and process adjustment schemes.

6. The wafer manufacturing approval method according to claim 5, characterized in that, Step S21 specifically includes the following steps: Step S211: Deploy a dedicated hardware monitor to collect actual production data in real time and obtain design target parameters; Step S212: Construct a dynamic threshold model based on the acquired historical production data and process specifications; Step S213: Calculate the deviation value based on the collected actual production data and design target parameters; Step S214: Determine whether an anomaly has occurred based on the deviation value and the dynamic threshold model. If so, trigger an anomaly alarm.

7. The wafer manufacturing approval method according to claim 5, characterized in that, Step S22 specifically includes the following steps: Step S221: Calculate the yield deviation based on the predicted yield value and the measured yield value obtained from real-time monitoring; Step S222: If the yield deviation is greater than the set yield deviation threshold, the capture mechanism is triggered; Step S223: Obtain hardware status snapshot data of key process nodes according to the triggered capture mechanism, and record the corresponding design parameter configuration.

8. The wafer manufacturing approval method according to claim 7, characterized in that, Step S23 specifically includes the following steps: Step S231: Import hardware status snapshot data and design parameter configuration into an external simulator to build a manufacturing process simulation environment under abnormal operating conditions; Step S232: Call the time-series backtracking analysis algorithm to trace data changes backward from the anomaly point, analyze the design rule constraints and process parameter change trends, and locate the root cause of the problem; Step S233: Based on the root cause analysis results, and in conjunction with design rules and process specifications, generate a commissioning report that includes design modification suggestions and process adjustment plans.

9. A wafer manufacturing approval method according to claim 1, characterized in that, Step S3 specifically includes the following steps: Step S31: Based on the generated debugging report, yield, and process parameter vector, call the gradient descent local optimization algorithm to calculate the gradient of the objective function with respect to the parameters, and continuously update iteratively based on the gradient until the yield is locally optimal; Step S32: Call the reinforcement learning algorithm to improve the yield of the local optimum to the objective function, search for the optimal combination of process parameters, and combine historical optimization cases to dynamically adjust the parameter adjustment step size to obtain the wafer manufacturing approval optimization result; Step S33: Feed back the approval and optimization results to the design tools and manufacturing execution system in real time, and trigger design iteration or process reconfiguration through the API interface to form a closed loop of "approval-optimization-re-verification".

10. A wafer manufacturing approval system for performing a wafer manufacturing approval method as described in claim 1; characterized in that, It includes a collaborative data integration module, a real-time signature verification module, and an agile optimization and iteration module; The collaborative data integration module is used to integrate the collected chip design data and manufacturing process parameters, and to store the integrated chip design data and manufacturing process parameters according to the constructed multi-level caching mechanism. The real-time signature verification module is used to deploy a dedicated hardware monitor and configure a data checker based on the integrated chip design data and manufacturing process parameters, compare the design target parameters with the actual production data in real time, and generate a debugging report based on the captured snapshot data. The agile optimization iteration module is used to call the gradient descent local optimization algorithm to optimize based on the generated debugging report, and feed the optimization results back to the design and manufacturing system.

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