Stress silicon (Si) vertical-groove silicon-on-insulator bipolar complementary metal-oxide semiconductor (SOI BICMOS) integrated device and preparation method

A vertical channel, integrated device technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of low mechanical strength, high cost, incompatibility with wide application and development, etc.

Inactive Publication Date: 2012-12-26
XIDIAN UNIV
View PDF2 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although GaAs and InP-based compound devices have superior frequency characteristics, their preparation process is more complicated than Si process, high cost, difficult to prepare large-diameter sing...

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Stress silicon (Si) vertical-groove silicon-on-insulator bipolar complementary metal-oxide semiconductor (SOI BICMOS) integrated device and preparation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0124] Embodiment 1: The strained Si vertical channel SOI BiCMOS integrated device and circuit with a channel length of 22nm are prepared, and the specific steps are as follows:

[0125] Step 1, epitaxial material preparation.

[0126] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 150nm, and the upper material is doped with a concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;

[0127] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 250nm on the upper layer of Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 ;

[0128] (1c) Using chemical vapor deposition (CVD), grow a SiGe layer with a thickness of 20nm on the substrate at 600°C. As the base region, the Ge composition of this layer is 15%, and the doping concentration is 5×10...

Embodiment 2

[0196] Embodiment 2: The strained Si vertical channel SOI BiCMOS integrated device and circuit with a channel length of 30nm are prepared, and the specific steps are as follows:

[0197] Step 1, epitaxial material preparation.

[0198] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 300nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;

[0199] (1b) Using the chemical vapor deposition (CVD) method, at 700 ° C, grow a layer of N-type epitaxial Si layer with a thickness of 250 nm on the upper Si material, as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 ;

[0200] (1c) Using chemical vapor deposition (CVD), grow a layer of SiGe layer with a thickness of 40nm on the substrate at 700°C. As the base region, the Ge composition of this layer is 20%, and the doping concentration is 1×1...

Embodiment 3

[0268] Embodiment 3: The strained Si vertical channel SOI BiCMOS integrated device and circuit with the channel length of 45nm are prepared, and the specific steps are as follows:

[0269] Step 1, epitaxial material preparation.

[0270] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;

[0271] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 300nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 ;

[0272] (1c) Using chemical vapor deposition (CVD), grow a layer of SiGe layer with a thickness of 60nm on the substrate at 750°C. As the base region, the Ge composition of this layer is 25%, and the doping concentration is 5×10 1...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to view more

Abstract

The invention discloses a stress silicon (Si) vertical-groove silicon-on-insulator bipolar complementary metal-oxide semiconductor (SOI BICMOS) integrated device and a preparation method. The preparation method comprises following steps of continuously growing n-type silicon (N-Si), p-type silicon germanium (P-SiGe), amorphous silicon (i-Si), amorphous poly silicon (i-Poly-Si) on an SOI substrate to prepare deep-groove isolation, preparing base-region shallow-groove isolation, photo-etching a base region, injecting boron ions, photo-etching a transmitting region, injecting phosphonium ions to form a collector electrode, and forming a SiGe heterojunction bipolar transistor (HBT) device; respectively photo-etching a N-channel metal-oxide semiconductor (NMOS) device active region groove and a P-channel metal-oxide semiconductor (PMOS) device active region groove, preparing a drain electrode and a grid electrode on the PMOS device active region to form a PMOS device; preparing a grid medium layer and grid polycrystal on the NMOS device active region to form an NMOS device; and photo-etching a lead to form the stress Si vertical-groove SOI BiCMOS integrated device and a circuit. The characteristics of mobility ratio anisotropy of a stress Si material are adequately utilized to prepare a stress Si vertical-groove SOI BiCMOS integrated circuit with enhanced performance under the temperature of 600 to 800 DEG C.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to a strained Si vertical channel SOIBiCMOS integrated device and a preparation method. Background technique [0002] Integrated circuits are the cornerstone and core of the economic development of an information society. Just as the American engineering and technology circle recently named the fifth electronic technology among the 20 greatest engineering and technological achievements in the world in the 20th century, "from vacuum tubes to semiconductors and integrated circuits, they have become the cornerstone of intelligent work in various industries today." Integrated circuits. It is one of the typical products that can best reflect the characteristics of knowledge economy. At present, the electronic information industry based on integrated circuits has become the world's largest industry. With the development of integrated circuit technology, the cle...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L27/12H01L21/84
Inventor 张鹤鸣王海栋胡辉勇宋建军舒斌宣荣喜戴显英郝跃
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap