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81results about How to "Improve reverse withstand voltage" patented technology

Fast recovery diode FRD chip and production process for same

The invention relates to a fast recovery diode FRD chip and a production process for the same. The process comprises the following steps of: diffusion pre-treatment, boron source pre-deposition, boron source main diffusion, diffusion after-treatment, single-surface back grinding thinning, oxidation pre-treatment, oxidation, photoetching, single-surface oxide layer removal, phosphorus source pre-deposition, phosphorus diffusion, sand blasting, platinum diffusion, N + surface mesa etching, electrophoresis, sintering, oxide layer removal, nickel plating, gold plating and chip cutting, wherein the structure of the obtained chip is P+-N-N+ type. According to the process, the uniformity of the reverse recovery time of the fast recovery diode is improved and controllability is improved, meanwhile, voltage drop is reduced, leakage current is reduced, and voltage-proof stability is improved; the contradiction of mutual condition among the reverse voltage, the positive voltage, the reverse recovery time and the leakage current of the fast recovery diode is solved to enable the various parameters to achieve the optimal matching, thus improving the reliability and switching characteristic of the diode, and reducing power consumption. The fast recovery diode disclosed by the invention breaks through the technical bottleneck of the traditional fast recovery diodes.
Owner:SUZHOU QILAN POWER ELECTRONICS

GaN hetero-junction diode device and method for manufacturing same

The invention discloses a GaN hetero-junction diode device and a method for manufacturing the same. The GaN hetero-junction diode device comprises a substrate, a buffer layer, a channel layer, a potential barrier layer, a cap layer, a first Ohm anode, an Ohm cathode and a second Ohm anode. The buffer layer is positioned on the substrate; the channel layer is positioned on the buffer layer; the potential barrier layer is positioned on the channel layer, the potential barrier layer and the channel layer form a hetero-structure, and a two-dimensional electric channel is formed at a hetero-junction interface; the cap layer is positioned on the potential barrier layer; the first Ohm anode and the Ohm cathode are positioned on the upper side of the potential barrier layer and are arranged on two sides of the cap layer, and the first Ohm anode is in contact with the cap layer; the second Ohm anode is positioned on the first Ohm anode and the cap layer and is in Ohm metal contact with the cap layer. The GaN hetero-junction diode device and the method have the advantages that the problem of conflict between forward start voltage control and reverse electric leakage in the prior art can be solved, and a diode has characteristics of low start voltages and turn-on resistance and high reverse withstand voltages and forward turn-on currents.
Owner:GPOWER SEMICON

Silicon carbide diode with low turn-on voltage and low on resistance and manufacturing method

The invention provides a silicon carbide diode with low turn-on voltage and low on resistance and a manufacturing method thereof. The silicon carbide diode comprises a cathode metal electrode, an N +substrate above the cathode metal electrode and an N-drift region above the N + substrate, a P-type shielding buried layer arranged above the N-drift region; a P + ohmic contact region arranged in theP-type shielding buried layer, an anode metal electrode arranged above the P + ohmic contact region, a trench gate dielectric layer arranged above the P-type shielding buried layer, a polysilicon trench gate arranged in the trench gate dielectric layer, an N+ source regions arranged between the trench gate dielectric layers, a plane gate dielectric layer arranged above the N + source regions, anda polysilicon plane gate arranged in the plane gate dielectric layer. The anode metal electrode covers the trench gate dielectric layer, the polysilicon trench gate, the N+ source region, the plane gate dielectric layer and the polysilicon plane gate. According to the invention, the three-channel accumulation type channel MOSFET and the JFET are connected in series to form the super-barrier diode, and the silicon carbide diode has the characteristics of low turn-on voltage, small on-resistance, high reverse withstand voltage, small leakage current and the like.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA

High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device

The invention relates to a high-voltage LDMOS (landscape diffusion metal oxide semiconductor) device which comprises a substrate, an epitaxial layer, a drift region, a drain region, a source region and at least one pair of n-type semiconductor regions and p-type semiconductor regions, wherein the epitaxial layer is positioned above the substrate; the drift region is positioned on one side, close to the drain region, of the epitaxial layer, and the lower surface of the drift region is coincided with the lower surface of the epitaxial layer; the drain region and the source region are positioned at two ends of the LDMOS device; at least one pair of the n-type semiconductor regions and the p-type semiconductor regions are arrayed alternatively, pass through the lower surface of the epitaxial layer on the border surface of the substrate and the epitaxial layer; the border surface of the n-type semiconductor regions and the p-type semiconductor regions is in parallel with the surface voltage drop direction of a power device in working; and the n-type semiconductor regions and the p-type semiconductor regions are arrayed closely, thus a PN junction is formed. The invention has the beneficial effects that the n-type semiconductor regions and the p-type semiconductor regions provided by the invention are named a bulk reduced surface field layer, and the contradiction of improving the reverse withstand voltage and reducing the positive conduction resistance of the existing LDMOS device is solved effectively by the LDMOS device with the bulk reduced surface field layer.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA

Semiconductor device and manufacturing method thereof

The invention discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor device comprises a plurality of cells which are the same in structure and are sequentially connected with one another, wherein each cell comprises an N-type doped substrate, an N-type lightly doped epitaxial layer, a diffused P-type well region, a first P-type heavily dope region, an N-type heavily dope region, an oxidation layer, a metal cathode, a second P-type heavily doped region and a metal anode; the N-type lightly doped epitaxial layer is located on the N-type doped substrate; the diffused P-type well region is located in the N-type lightly doped epitaxial layer; the first P-type heavily dope region and the N-type heavily dope region are located in the diffused P-type well region; the oxidation layer is located on the upper surfaces of the N-type lightly doped epitaxial layer and the diffused P-type well region; the metal cathode covers the overall cells; and the second P-type heavily doped region and the metal anode are located on the lower surface of the N-type doped substrate. According to the semiconductor device disclosed by the invention, a semiconductor material which is opposite to the substrate in the doping type is injected into the back surface of the substrate, so that, on one hand, holes are injected into the N-type substrate and the N-type lightly doped epitaxial layer through P-type heavily doped back injection, the semiconductor device has two carrier currents, namely a hole current and an electron current, and the current density of the device is increased; and on the other hand, the reverse withstand voltage of the device can be improved.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA

High-voltage-resistant silicon carbide device and preparation method thereof

The invention discloses a high-voltage-resistant silicon carbide device and a preparation method thereof, the high-voltage-resistant silicon carbide device comprises a silicon carbide substrate, a silicon carbide epitaxial layer arranged on the silicon carbide substrate and a drain metal electrode arranged on the back surface of the silicon carbide substrate, and a blocking injection region and a source injection region are sequentially arranged on the silicon carbide epitaxial layer; a plurality of first grooves and second grooves are etched in the silicon carbide epitaxial layer; a gate protection region is arranged at the bottom of the first groove, an oxide layer grows on the surface of the first groove, a gate polycrystalline silicon electrode is arranged on the oxide layer, and an insulating layer covers the gate polycrystalline silicon electrode; the bottom of the second groove is provided with a voltage-withstanding injection region, and the second groove is provided with a polycrystalline silicon filler. And the source electrode injection region and the insulating layer are covered with a source electrode metal electrode, so that the problems of low reverse voltage and complex process in the prior art are solved.
Owner:成都功成半导体有限公司

Schottky diode controlled by junction barrier having superposed P<+>-P structure

InactiveCN102208456AEasy to meet application requirementsImprove reverse withstand voltageSemiconductor devicesCapacitanceElectronic systems
The invention provides a schottky diode controlled by a junction barrier having a superposed P<+>-P structure. The schottky diode comprises an N<+> type substrate zone (100), an N type drift region (101), P<+> portions of the superposed P<+>-P structure (102), an anodic electrode (104), a cathodic electrode (105), a silicon dioxide layer (106), a schottky contact (107), and an ohmic contact (108). Besides, the schottky diode also includes P portions of the superposed P<+>-P structure (103), wherein the P<+> window portions of the superposed P<+>-P structure (102) is on the P window portions of the superposed P<+>-P structure (103). According to the invention, before the P<+> portions of the superposed P<+>-P structure in an area are formed, the P portions of the superposed P<+>-P structure in an area are formed, wherein the P portions are separated from each other and the structure of P portions is similar to the netted structure of a junction barrier schottky (JBS). Therefore, reverse withstand voltage of the JBS diode device can be improved and the output capacitance can be reduced, on the condition that the forward conduction characteristic of the device is not sacrificed. The process of the invention has the strong feasibility of implementation, and the application requirement of the power electronic system can be satisfied easily according to the invention.
Owner:HARBIN ENG UNIV

Power diode and method for manufacturing power diode

The invention relates to a power diode and a method for manufacturing the power diode. The power diode comprises a bottom electrode, a substrate layer, an N- type epitaxial layer and a top electrode, wherein the top electrode serves as the positive electrode of the power diode, the bottom electrode serves as the negative electrode of the power diode, at least two grooves are transversely formed in the upper portion of the N- type epitaxial layer in a spaced mode, and an MOS channel is formed in the portion, between every two adjacent grooves, of the N- type epitaxial layer. The power diode is made of silicon materials and can be obtained through an existing silicon semiconductor integrated circuit; special metal materials are not needed, and the method for manufacturing the power diode is compatible with an existing semiconductor production technology; the backward voltage resistance of the device is improved through p+ regions injected into the grooves; when backward voltage is applied to the device, the p+ exhaustion regions in the grooves expand and are connected, a backward current channel is cut off, and the voltage resistance of the device is improved; when the power diode operates in the forward direction, electricity is conducted through parasitic mosfet, and the forward starting voltage of the device is reduced.
Owner:无锡橙芯微电子科技有限公司

Manufacturing method of BiCMOS integrated circuit

The present invention provides a manufacturing method of a BiCMOS integrated circuit. The method comprises a step of orderly forming a first oxide layer and the silicon nitride layer on the surface of a substrate, a step of removing the silicon nitride layer in a preset first area, forming second oxide layers in the first area, wherein the edges of the second oxide layers are in the shape of a beak with increasing thickness, and the beak extends to the area surface outside the first area, a step of removing the remaining silicon nitride layer and forming ion implanting area in the second area surface between the second oxide layers, a step of carrying out annealing process such that the ion implanting area is allowed to be in thermal diffusion to form a base area which surrounds the beaks of the edges of the second oxide layers. Through the scheme provided by the invention, the base area can laterally spread to an area under the beaks and surrounds the beaks, when a transistor is under high voltage, a wide depletion layer can be realized in the base area, thus the reverse voltage withstanding of the BiCMOS integrated circuit is improved, the highest working voltage of the transistor is raised, and the requirement of a high voltage device is satisfied.
Owner:PEKING UNIV FOUNDER GRP CO LTD +1

Trench MOS barrier Schottky diode and manufacturing method

Provided are a trench MOS barrier Schottky diode and a manufacturing method. The trench MOS barrier Schottky diode comprises a substrate, an epitaxial thin film manufactured on the substrate, a protective ring, an insulation dielectric film, Schottky contact metal, a first bonding block, ohmic contact metal and a second bonding block. A boss is arranged in the middle of the epitaxial thin film, and the side wall of the boss is a plane. The protective ring is manufactured on the periphery of the boss of the epitaxial thin film and is located below the plane on the periphery of the boss. The insulation dielectric film is manufactured on the side wall of the periphery of the boss of the epitaxial thin film, the height of the insulation dielectric film is flush with that of the boss of the epitaxial thin film, the insulation dielectric film is located on the protective ring, the height of the part, on the protective ring, of the insulation dielectric film is smaller than that of the surface of the boss, and the section of the insulation dielectric film is an L shape. The Schottky contact metal is manufactured on the surface of the insulation dielectric film and covers the surface of the boss of the epitaxial thin film. The first bonding block covers the surface of the Schottky contact metal. The ohmic contact metal is manufactured on the back face of the substrate. The second bonding block is manufactured on the back face of the ohmic contact metal and can further lower the power consumption of a carborundum power electronic device.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI

Composite RC-LIGBT (Reverse-Conducting Lateral Insulated Gate Bipolar Transistor) device integrated with LDMOS (Laterally Diffused Metal Oxide Semiconductor) and LIGBT (Lateral Insulated Gate Bipolar Transistor)

The invention discloses a composite RC-LIGBT (Reverse-Conducting Lateral Insulated Gate Bipolar Transistor) device integrated with an LDMOS (Laterally Diffused Metal Oxide Semiconductor) and an LIGBT(Lateral Insulated Gate Bipolar Transistor). The composite RC-LIGBT device comprises an LDMOS active area and an LIGBT active area which form a left and right symmetrical structure and share the sameemitter. A channel of the LDMOS active area is controlled by a gate I. The channel of the LIGBT active area is controlled by a gate II. A metal collector I is connected with a metal collector II. Thecomposite RC-LIGBT device has the following advantages that when forward switch-on is carried out, snapback effect is eliminated; due to existence of a collector N-Collector in the LDMOS area, when backward switch-on is carried out, the RC-LIGBT composite is enabled to have backward switch-on capability; and blocking effect of a collector P-Collector to a current does not exist, so the backward switch-on capability of the composite RC-LIGBT is superior to that of a conventional RC-LIGBT. The composite RC-LIGBT technology provided by the invention is compatible with a conventional RC-LIGBT technology, only layout design is required, and an additional technology is avoided.
Owner:CHONGQING UNIV OF POSTS & TELECOMM
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