6results about How to "Improve reverse withstand voltage" patented technology

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the base comprises a substrate and an epitaxial layer which are stacked; the main junction is positioned in the epitaxial layer; at least one field limiting ring located in the epitaxial layer; the junction termination extension region is located in the epitaxial layer; the junction termination expansion region and the field limiting ring have an overlapping region; the cut-off ring is located in the epitaxial layer; wherein the surfaces of one sides, far away from the substrate, of the main junction, the field limiting ring, the cut-off ring and the junction termination extension region are flush with the surface, far away from the substrate, of the epitaxial layer; the main junction, the field limiting ring and the cut-off ring are arranged at intervals along a first direction, and the first direction is perpendicular to a direction pointing to the main junction along the substrate; the field oxide layer is at least located on the sides, away from the substrate, of the epitaxial layer, the junction termination extension region and the cut-off ring; the field plates are respectively positioned on one sides, far away from the substrate, of the main junction and the field oxide layer; wherein the doping types of the substrate and the cut-off ring are the same, and the doping types of the main junction, the field limiting ring and the junction termination expansion region are the same. The semiconductor structure has a high withstand voltage level.

The invention provides a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and the method comprises the following steps: preparing and forming an epitaxial layer on a SiC substrate, and respectively forming an inverted floating layer and a P-WELL layer on the surfaces of an N-type base layer and a current expansion layer through ion implantation; preparing an N-type source layer, a P + layer and a grid layer on the epitaxial layer; and sequentially preparing and forming an ILD layer, an electrode layer and a passivation layer on the surface of the device to obtain a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device. Through the arrangement of the inverted floating layer, when the device is short-circuited, the P-WELL layer is connected with the inverted floating layer through the P + layer, namely, heat borne by the P + layer is dispersed into a semiconductor material, burnout is not easy to occur after the heat is dispersed, and the short-circuit tolerance capability is improved; when the device works normally, the inversion floating layer forms a depletion layer, so that the electric field trend at the corner of the P-WELL layer becomes slow, and the voltage endurance capability of the device is enhanced.

The present application relates to a SiC Schottky diode with wide process window and a manufacturing method thereof, wherein the SiC Schottky diode comprises a first conductive type semiconductor substrate, a first conductive type semiconductor epitaxial layer, a patterned silicon dioxide layer and a first metal layer; a first surface of the first conductive type semiconductor epitaxial layer is provided with a second conductive type main junction, a projection of the patterned silicon dioxide layer on the first conductive type semiconductor substrate is located within a projection of the second conductive type main junction on the first conductive type semiconductor substrate; and a projection of the first metal layer on the first conductive type semiconductor epitaxial layer overlaps with a projection of the patterned silicon dioxide layer on the first conductive type semiconductor epitaxial layer. The present application utilizes an angular dielectric layer structure to realize the lifting of the terminal metal, and can improve the overall reverse withstand voltage and reliability of the device.

The invention discloses lead-free powder glass for surface stabilization of a mesa type semiconductor device and application of the lead-free powder glass, the lead-free powder glass comprises base material powder and zinc oxide-containing crystal powder, the base material powder comprises the following components in percentage by weight: 50-70% of ZnO, 35-22% of B2O3, 15-25% of SiO2, 0.01-5% of RxOy and 20-15% of Y2O3 and / or GeO, and RxOy is at least one of SnO2 and the like; the zinc oxide-containing crystal powder is at least one of Zn4B6O13 and the like, and the D50 particle size of the powder glass is 1-10 [mu] m. According to the glass powder provided by the invention, various components in the base material powder of the zinc series glass powder are properly proportioned, Y2O3 and GeO2 are introduced to homogenize the glass, and Zn4B6O13 and other crystal powder containing zinc oxide are introduced to enable the crystal granularity of the glass powder to be small, so that the glass powder can be sintered and crystallized at the relative low temperature of 700-750 DEG C, and the glass powder has the advantages of high temperature resistance, high temperature resistance, high temperature resistance and the like. And the coefficient of thermal expansion after crystallization is close to that of a semiconductor material silicon wafer, so that the silicon wafer cannot be warped and cracked, and the reverse withstand voltage is improved.

The application relates to the technical field of semiconductors, in particular to a super-junction fast recovery diode and a manufacturing method thereof, which comprises a substrate, a buffer layer located on the substrate, a drift layer located on the buffer layer, a P-type region located on the drift layer, and a P column located in the drift layer and on the buffer layer, wherein the bottom of the P column is in contact with the upper edge of the buffer layer, and the top of the P column is not in contact with the lower edge of the P-type region. Through the structural arrangement of the super-junction fast recovery diode, the reverse withstand voltage of the device is greatly improved, the on-state voltage drop is reduced, the reverse recovery performance is enhanced, and the reverse recovery loss is reduced.

The invention discloses a GaN diode and a manufacturing method thereof, and the GaN diode comprises a substrate, a GaN buffer layer, a GaN channel layer and an InAlN barrier layer which are laminated. An anode region and cathode regions located on the two sides of the anode region are arranged on the top of the InAlN barrier layer. An anode region metal electrode penetrates through a groove formed in the InAlN barrier layer to form ohmic contact with the GaN channel layer. Depletion blocks in contact with the anode metal are deposited on the two sides of the groove in the top of the InAlN barrier layer. The anode voltage can directly control the depletion and closing of the two-dimensional electron gas of the GaN channel layer, so that the turn-on voltage of the diode depends on the depletion degree of the depletion block on the 2DEG, and the reverse withstand voltage also depends on the depletion degree of the depletion block on the 2DEG and is irrelevant to the interface potential barrier of the anode metal and GaN; therefore, on the basis of ensuring relatively low forward turn-on voltage, the reverse withstand voltage is effectively improved, so that the process window is larger, and the preparation method has a potential application prospect.