35results about How to "Improve reverse withstand voltage capability" patented technology

The invention discloses a shield grid trench MOSFET device.In grid electrode structures of primitive cells, shield electrodes are formed after epitaxial layers filling trenches are etched back, and trench grids are formed at the tops of the shield electrodes; the shield electrodes and adjacent drift regions make direct contact, carrier balance is achieved, the shield electrodes of the primitive cells and the drift regions form alternately-arranged structures in the transverse direction, and the shield electrodes carry out transverse exhausting on the adjacent drift regions in reverse bias of the device.The invention further discloses a manufacturing method of the shield grid trench MOSFET device.According to the shield grid trench MOSFET device and the manufacturing method, it is unnecessary to arrange dielectric films at the bottoms of the shield electrodes, stepping of device units can be reduced, the specific on-resistance of the device can be reduced, manufacturing difficulty can be lowered, and the uniformity of device performance can be improved.

The invention discloses an insulated gate bipolar transistor and its manufacturing method. The insulated gate bipolar transistor comprises a collector region, a super-junction drift region positioned on the surface of the collector region, an active region positioned on the surface of the super-junction drift region, a first terminal structure which encircles the active region and a second terminal structure which encircles the super-junction drift region and the first terminal structure. Width of the second terminal structure increases progressively in a first direction. The first direction is from the collector region to the active region. The bottom of the second terminal structure is contacted with the collector region, and the top of the second terminal structure is flush with the top of the active region. As the insulated gate bipolar transistor provided by the application is equipped with the second terminal structure which is used as a reverse pressure terminal structure of the insulated gate bipolar transistor, reverse pressure resistance of the insulated gate bipolar transistor can be raised effectively.

The invention discloses a rectifier grain, a production method thereof and a suction cup mould. The grain is in the shape of a regular hexagon. The production method for the grain comprises the following steps of: coating a photo-resist; adhering an MASK film; exposing; making a GPP film; arranging a glass sheet; waxing a chip; arranging a baffle; adhering the baffle; accurately aligning; cutting by sand blasting; and separating the grain. The suction cup mould comprises an upper die and a lower die, wherein the upper and lower dies are detachably connected with each other so as to form a cavity which can be vacuumized; the upper surface of the upper die is provided with a notch; the bottom surface of the notch is provided with a plurality of regularly hexagonal counter bores which are cellular and arranged closely; and each counter bore is communicated with the cavity. By using the structure and the method, the rectifier grain, the production method and the suction cup mould have the advantages that: firstly, the area utilization of the grain is improved, the product is durable, and the impact resistance is enhanced; secondly, the point discharge effect is reduced and the backward voltage resistance of the product is enhanced; and thirdly, the edge of a glass trench of the grain which is cut by the sand blasting method is tidy and the electrical performance is better protected.

To provide a semiconductor diode with a part of a semiconductor lamination portion having a mesa structure portion, which is the part where a pn-junction is formed by lamination of an n-type semiconductor layer and a p-type semiconductor layer on a substrate, comprising: a protective insulating film formed by coating a main surface of the mesa structure portion, a side face of the mesa structure portion in which an interface of the pn-junction is exposed, and an etched and exposed surface of the n-type semiconductor layer; and an anode electrode formed in ohmic-contact with the p-type semiconductor layer exposed from an opening formed on a part of the main surface of the mesa structure portion of the protective insulating film, extending from the main surface, through the side face of the mesa structure portion, to the surface of the n-type semiconductor layer.

The invention relates to a power diode and a method for manufacturing the power diode. The power diode comprises a bottom electrode, a substrate layer, an N- type epitaxial layer and a top electrode, wherein the top electrode serves as the positive electrode of the power diode, the bottom electrode serves as the negative electrode of the power diode, at least two grooves are transversely formed in the upper portion of the N- type epitaxial layer in a spaced mode, and an MOS channel is formed in the portion, between every two adjacent grooves, of the N- type epitaxial layer. The power diode is made of silicon materials and can be obtained through an existing silicon semiconductor integrated circuit; special metal materials are not needed, and the method for manufacturing the power diode is compatible with an existing semiconductor production technology; the backward voltage resistance of the device is improved through p+ regions injected into the grooves; when backward voltage is applied to the device, the p+ exhaustion regions in the grooves expand and are connected, a backward current channel is cut off, and the voltage resistance of the device is improved; when the power diode operates in the forward direction, electricity is conducted through parasitic mosfet, and the forward starting voltage of the device is reduced.

The invention discloses a heterojunction power device and a manufacturing method thereof, and mainly solves the problems of current collapse phenomenon and low breakdown voltage of the existing gallium nitride-based device. The heterojunction power device comprises a substrate (1), a transition layer (2), a barrier layer (3), a source groove (7), a drain groove (8), a source electrode (9), a drain contact (10), floating island metal (11), drain island metal (12), a grid electrode (14) and a passivation layer (16), wherein a gate island (4), a floating island (5) and a drain island (6) are sequentially arranged on the barrier layer from left to right; the floating island (5) is composed of 2n-1 independent P-type semiconductor blocks, the drain island (6) is composed of m P-type semiconductor cuboid blocks, and a groove (13) is formed between every two cuboid blocks; and metal is deposited on the inner portion, the front side, the rear side and the right side of the groove to form Schottky contact (15). Current collapse can be restrained, breakdown voltage is improved, forward blocking and reverse blocking are good, and the heterojunction power device can be used for a basic device of a power electronic system.

The invention relates to the technical field of semiconductors, in particular to a JBS (Junction Barrier Schottky)-structured diode. The JBS diode comprises a first conductive type substrate, a first conductive type semiconductor layer, an anode metal layer, an insulating layer, a terminal protection region and a second conductive type semiconductor region, wherein multiple grooves are formed in the upper surface layer of the first conductive type semiconductor layer at certain intervals; the terminal protection region and the second conductive type semiconductor region are formed below the grooves; insulated side walls are formed on side walls of the grooves; the grooves are filled with conductive materials. According to the JBS diode, the improvement function of a PN junction of the JBS diode on voltage withstanding performance of the diode is effectively improved.

The invention discloses a Schottky clamping diode with a groove structure. The diode comprises an N-type epitaxial layer serving as the negative electrode of the Schottky clamping diode with the groove structure, multiple grooves formed in the N-type epitaxial layer, P-type doping areas formed on the bottom of each groove, and a metal layer formed at the upper end of the N-type epitaxial layer and at the upper end of a groove area, wherein an oxidation layer is formed in each groove, polycrystalline silicon is arranged above each oxidation layer to enable the corresponding groove to be filled up, the multiple grooves and the oxidation layers and polycrystalline silicon inside form the groove area, the bottom of each groove is wrapped in the corresponding P-type doping area, the P-type doping areas are not mutually connected, and the N-type epitaxial layer and the groove area are connected through the metal layer to serve as the positive electrode of the Schottky clamping diode with the groove structure. The invention further discloses a terminal structure matched with the Schottky clamping diode with the groove structure. According to the Schottky clamping diode with the groove structure and the terminal structure, the pressure resistance of the bottom of each groove can be improved, so that reverse pressure resistance of products is improved.

The invention relates to a Ga2O3 Schottky diode based on a diamond terminal structure and a manufacturing method. The Schottky diode comprises a Ga2O3 epitaxial layer; an active region, located in the surface layer of the Ga2O3 epitaxial layer; a terminal region, located in the Ga2O3 epitaxial layer and located on the two sides of the active region. The terminal region comprises a plurality of first diamond terminal structures and a plurality of second diamond terminal structures, the first diamond terminal structures are arranged at intervals, and the second diamond terminal structures are arranged at intervals; the plurality of first diamond terminal structures and the plurality of second diamond terminal structures are alternately distributed up and down, and pn junctions are formed between the plurality of first diamond terminal structures and the Ga2O3 epitaxial layer and between the plurality of second diamond terminal structures and the Ga2O3 epitaxial layer. A surface electric field in the Schottky diode is intensively and gradually introduced into a device body, so that the phenomenon that the device is broken down in advance is avoided, the reliability of the device is improved, and the reverse voltage endurance capability of the device under normal static characteristics is improved.

The invention relates to a groove-type MOS Schottky rectifier with deep grooves and a T-POLY structure and a manufacturing method thereof. The groove-type MOS Schottky rectifier comprises an epitaxial layer, wherein the epitaxial layer is etched at intervals along the transverse direction to form a plurality of longitudinal grooves, the grooves extend downwards from the upper surface of the epitaxial layer, the thickness of the epitaxial layer is D, D is greater than 0, and the depth of the grooves ranges from 1/2[D(1-20%)] to 1/2[D(1+20%)]; the bottom part and two inner side walls of each groove are provided with an insulating medium, and the insulating medium at the two inner side walls is of a stepped shape; polycrystal is deposited in each groove, the polycrystal is of a T-shaped structure and composed of a horizontal shoulder portion and a longitudinal extending portion, the upper surface of the horizontal shoulder portion is flush with the upper surface of the epitaxial layer, and the lower surface of the horizontal shoulder portion extends to the upper surface of the longitudinal extending portion; and the thickness of the horizontal shoulder portion is one third to half of the depth of the corresponding groove. Under high reverse bias, the groove-type MOS Schottky rectifier provided by the invention increases the potential longitudinal landing space, improves electric field distribution near corners of the bottom part of each groove and inside an oxide, and reduces the electric field intensity near barrier metal.

The invention discloses a GaN-based high-electron-mobility transistor and a manufacturing method thereof, and mainly solves the problems of current collapse of an existing GaN-based device and complex process when high breakdown voltage is realized. The transistor comprises a substrate (1), a transition layer (2) and a barrier layer (3), a source groove (7) is formed in the left edge of the barrier layer, a source (9) is deposited at the upper part of the barrier layer, a drain groove (8) is formed in the right edge of the barrier layer, a drain contact (10) is deposited at the upper part of the barrier layer, a gate island (4) is arranged at the upper part of the barrier layer, and a gate (14) is deposited at the upper part; a floating island (5) and a drain island (6) are arranged on the barrier layer on the right side of the gate island, floating island metal (11) is deposited on the upper portion of the floating island, drain island metal (12) is deposited on the upper portion of the drain island, a groove (13) is arranged between the floating island and the drain contact, and Schottky contacts (15) are deposited inside and on the upper portion of the groove. The transistor is good in forward blocking and reverse blocking, strong in inhibition of current collapse, and can be used as a basic device of a high-reliability power electronic system.

The invention discloses an electrostatic discharge protection structure in a semiconductor device, and the semiconductor device. The structure is provided with a pair of opposite diodes. A field plate which is always grounded is disposed above the node region of one diode. A depletion layer of the node region is increased through an internal electric field between the field plate and an N-type trench region, so as to improve the breakdown voltage. Because there is no oxidation layer, a conduction resistance Rdson is reduced, thereby enabling a withstand current value to be increased, and effectively solving a problem of conflict between the breakdown voltage and the withstand current.

The invention provides a diode device. The diode device includes an oxide layer, a doped polysilicon region, and cathode metal, N-type heavily doped region, N-type lightly doped region, P-type doped region, a barrier layer and anode metal which are arranged in sequence and are electrically conductive. The invention also provides a manufacturing process of the diode device, which includes the following steps: epitaxially growing the P-type doped region on the N-type lightly doped region; inward etching from the P-type doped region to the N-type lightly doped region to form a trench region; forming the oxide layer on the surfaces of the P-type doped region and the N-type lightly doped region; filling the trench region covered with the oxide layer with doped polysilicon; and sputtering metalon the P-type doped region to form the barrier layer and depositing the anode metal on the barrier layer. In forward electrification, low on-voltage is realized by Schottky contact of the P-type dopedregion and the barrier layer. In reverse electrification, high reverse withstand voltage is realized by a PN junction formed by the P-type doped region and the N-type lightly doped region.

The invention discloses a schottky diode which comprises an N-type epitaxy arranged on an N-type substrate and deep grooves formed in the N-type epitaxy. A silica layer is arranged in each deep groove and a polycrystalline silicon area is arranged at the inner side of the silica layer. A schottky contact area is arranged on the N-type epitaxy between deep grooves, and a metal layer is arranged on the schottky contact area, wherein the depth of the silica layer is larger than 1000 angstroms and the polycrystalline silicon area is connected with the metal layer through a metal wire. When the depth of silica layer filling each deep groove is larger than 1000 angstroms, the schottky diode can endure the high pressure of over 80 V.

The invention provides a shield gate trench field effect transistor and a preparation method thereof. The method mainly comprises the steps: providing a substrate, forming an epitaxial layer on the upper surface of the substrate, forming a deep trench in the epitaxial layer, and forming a shielding oxide layer, shield polysilicon, a first isolation oxide layer and a second isolation oxide layer on the inner wall of the deep trench, wherein the density of the first isolation oxide layer is greater than that of the second isolation oxide layer; removing the second isolation oxide layer, a part of the first isolation oxide layer and the shielding oxide layer through wet etching, so that an obtuse angle is formed between the upper surface of the shielding oxide layer and the side wall of the deep trench; forming a gate oxide layer and gate polysilicon on the inner wall of the deep trench; and forming other structures of the field effect transistor. According to the method, the reverse voltage endurance capability of the gate oxide layer can be effectively improved, and other working parameters of the field effect transistor cannot be influenced; and the preparation method provided by the invention is easy to realize in process manufacturing and mass production.