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A deep trench dmos device

A deep groove and device technology, applied in the field of deep groove DMOS devices, can solve the problems of increased junction surface, high production cost, poor body diode reverse recovery characteristics, etc., and achieve the goal of reducing on-resistance and improving reverse withstand voltage performance Effect

Active Publication Date: 2020-09-29
HANGZHOU SILICON-MAGIC SEMICON TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the current introduction of super-junction technology also brings the following two main defects to the practical application and development of devices: one is that the junction surface of the lateral PN junction inside the device increases, making the reverse recovery characteristics of the body diode become The second is that the formation of alternating PN junctions is difficult and the production cost is too high

Method used

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Experimental program
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Effect test

Embodiment 1

[0026] Such as figure 1 As shown, this embodiment provides a deep trench DMOS device, including: N + Substrate 2, at N + The backside of the substrate 2 is provided with a metallized drain 1, and the N + The front side of the substrate 2 is provided with an N-type drift region 3, and a P-type body region 4 is provided under the surface of the N-type drift region 3, and a deep groove 7 is arranged in the P-type body region 4, and the P-type body regions on both sides of the deep groove 7 4 with N + source region 5 and P + Contact area 6, deep groove 7, N + source region 5 and P + The upper surface of the contact region 6 is in contact with the metallized source 12, the deep groove 7 has a gate electrode 8 and a gate dielectric layer 9, and the junction depth of the upper surface of the gate electrode 8 is less than N + The lower surface junction depth of the source region 5, the lower surface junction depth of the gate electrode 8 is greater than the lower surface junctio...

Embodiment 2

[0039] The structure of this embodiment is the same as that of Embodiment 1 except that the doping amount of negative charges in the strained insulating dielectric region 10 gradually decreases from top to bottom (ie, from the metallized source to the metallized drain).

[0040] This embodiment is an improvement of Embodiment 1. Through the above means, the lateral electric field distribution formed by the N-type drift region 3 and the strained insulating dielectric region 10 can be made more uniform, so that the vertical electric field is closer to the rectangular distribution, and the reverse blocking of the device is further improved. Voltage.

Embodiment 3

[0042] This embodiment provides a deep groove DMOS device, including: P + Substrate 2, at P + The backside of the substrate 2 is provided with a metallized drain 1, on the P + The front side of the substrate 2 is provided with a P-type drift region 3, and a P-type body region 4 is provided under the surface of the P-type drift region 3. There are deep grooves 7 in the P-type body region 4, and the P-type body regions on both sides of the deep groove 7 4 with P + source region 5 and P + Contact zone 6, deep groove 7, P + source region 5 and P + The upper surface of the contact region 6 is in contact with the metallized source 12, the deep groove 7 has a gate electrode 8 and a gate dielectric layer 9, and the junction depth of the upper surface of the gate electrode 8 is less than P + The lower surface junction depth of the source region 5, the lower surface junction depth of the gate electrode 8 is greater than the lower surface junction depth of the N-type body region 4, ...

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Abstract

The invention provides a deep groove DMOS device and belongs to the technical field of power semiconductor devices. The present invention includes a metallized source electrode, a drift region, a substrate, and a metallized drain electrode arranged from top to bottom; wherein the drift region has deep grooves and body regions located on both sides or the periphery thereof, and the deep grooves include gate electrodes, The gate dielectric layer and the strained insulating dielectric region, the lower surface of the strained insulating dielectric region is in contact with the upper surface of the substrate. In the present invention, by introducing a strained insulating dielectric region with compressive or tensile properties into the deep groove structure, stress is applied to the semiconductor material where the multi-subcurrent flow path is located, thereby increasing the mobility of carriers and reducing the on-resistance; At the same time, the strained insulating dielectric region is doped with charges to form a lateral electric field with the drift region, assisting in depleting the drift region, and achieving the purpose of improving the reverse withstand voltage of the device.

Description

technical field [0001] The invention belongs to the technical field of power semiconductors, and in particular relates to a deep groove DMOS device. Background technique [0002] Two key parameters of power Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) are breakdown voltage BV and on-resistance R on . Since MOSFET devices are single-stage devices, their breakdown voltage is related to the thickness of the drift region and the doping concentration of the drift region. A high breakdown voltage requires a thick drift region and a low doping concentration of the drift region, but this will make its conduction On-resistance R on Increase. On-resistance R on There is a relationship between the withstand voltage and BV: Ron∝BV 2.5 , the silicon limit. Therefore, as the withstand voltage of the device increases, the on-resistance increases exponentially, and the power consumption increases greatly. In particular, the on-resistance in typical high-voltage MOSFET d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06
CPCH01L29/0623H01L29/7813H01L29/7843
Inventor 任敏罗蕾谢驰李佳驹李泽宏高巍张金平张波
Owner HANGZHOU SILICON-MAGIC SEMICON TECH CO LTD
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