7results about How to "Improve area utilization" patented technology

The application discloses a 3D heterogeneous chip-based attenuator and an attenuation method thereof. The 3D heterogeneous chip-based attenuator comprises a first radio frequency chip and a second radio frequency chip. The first radio frequency chip is provided with a first radio frequency transmission line for transmitting a radio frequency signal, a first coupling member for coupling radio frequency signal energy and a second coupling member for coupling radio frequency signal energy. The first coupling member is electrically connected with an input end of the first radio frequency transmission line, and the second coupling member is electrically connected with an output end of the first radio frequency transmission line. The second radio frequency chip is provided with a second radio frequency transmission line for receiving the radio frequency signal on the first coupling member and outputting the radio frequency signal to the second coupling member. In the application, the first coupling member and the second coupling member can sequentially couple radio frequency signal energy to realize radio frequency signal energy attenuation, that is, the attenuator does not need to install a resistor on the first radio frequency chip when attenuating radio frequency signal energy, which improves the integration of the 3D heterogeneous chip.

The application discloses a wiring method and device applied to a chip and a storage medium, the chip comprising a plurality of functional modules, the functional module comprising a pin area, wherein the wiring method applied to the chip comprises: grouping processing the plurality of functional modules to determine at least one functional group, each functional group comprising a plurality of adjacent functional modules; and performing wiring processing on the functional group, the wiring processing comprising: determining at least one functional module in the functional group as a to-be-wired unit, the to-be-wired unit further comprising an output area; determining a single-layer wiring corresponding to the to-be-wired unit, the single-layer wiring being connected from the pin area of the to-be-wired unit to the output area. The technical scheme can effectively wire the to-be-wired unit, thereby preventing wiring congestion and improving the area utilization rate of the functional module.

The application provides a trench power device with a back source structure and a preparation method thereof. The preparation method comprises the following steps: forming a P-type body region and an N-type drift region on a surface layer of an N-type substrate; forming a trench, wherein the trench extends from the P-type body region to the N-type substrate; forming a gate dielectric layer on a surface of the trench, and filling a gate layer in the trench; forming an isolation layer, and forming a drain through hole in the isolation layer; performing N-type ion implantation on the drain through hole to form an N-type drain region in the N-type drift region; forming a drain electrode; etching a back surface of the N-type substrate to form a source through hole, wherein the source through hole exposes the P-type body region; and depositing a source electrode on the back surface of the N-type substrate and in the source through hole, wherein the source electrode is connected with the N-type substrate and the P-type body region. The drain electrode and the gate electrode are integrated on the front surface of the device, the trench gate structure is adopted to improve the unit density and the channel control ability, and the source electrode is connected with the P-type body region through the back surface deep groove contact, so that the source contact resistance is effectively reduced, and the heat dissipation capacity is improved.

This invention relates to a compact V-type condenser with a subcooling section, comprising a V-type heat exchanger and a condensing fan mounted above it. The V-type heat exchanger includes a heat exchanger 1 and a heat exchanger 2 arranged symmetrically and inclined. The V-type heat exchanger is divided into a heat exchange section near the condensing fan and a subcooling section away from the condensing fan. The refrigerant is connected through a manifold, which includes an exhaust manifold and a liquid collection manifold located in the heat exchange section, and a subcooling manifold and a return manifold located in the subcooling section. The refrigerant flows from the exhaust manifold through several heat exchange paths into the liquid collection manifold, then into the subcooling manifold, and finally into the return manifold through several more heat exchange paths. The subcooling section further subcools the already liquefied refrigerant. This invention, without increasing the condensing area, improves the internal heat exchange effect of the refrigerant simply by adjusting the refrigerant flow path, effectively increasing the utilization rate of the heat exchanger area, and has significant economic and promotional value.

This invention proposes a multifunctional ceramic packaging substrate and its fabrication method, relating to the field of semiconductor technology. The multifunctional ceramic packaging substrate includes a ceramic core board and a wiring layer; the wiring layer is disposed on the side of the ceramic core board, and multiple chips and multiple passive devices are embedded within the wiring layer, with the chips and passive devices electrically interconnected with the wiring layer. This invention also proposes a fabrication method for the multifunctional ceramic packaging substrate, comprising the following steps: providing a ceramic core board; forming a plurality of interconnect holes through the ceramic core board; embedding corresponding chips and passive devices within the wiring layer; forming a second layer by distributing a plurality of stacked ABF / BT layers outside the first layer, the first and second layers forming an ABF / BT composite layer; distributing a solder resist layer outside the ABF / BT composite layer; and distributing a surface treatment layer outside the solder resist layer. This invention embeds chips and passive devices into the wiring layer, improving circuit reliability and the overall area utilization of the ceramic core board, and reducing signal transmission delay.

The application relates to the technical field of liquid cooling equipment, and particularly provides a high-heat-flow-density spiral heterogeneous pin-finned liquid cooling plate, which comprises a plurality of heat-dissipating pin-fins, an upper cover shell, a bottom of the upper cover shell being provided with a downwardly-opened accommodating cavity, a lower base plate, the lower base plate being combined with the open cover, the plurality of heat-dissipating pin-fins being arranged in the accommodating cavity and fixedly arranged on the lower base plate, and an outer wall of the lower base plate being used for contacting a high-heat-flow-density equipment; wherein the plurality of heat-dissipating pin-fins are all extended upwards from the bottom of the lower base plate by spiral blades; then the heat-dissipating pin-fins in the form of the spiral blades extending upwards from the bottom are arranged on the lower base plate, so that the cooling liquid is fully contacted with the spiral blades when flowing in the cavity, the contact area between the cooling liquid and the heat-dissipating pin-fins is increased, and the heat exchange efficiency is improved. Furthermore, the heterogeneous pin-fins adopting the pin-finned process can cover a larger range of edges and corners, so that the utilization rate of the base plate area is improved.

This disclosure provides a carry compression circuit, a chip, and an electronic device. The carry compression circuit includes a first selection module and a second selection module. The first selection module is used to perform XOR processing on a first input signal and a second input signal to obtain a first XOR result, select a first carry output signal from the first input signal and a third input signal based on the first XOR result, and output it; and determine an intermediate processing result based on the first XOR result and the third input signal and send it to the second selection module. The second selection module is used to perform XOR processing on the intermediate processing result and a fourth input signal to obtain a second XOR result, and determine a second carry output signal and an XOR output signal based on the second XOR result and the carry input signal, and output them. Embodiments of this disclosure can reduce the number of transistors.