83results about How to "Improve area utilization" patented technology

The invention provides a method for determining the optimal installation spacing of a photovoltaic array in combination with geographic parameters, and relates to the technical field of photovoltaic power station measurement and calculation, and the method comprises the steps: obtaining the installation place of the photovoltaic array, and collecting the comprehensive parameters of the installation place; determining a corresponding geographical spacing coefficient; calculating sun position parameters according to the geographic parameters; obtaining an optimal inclination angle of the photovoltaic module according to the terrain parameters; calculating a basic installation interval, calculating a comprehensive correction coefficient according to the comprehensive parameters, and calculating an optimized installation interval according to the basic installation interval and the comprehensive correction coefficient; arranging the photovoltaic array according to the optimized installation spacing, performing shadow distribution simulation and generating capacity analysis in simulation software, and performing fine adjustment on the optimized installation spacing according to a simulation result; and outputting and obtaining the optimal installation spacing until the simulation result meets the requirement. According to the method, accurate calculation and optimal design of the photovoltaic array installation spacing can be realized, so that the land utilization rate and the power generation efficiency of a photovoltaic power station are improved, and finally the maximization of economic benefits is realized.

The invention discloses a low-repetition-frequency spiral microcavity structure and a design method, and belongs to the field of silicon-based integrated photon chips. The low-repetition-frequency spiral microcavity structure comprises a first spiral bent waveguide, a second spiral bent waveguide, an internal connection bent waveguide, an external connection bent waveguide and a bus waveguide. The curvature radius of each point of the internal connection bending waveguide changes along with the length and meets the Euler spiral equation, and the internal connection bending waveguide is used for connecting the starting points of the first spiral bending waveguide and the second spiral bending waveguide. The external connection bending waveguide is used for connecting the end points of the first spiral bending waveguide and the second spiral bending waveguide. The first spiral bent waveguide, the second spiral bent waveguide, the internal connection bent waveguide and the external connection bent waveguide form a closed spiral annular waveguide. A light beam transmitted in the bus waveguide is coupled into the spiral annular waveguide. The invention further discloses a design method of the low-repetition-frequency spiral microcavity structure. According to the invention, loss caused by high-order mode crosstalk and mode mismatch can be reduced, and the area utilization rate of a chip is improved.

The present invention relates to the field of semiconductor technology, and in particular to a gallium oxide diode. The gallium oxide diode comprises a gallium oxide wafer, a cathode electrode, an anode electrode and a P-type semiconductor. The gallium oxide wafer comprises a gallium oxide substrate layer and a gallium oxide epitaxial layer. The P-type semiconductor is n layers, where n is the number of layers and n≥2. The present invention provides a multilayer P-type semiconductor, and one end of the P-type semiconductor forms a PN junction with the gallium oxide epitaxial layer, and the PN junction can compensate for the charge on the depletion side. Through the depletion effect of the PN junction, non-ideal factors such as dangling bonds introduced by etching and fixed charges introduced by etching damage in the gallium oxide diode can be passivated, thereby reducing the resistance degradation caused thereby and improving the stability of the device. At the same time, the other end of the P-type semiconductor is connected to the anode electrode to form an equipotential body, which can promote the depletion of the side PN junction, and can also disperse the high electric field of the device from the original side to the end face, thereby achieving the purpose of reducing the electric field strength of the entire device.

The utility model provides a multi-stage extraction phase splitting device and laminated extraction equipment. The multi-stage extraction phase-splitting device comprises a phase-splitting barrel, a power mechanism and a multi-stage extraction mechanism, the split-phase barrel is provided with a split-phase cavity; the power mechanism is provided with a plurality of output assemblies; the multi-stage extraction mechanism is located in the split-phase cavity and nested with the split-phase barrel, the multi-stage extraction mechanism comprises a first hollow shaft sleeve, a second hollow shaft sleeve and a plurality of extraction barrels which are sequentially nested and relatively rotatably arranged, and each extraction barrel is provided with an extraction mixing cavity and a liquid outlet via hole which are communicated with each other; the extraction mixing cavities of every two adjacent extraction barrels are communicated through corresponding liquid outlet via holes, the extraction mixing cavity of the extraction barrel on the outermost side is communicated with the phase splitting cavity through the corresponding liquid outlet via hole, and the first hollow shaft sleeve and the second hollow shaft sleeve are both communicated with the extraction mixing cavity of the extraction barrel on the innermost side. According to the multi-stage extraction phase-splitting device, the area utilization rate of a plant site is relatively high.

The invention discloses a packaging structure of a half-bridge power module. The packaging structure comprises an insulating heat-conducting plate, a multi-layer circuit board, a plastic packaging body and a bridge arm switch, on the other hand, the invention discloses application of the packaging structure of the half-bridge power module in a vehicle-mounted OBC power converter, a DCDC isolation converter, a non-isolation power converter, a cardiac arrest wake-up device and a circuit module formed by combining multiple half bridges such as ANPC, TNPC and Heric. The invention further discloses a manufacturing method of the packaging structure of the half-bridge power module. The manufacturing method comprises the steps of assembling, arranging the overflow area and synchronously filling and grinding to remove the overflow area. The minimum size and low impedance are achieved through the DBC, flexible pin outgoing and welding are achieved through the PCB, the reliability, safety and heat dissipation of the module are supported through the plastic package body, and the expansion temperature monitoring unit and the decoupling capacitor are supported.

The invention relates to a cantilever beam type capacitance MEMS acceleration sensor. The cantilever beam type capacitance MEMS acceleration sensor comprises an upper wafer layer, a middle wafer layer and a lower wafer layer which are arranged in sequence, the middle wafer layer is used for forming a movable mass block, a fixed electrode and an anchor point; the number of the anchor point is one, the anchor point is located at the first end of the movable mass block, and the anchor point is connected with the first end of the movable mass block through an elastic beam; a differential capacitor group is formed between the movable mass block and the fixed electrode along one or more directions, so that the acceleration in one or more directions can be measured; the upper wafer layer and the lower wafer layer are respectively connected with the middle wafer layer from two sides, and the fixed electrode and the anchor point are connected with the upper wafer layer and / or the lower wafer layer. According to the invention, the requirement of multi-axis detection is met, and the area utilization rate and the working reliability of the movable mass block are improved at the same time.

The invention provides an eDRAM-based high-density near-storage calculation and in-storage calculation hybrid architecture and a calculation method. The architecture comprises an eDRAM near-storage and storage calculation hybrid array, a sensitive amplifier, an ADC circuit, a storage calculation result register, a characteristic value updating drive circuit, a controller, a row decoder and a column decoder. According to the calculation method, the architecture is adopted for calculation. By combining a near memory and an in-memory calculation structure, the characteristics of the near memory and the in-memory calculation structure are fully matched to carry out optimization design on an array structure and a basic unit and complement the independent defects of the two architectures, meanwhile, a deep groove capacitor is adopted to replace a plane capacitor, and the advantages of low power consumption, low time delay, high calculation efficiency, high density and the like are achieved; the bandwidth limitation of a traditional near storage circuit and the process limitation of an in-storage computing circuit are effectively overcome, and the method can be applied to a deep learning accelerator computing core and is particularly suitable for edge end hardware deployment with high requirements for the integration level and the power consumption performance.

The application provides a chip layout method, device and readable storage medium of a multi-project wafer. The chip layout method of the multi-project wafer comprises the following steps: acquiring relevant information, arranging chips in a maximum single exposure area, comparing different chip arrangement schemes, adjusting the chips to longitudinally fill the maximum single exposure area, adjusting the maximum single exposure area to obtain a final chip layout scheme, closely arranging the final chip layout scheme in a first quadrant of the wafer, and completing an overall layout scheme by mirror processing of the chip layout scheme in the first quadrant of the wafer. The method not only optimizes the range of the single exposure area, improves the effective layout area utilization rate, and further improves the overall yield, but also adopts a central symmetric layout, facilitates chip cutting, improves the cutting efficiency, and further reduces the cost.

The present invention provides a heat exchange tube, a heat exchanger and an air conditioner. The heat exchange tube includes: a tube base; an outer rib structure is provided on the outer wall of the tube base, and a flow channel structure is provided on the outer rib structure. The flow channel structure is in a snowflake shape, and the flow channel structure is used to provide a vaporization core required for the evaporation of liquid refrigerant. The present invention provides a heat exchange tube, which solves the problem of uniform distribution of liquid refrigerant in the axial and circumferential directions of a falling film evaporator, improves the area utilization rate of the heat exchange tube, and further improves the heat exchange performance of the falling film evaporator. The snowflake-shaped inter-wing flow channels on the outer surface of the present invention form a series of uniform hole clusters and flow channels through cross gaps, providing a large amount of vaporization cores required for the evaporation of liquid saturated refrigerant, which makes the vaporization core density of the heat exchange tube in the embodiment of the present invention large, and significantly enhances the heat exchange efficiency.

The invention belongs to the field of design of an electrostatic discharge (ESD) protection device of a high-voltage integrated circuit (IC), aims at an improved lateral silicon controlled rectifier (MLSCR), and particularly provides a multi-channel SCR device which is used for ESD protection of the high-voltage integrated circuit and is adjustable in trigger voltage and maintaining voltage, and the multi-channel SCR device can be used for achieving ESD protection of an input / output port (I / O for short) and a power domain. The device comprises two MLSCR structures, has the advantages of being adjustable in trigger voltage and maintaining voltage, high in latch-up resistance, high in robustness and the like, and can be suitable for integrated circuit ESD protection under various high-voltage power supply domains.

The utility model relates to the technical field of amusement equipment, in particular to tower combined amusement equipment which comprises a trampoline, the trampoline comprises jumping cloth, a vertical elastic protection net is arranged on the edge of the jumping cloth, and a plurality of main towers are arranged on the outer side of the elastic protection net. Floors of the main tower are made of elastic woven meshes or hard boards; the side wall of the main tower is formed by weaving a rope net; the main towers are divided into a first main tower, a second main tower and a third main tower, a top floor of the first main tower is communicated with a top opening of the rotary slide, and a bottom opening of the rotary slide is connected to the ground; a climbing net is connected between the bottom floor of the second main tower and the ground; and the bottom floor of the third main tower is communicated with the ground through a spiral stair. The trampoline is combined with various types of main towers, and the multifunctional trampoline has multiple layers of playing spaces, improves the utilization rate of land area, has the functions of sliding, running, jumping and climbing up and down, can provide various different experiences for experiencers, and is good in playability.

The utility model discloses an automobile outside rear-view mirror with mirror surface adjustment and lens folding integrated control, which comprises a mirror main body, a heating plate and a lens, the mirror main body comprises a mirror frame, a heating plate and a lens, the mirror frame comprises a raised upper edge and a back plate arranged in the upper edge, and a clamping block is arranged on the back plate; the heating sheet is fixed on the front surface of the mirror frame through the clamping block; an adhesive layer is arranged on the front surface of the heating sheet; the lenses are adhered to the heating sheets through the adhesive layers, and the upper surfaces of the lenses are 0.3 mm lower than the upper surface of the glasses frame; the integrated motor part comprises a base plate, a motor and a folding protective cover, and the base plate is fixed to the back face of the mirror frame; the base plate, the motor and the folding shield are fixedly connected together through bolts, and the motor is electrically connected with the heating piece and an automobile control unit through a wire harness. And the support assembly is connected with the lower end of the integrated motor part.

The invention discloses a transistor structure, a cascode current mirror and a chip, and belongs to the technical field of integrated circuit chips. The transistor structure comprises at least one transistor unit. The transistor unit comprises a substrate and an active region formed on the substrate. The n grid electrodes are arranged on the active region in the first direction, n is an even number, diffusion regions are defined on the two sides of each grid electrode in the first direction, and the diffusion regions between every two adjacent grid electrodes are continuous; wherein the ith grid electrode is connected with the (ni + 1) th grid electrode, and i = 1, 2,..., n / 2. By sharing the diffusion regions, the area utilization rate is improved, wiring is simplified to reduce parasitic resistance and parasitic capacitance effects, and the layout performance is improved.

The present application provides a semiconductor device and a preparation method thereof, a substrate, the substrate comprising a first region and a second region; a virtual gate pattern and a functional gate pattern, located on the substrate in the second region, the virtual gate pattern being close to the first region, the virtual gate pattern comprising a first partial gate pattern and a second partial gate pattern, the virtual gate pattern and the functional gate pattern both comprising a gate metal layer, the upper surface of the gate metal layer in the first partial gate pattern being lower than the upper surface of the gate metal layer in the second partial gate pattern; a dielectric layer, located on the substrate in the first region, and located on the substrate in the second region between the virtual gate pattern and the first region.

The invention discloses a vehicle storage warehouse area determination method, electronic equipment and a storage medium. The method comprises the following steps: acquiring part list information of to-be-stored parts, and goods allocation size information and area coefficients of a plurality of storage areas in a warehouse; based on the part list information and the goods allocation size information, the storage area of the multiple storage areas is determined, and the storage area is used for determining the occupied area of the to-be-stored part; determining occupied areas of the plurality of storage regions based on the area coefficient and the storage area; carrying out summation operation on the occupied areas of the plurality of storage areas to obtain the area of a vehicle storage warehouse; according to the area of the vehicle storage warehouse, a part scheduling strategy is made, and the part scheduling strategy is used for determining a warehouse-in plan and a warehouse-out plan of the parts. The method solves the technical problems that the utilization rate of the storage warehouse area is low and diversified storage requirements of parts cannot be met due to the determination method of the vehicle storage warehouse area in the prior art.

The application discloses a 3D heterogeneous chip-based attenuator and an attenuation method thereof. The 3D heterogeneous chip-based attenuator comprises a first radio frequency chip and a second radio frequency chip. The first radio frequency chip is provided with a first radio frequency transmission line for transmitting a radio frequency signal, a first coupling member for coupling radio frequency signal energy and a second coupling member for coupling radio frequency signal energy. The first coupling member is electrically connected with an input end of the first radio frequency transmission line, and the second coupling member is electrically connected with an output end of the first radio frequency transmission line. The second radio frequency chip is provided with a second radio frequency transmission line for receiving the radio frequency signal on the first coupling member and outputting the radio frequency signal to the second coupling member. In the application, the first coupling member and the second coupling member can sequentially couple radio frequency signal energy to realize radio frequency signal energy attenuation, that is, the attenuator does not need to install a resistor on the first radio frequency chip when attenuating radio frequency signal energy, which improves the integration of the 3D heterogeneous chip.

The invention relates to the field of storage, in particular to a hybrid cache architecture and a cache data management method and system.The hybrid cache architecture comprises a plurality of cache sets, each cache set comprises M SRAM storage spaces and N STT-RAM storage spaces, SRAMs are used for cache data writing, and STT-RAMs are used for maintaining data content in caches; each storage space of the STT-RAM has two states: an activation state and a deactivation state. According to the cache data management method, a counting register and a threshold value T1 are set based on a hybrid cache architecture, self-adaptive tag comparison is carried out during data reading, the self-adaptive tag comparison greatly compresses an exploration space, only a cache path of an STT-RAM in an activated state participates in tag comparison, and the operation speed is increased. According to the method, the area utilization rate can be increased, the overall power consumption is reduced, the tag comparison exploration space is reduced, and the power consumption and delay in the tag comparison process are remarkably reduced while the performance is ensured.

The utility model relates to an arrangement structure of an anti-shading short lead assembly, which is characterized in that a plurality of battery pieces are welded in series to form a battery piece string, a plurality of rows of battery piece strings are connected in parallel through interconnection strips, the battery piece strings connected in parallel are welded on a bus bar to form a parallel battery piece group, and a plurality of parallel battery piece groups are connected in series to form the anti-shading short lead assembly. A positive junction box is arranged at the positive output end of the battery piece rectangular array, a negative junction box is arranged at the negative output end of the battery piece rectangular array, diodes in the positive junction box and the negative junction box are connected with battery piece sets at the two ends in parallel, an intermediate junction box is assembled on a middle battery piece, and diodes in the intermediate junction box are connected with a middle battery piece set in parallel. And the formed assembly is arranged in the frame body, so that a complete arrangement structure of the short lead assembly is formed. According to the utility model, the influence of shading can be reduced, more power is generated compared with a traditional assembly, and intervals among arrays are reduced, so that the installed capacity is improved under the same area, the area utilization rate is improved, and the maximum generating capacity is obtained.

A semiconductor array structure includes: a substrate; a semiconductor device includes a substrate, a plurality of field effect transistors (FETs) arranged in a row and located on the substrate, each FET including a first source-drain region, a second source-drain region, at least one channel coupling the source-drain regions, and a gate adjacent the at least one channel. A plurality of front side signal lines on a front side of the FETs; a plurality of backside power rails on a backside of the FETs; a plurality of backside signal conductors are on the backside. A front side signal connection extends from the front side signal conductor to the first source-drain region; a power connection extends from the backside power rail to the second source-drain region; and a backside gate contact connection extends from the backside signal conductor to the gate. The backside gate contact connections each have a bottom dimension greater than the gate length.

The micro-power DCDC converter comprises a transformer, the transformer comprises a magnetic core and two windings, the magnetic core is of a square ring structure and is integrally formed by ferrite materials, and four side columns are formed; and the two windings are respectively wound on the two side columns of the magnetic core to form non-crossed and overlapped layout positioning of the two windings. Compared with the prior art, according to the scheme, the utilization rate of the window area of the magnetic core can be increased, the overall size of a high-isolation product can be reduced, the consistency of isolation voltage resistance, isolation capacitance and leakage inductance can be better, and the magnetic core is suitable for mechanical winding of a large-wire-diameter winding and particularly suitable for a micro-power product with the high isolation voltage resistance requirement.

An adapter power supply includes a circuit board, a power factor correction transistor, a bridge rectifier, a power factor correction inductor, a capacitor and a transformer. The circuit board has a first long side and a second long side parallel to each other. The power factor correction transistor is arranged on the circuit board and is close to the first long side. The bridge rectifier is arranged on the circuit board and is close to the second long side. The power factor correction inductor is arranged on the circuit board and has a first long axis. The first long axis is parallel to the first long side. The capacitor and the power factor correction inductor are arranged side by side on the circuit board along the width direction of the circuit board. The capacitor has a second long axis. The first long axis of the power factor correction inductor is parallel to the second long axis of the capacitor. The transformer is arranged on the circuit board and is located next to the power factor correction inductor and the capacitor.

The present invention discloses a three-dimensional flash memory and its array layout structure. The three-dimensional flash memory includes a gate stack structure, an annular channel column, a first source / drain column, a second source / drain column and a charge storage structure. The gate stack structure is arranged on a dielectric substrate and includes a plurality of gate layers electrically insulated from each other. The annular channel column is arranged on the dielectric substrate and penetrates the gate stack structure. The first source / drain column and the second source / drain column are arranged on the dielectric substrate and are located in the channel column and penetrate the gate stack structure, wherein the first source / drain column and the second source / drain column are separated from each other and are respectively connected to the channel column. The charge storage structure is arranged between each of the plurality of gate layers and the channel column.

The utility model relates to a composite material frame pultrusion layout device which comprises a yarn guide assembly, a yarn guide assembly and a yarn guide assembly, the yarn guide assembly comprises a sliding plate which is movably arranged, a yarn guide plate fixed to the top of the sliding plate and yarn guide holes formed in the yarn guide plate in an array mode; the forming assembly is arranged on one side of the yarn guide assembly and used for forming the composite material frame, and the forming assembly comprises a first forming mold and a second forming mold; according to the composite material frame pultrusion layout equipment disclosed by the utility model, the traction mechanism is arranged to pull the composite material frame formed by the forming assembly, so that mold blockage or incomplete curing of a product is avoided; meanwhile, downward bending deformation of the thermal-state profile under the gravity is avoided, and the precision of a finished product is improved; and by arranging the supporting frames with the adjustable intervals, the composite material frames with different heights are pulled, and the universality of the equipment is improved.

The utility model relates to an electric furnace feeding device and belongs to the field of material transportation. A waste steel conveying device (1), a rear section conveying device (2), a connecting conveying device (4) and an automobile material receiving groove (5) are sequentially arranged in the waste steel conveying direction. At least two electric furnace modules are arranged at the rear section conveying equipment (2) in parallel, the electric furnace modules are connected to an electric furnace feeding conveyor (3) through a material distributing device (9), and the electric furnace feeding conveyor (3) is used for conveying waste steel into an electric furnace; and the material distributing device (9) is used for distributing materials to the electric furnace according to the matched electric furnace requirements. According to the scheme, the relative position of the electric furnace main workshop and the steel scrap yard is not limited, the site utilization rate and flexibility are effectively improved, the logistics pressure in the factory can be effectively relieved, the logistics efficiency is improved, and the intermediate transfer and logistics cost is reduced.

The application discloses a wiring method and device applied to a chip and a storage medium, the chip comprising a plurality of functional modules, the functional module comprising a pin area, wherein the wiring method applied to the chip comprises: grouping processing the plurality of functional modules to determine at least one functional group, each functional group comprising a plurality of adjacent functional modules; and performing wiring processing on the functional group, the wiring processing comprising: determining at least one functional module in the functional group as a to-be-wired unit, the to-be-wired unit further comprising an output area; determining a single-layer wiring corresponding to the to-be-wired unit, the single-layer wiring being connected from the pin area of the to-be-wired unit to the output area. The technical scheme can effectively wire the to-be-wired unit, thereby preventing wiring congestion and improving the area utilization rate of the functional module.

The application provides a trench power device with a back source structure and a preparation method thereof. The preparation method comprises the following steps: forming a P-type body region and an N-type drift region on a surface layer of an N-type substrate; forming a trench, wherein the trench extends from the P-type body region to the N-type substrate; forming a gate dielectric layer on a surface of the trench, and filling a gate layer in the trench; forming an isolation layer, and forming a drain through hole in the isolation layer; performing N-type ion implantation on the drain through hole to form an N-type drain region in the N-type drift region; forming a drain electrode; etching a back surface of the N-type substrate to form a source through hole, wherein the source through hole exposes the P-type body region; and depositing a source electrode on the back surface of the N-type substrate and in the source through hole, wherein the source electrode is connected with the N-type substrate and the P-type body region. The drain electrode and the gate electrode are integrated on the front surface of the device, the trench gate structure is adopted to improve the unit density and the channel control ability, and the source electrode is connected with the P-type body region through the back surface deep groove contact, so that the source contact resistance is effectively reduced, and the heat dissipation capacity is improved.

The embodiment of the invention provides a photovoltaic system, which comprises at least one photovoltaic module string group, the photovoltaic module string group comprises two columns of photovoltaic module strings arranged along a first direction, and each column of photovoltaic module string comprises a plurality of photovoltaic modules arranged along a second direction; the photovoltaic module comprises a body, a first cable and a second cable, wherein the first cable and the second cable are arranged on the back face of the body and are opposite in polarity. In two photovoltaic modules positioned at one end of the photovoltaic module string group along the second direction, the first cable of one photovoltaic module and the second cable of the other photovoltaic module extend towards the inner side of the photovoltaic module string group along the first direction and are electrically connected; all the rest first cables and all the rest second cables in the photovoltaic module string group extend towards the outer side of the photovoltaic module string group along the first direction; any two adjacent photovoltaic modules in the same column of photovoltaic module strings are electrically connected through a first cable and a second cable. The space between the photovoltaic modules can be reduced, and the generating capacity of the photovoltaic system is improved.

The invention discloses a flexible pressure circular array sensor for a finger-wearing pulse instrument and a preparation method thereof, the flexible pressure circular array sensor is arranged on a finger stall of the pulse instrument, the flexible pressure circular array sensor comprises a flexible substrate, the flexible substrate is provided with a plurality of fan-shaped interdigital electrodes, and the fan-shaped interdigital electrodes are arranged on the flexible substrate. The fan-shaped interdigital electrodes are arranged at equal intervals from the circle point to the circumference of the circle, and the circle is divided into 3-10 equal parts; and a fan-shaped piezoresistive sensitive layer and a pressure-sensitive substrate film layer are sequentially arranged on the fan-shaped interdigital electrode. According to the invention, a sensor array design is adopted, wherein a flexible pressure sensor array unit is designed into a sector shape. The original point of each fan-shaped sensor unit is located at the center position of the finger pulp of the fingerstall of the pulse instrument, so that all array units can be synchronously sampled, the risk that pulse signals cannot be measured due to failure of a single-point sensor is reduced, and the measurement reliability is improved.

The application discloses a microwave network assisted arbitrary-tap T-coil automatic synthesis method, comprising the following steps: firstly, using a microwave network to obtain the limit performance and the optimal topological structure of a circuit under the action of non-ideal factors; then, using the microwave network to consider the change range of the optimal inductance value when the quality factor and the coupling coefficient of the T-coil change in a reasonable range and to take the change range as an optimization area; then, according to the set index and process, combining the extended Wheeler formula and Latin hypercube sampling to obtain initial samples; then, using a Gaussian process regression to establish a proxy model of the concerned index and the parameters; finally, performing global optimization through a multi-path global optimization algorithm to obtain a target T-coil layout. It is verified that the method can efficiently synthesize the optimal T-coil.

The invention provides an inductor, a circuit board integrated inductor, charging equipment and electronic equipment. The inductor comprises a magnetic core, the magnetic core is provided with a plurality of first through holes and a plurality of second through holes, the first through holes are sequentially arranged at intervals in the first direction, the second through holes are sequentially arranged at intervals in the first direction, and the first through holes and the second through holes are arranged at intervals in the second direction; when the thickness of the magnetic core is 0.3 mm to 0.5 mm, the range of collapse pressure F is larger than or equal to 200 N, and the first direction intersects with the second direction; the coil sequentially and alternately penetrates through the first through hole and the second through hole and is wound on the magnetic core, and the coil and the magnetic core are arranged in an insulated mode. According to the inductor provided by the embodiment of the invention, under the condition of a certain size, the proportion of the magnetic core can be increased, so that the inductor has relatively high inductance value and relatively high collapse pressure.