35results about How to "Improve area utilization" patented technology

The invention provides a method for determining the optimal installation spacing of a photovoltaic array in combination with geographic parameters, and relates to the technical field of photovoltaic power station measurement and calculation, and the method comprises the steps: obtaining the installation place of the photovoltaic array, and collecting the comprehensive parameters of the installation place; determining a corresponding geographical spacing coefficient; calculating sun position parameters according to the geographic parameters; obtaining an optimal inclination angle of the photovoltaic module according to the terrain parameters; calculating a basic installation interval, calculating a comprehensive correction coefficient according to the comprehensive parameters, and calculating an optimized installation interval according to the basic installation interval and the comprehensive correction coefficient; arranging the photovoltaic array according to the optimized installation spacing, performing shadow distribution simulation and generating capacity analysis in simulation software, and performing fine adjustment on the optimized installation spacing according to a simulation result; and outputting and obtaining the optimal installation spacing until the simulation result meets the requirement. According to the method, accurate calculation and optimal design of the photovoltaic array installation spacing can be realized, so that the land utilization rate and the power generation efficiency of a photovoltaic power station are improved, and finally the maximization of economic benefits is realized.

The invention discloses a low-repetition-frequency spiral microcavity structure and a design method, and belongs to the field of silicon-based integrated photon chips. The low-repetition-frequency spiral microcavity structure comprises a first spiral bent waveguide, a second spiral bent waveguide, an internal connection bent waveguide, an external connection bent waveguide and a bus waveguide. The curvature radius of each point of the internal connection bending waveguide changes along with the length and meets the Euler spiral equation, and the internal connection bending waveguide is used for connecting the starting points of the first spiral bending waveguide and the second spiral bending waveguide. The external connection bending waveguide is used for connecting the end points of the first spiral bending waveguide and the second spiral bending waveguide. The first spiral bent waveguide, the second spiral bent waveguide, the internal connection bent waveguide and the external connection bent waveguide form a closed spiral annular waveguide. A light beam transmitted in the bus waveguide is coupled into the spiral annular waveguide. The invention further discloses a design method of the low-repetition-frequency spiral microcavity structure. According to the invention, loss caused by high-order mode crosstalk and mode mismatch can be reduced, and the area utilization rate of a chip is improved.

The invention discloses a packaging structure of a half-bridge power module. The packaging structure comprises an insulating heat-conducting plate, a multi-layer circuit board, a plastic packaging body and a bridge arm switch, on the other hand, the invention discloses application of the packaging structure of the half-bridge power module in a vehicle-mounted OBC power converter, a DCDC isolation converter, a non-isolation power converter, a cardiac arrest wake-up device and a circuit module formed by combining multiple half bridges such as ANPC, TNPC and Heric. The invention further discloses a manufacturing method of the packaging structure of the half-bridge power module. The manufacturing method comprises the steps of assembling, arranging the overflow area and synchronously filling and grinding to remove the overflow area. The minimum size and low impedance are achieved through the DBC, flexible pin outgoing and welding are achieved through the PCB, the reliability, safety and heat dissipation of the module are supported through the plastic package body, and the expansion temperature monitoring unit and the decoupling capacitor are supported.

The invention relates to a cantilever beam type capacitance MEMS acceleration sensor. The cantilever beam type capacitance MEMS acceleration sensor comprises an upper wafer layer, a middle wafer layer and a lower wafer layer which are arranged in sequence, the middle wafer layer is used for forming a movable mass block, a fixed electrode and an anchor point; the number of the anchor point is one, the anchor point is located at the first end of the movable mass block, and the anchor point is connected with the first end of the movable mass block through an elastic beam; a differential capacitor group is formed between the movable mass block and the fixed electrode along one or more directions, so that the acceleration in one or more directions can be measured; the upper wafer layer and the lower wafer layer are respectively connected with the middle wafer layer from two sides, and the fixed electrode and the anchor point are connected with the upper wafer layer and / or the lower wafer layer. According to the invention, the requirement of multi-axis detection is met, and the area utilization rate and the working reliability of the movable mass block are improved at the same time.

The application provides a chip layout method, device and readable storage medium of a multi-project wafer. The chip layout method of the multi-project wafer comprises the following steps: acquiring relevant information, arranging chips in a maximum single exposure area, comparing different chip arrangement schemes, adjusting the chips to longitudinally fill the maximum single exposure area, adjusting the maximum single exposure area to obtain a final chip layout scheme, closely arranging the final chip layout scheme in a first quadrant of the wafer, and completing an overall layout scheme by mirror processing of the chip layout scheme in the first quadrant of the wafer. The method not only optimizes the range of the single exposure area, improves the effective layout area utilization rate, and further improves the overall yield, but also adopts a central symmetric layout, facilitates chip cutting, improves the cutting efficiency, and further reduces the cost.

The utility model discloses an automobile outside rear-view mirror with mirror surface adjustment and lens folding integrated control, which comprises a mirror main body, a heating plate and a lens, the mirror main body comprises a mirror frame, a heating plate and a lens, the mirror frame comprises a raised upper edge and a back plate arranged in the upper edge, and a clamping block is arranged on the back plate; the heating sheet is fixed on the front surface of the mirror frame through the clamping block; an adhesive layer is arranged on the front surface of the heating sheet; the lenses are adhered to the heating sheets through the adhesive layers, and the upper surfaces of the lenses are 0.3 mm lower than the upper surface of the glasses frame; the integrated motor part comprises a base plate, a motor and a folding protective cover, and the base plate is fixed to the back face of the mirror frame; the base plate, the motor and the folding shield are fixedly connected together through bolts, and the motor is electrically connected with the heating piece and an automobile control unit through a wire harness. And the support assembly is connected with the lower end of the integrated motor part.

The invention discloses a transistor structure, a cascode current mirror and a chip, and belongs to the technical field of integrated circuit chips. The transistor structure comprises at least one transistor unit. The transistor unit comprises a substrate and an active region formed on the substrate. The n grid electrodes are arranged on the active region in the first direction, n is an even number, diffusion regions are defined on the two sides of each grid electrode in the first direction, and the diffusion regions between every two adjacent grid electrodes are continuous; wherein the ith grid electrode is connected with the (ni + 1) th grid electrode, and i = 1, 2,..., n / 2. By sharing the diffusion regions, the area utilization rate is improved, wiring is simplified to reduce parasitic resistance and parasitic capacitance effects, and the layout performance is improved.

The application discloses a 3D heterogeneous chip-based attenuator and an attenuation method thereof. The 3D heterogeneous chip-based attenuator comprises a first radio frequency chip and a second radio frequency chip. The first radio frequency chip is provided with a first radio frequency transmission line for transmitting a radio frequency signal, a first coupling member for coupling radio frequency signal energy and a second coupling member for coupling radio frequency signal energy. The first coupling member is electrically connected with an input end of the first radio frequency transmission line, and the second coupling member is electrically connected with an output end of the first radio frequency transmission line. The second radio frequency chip is provided with a second radio frequency transmission line for receiving the radio frequency signal on the first coupling member and outputting the radio frequency signal to the second coupling member. In the application, the first coupling member and the second coupling member can sequentially couple radio frequency signal energy to realize radio frequency signal energy attenuation, that is, the attenuator does not need to install a resistor on the first radio frequency chip when attenuating radio frequency signal energy, which improves the integration of the 3D heterogeneous chip.

The invention relates to the field of storage, in particular to a hybrid cache architecture and a cache data management method and system.The hybrid cache architecture comprises a plurality of cache sets, each cache set comprises M SRAM storage spaces and N STT-RAM storage spaces, SRAMs are used for cache data writing, and STT-RAMs are used for maintaining data content in caches; each storage space of the STT-RAM has two states: an activation state and a deactivation state. According to the cache data management method, a counting register and a threshold value T1 are set based on a hybrid cache architecture, self-adaptive tag comparison is carried out during data reading, the self-adaptive tag comparison greatly compresses an exploration space, only a cache path of an STT-RAM in an activated state participates in tag comparison, and the operation speed is increased. According to the method, the area utilization rate can be increased, the overall power consumption is reduced, the tag comparison exploration space is reduced, and the power consumption and delay in the tag comparison process are remarkably reduced while the performance is ensured.

The micro-power DCDC converter comprises a transformer, the transformer comprises a magnetic core and two windings, the magnetic core is of a square ring structure and is integrally formed by ferrite materials, and four side columns are formed; and the two windings are respectively wound on the two side columns of the magnetic core to form non-crossed and overlapped layout positioning of the two windings. Compared with the prior art, according to the scheme, the utilization rate of the window area of the magnetic core can be increased, the overall size of a high-isolation product can be reduced, the consistency of isolation voltage resistance, isolation capacitance and leakage inductance can be better, and the magnetic core is suitable for mechanical winding of a large-wire-diameter winding and particularly suitable for a micro-power product with the high isolation voltage resistance requirement.

The utility model relates to an electric furnace feeding device and belongs to the field of material transportation. A waste steel conveying device (1), a rear section conveying device (2), a connecting conveying device (4) and an automobile material receiving groove (5) are sequentially arranged in the waste steel conveying direction. At least two electric furnace modules are arranged at the rear section conveying equipment (2) in parallel, the electric furnace modules are connected to an electric furnace feeding conveyor (3) through a material distributing device (9), and the electric furnace feeding conveyor (3) is used for conveying waste steel into an electric furnace; and the material distributing device (9) is used for distributing materials to the electric furnace according to the matched electric furnace requirements. According to the scheme, the relative position of the electric furnace main workshop and the steel scrap yard is not limited, the site utilization rate and flexibility are effectively improved, the logistics pressure in the factory can be effectively relieved, the logistics efficiency is improved, and the intermediate transfer and logistics cost is reduced.

The application discloses a wiring method and device applied to a chip and a storage medium, the chip comprising a plurality of functional modules, the functional module comprising a pin area, wherein the wiring method applied to the chip comprises: grouping processing the plurality of functional modules to determine at least one functional group, each functional group comprising a plurality of adjacent functional modules; and performing wiring processing on the functional group, the wiring processing comprising: determining at least one functional module in the functional group as a to-be-wired unit, the to-be-wired unit further comprising an output area; determining a single-layer wiring corresponding to the to-be-wired unit, the single-layer wiring being connected from the pin area of the to-be-wired unit to the output area. The technical scheme can effectively wire the to-be-wired unit, thereby preventing wiring congestion and improving the area utilization rate of the functional module.

The application provides a trench power device with a back source structure and a preparation method thereof. The preparation method comprises the following steps: forming a P-type body region and an N-type drift region on a surface layer of an N-type substrate; forming a trench, wherein the trench extends from the P-type body region to the N-type substrate; forming a gate dielectric layer on a surface of the trench, and filling a gate layer in the trench; forming an isolation layer, and forming a drain through hole in the isolation layer; performing N-type ion implantation on the drain through hole to form an N-type drain region in the N-type drift region; forming a drain electrode; etching a back surface of the N-type substrate to form a source through hole, wherein the source through hole exposes the P-type body region; and depositing a source electrode on the back surface of the N-type substrate and in the source through hole, wherein the source electrode is connected with the N-type substrate and the P-type body region. The drain electrode and the gate electrode are integrated on the front surface of the device, the trench gate structure is adopted to improve the unit density and the channel control ability, and the source electrode is connected with the P-type body region through the back surface deep groove contact, so that the source contact resistance is effectively reduced, and the heat dissipation capacity is improved.

The embodiment of the invention provides a photovoltaic system, which comprises at least one photovoltaic module string group, the photovoltaic module string group comprises two columns of photovoltaic module strings arranged along a first direction, and each column of photovoltaic module string comprises a plurality of photovoltaic modules arranged along a second direction; the photovoltaic module comprises a body, a first cable and a second cable, wherein the first cable and the second cable are arranged on the back face of the body and are opposite in polarity. In two photovoltaic modules positioned at one end of the photovoltaic module string group along the second direction, the first cable of one photovoltaic module and the second cable of the other photovoltaic module extend towards the inner side of the photovoltaic module string group along the first direction and are electrically connected; all the rest first cables and all the rest second cables in the photovoltaic module string group extend towards the outer side of the photovoltaic module string group along the first direction; any two adjacent photovoltaic modules in the same column of photovoltaic module strings are electrically connected through a first cable and a second cable. The space between the photovoltaic modules can be reduced, and the generating capacity of the photovoltaic system is improved.

The invention discloses a flexible pressure circular array sensor for a finger-wearing pulse instrument and a preparation method thereof, the flexible pressure circular array sensor is arranged on a finger stall of the pulse instrument, the flexible pressure circular array sensor comprises a flexible substrate, the flexible substrate is provided with a plurality of fan-shaped interdigital electrodes, and the fan-shaped interdigital electrodes are arranged on the flexible substrate. The fan-shaped interdigital electrodes are arranged at equal intervals from the circle point to the circumference of the circle, and the circle is divided into 3-10 equal parts; and a fan-shaped piezoresistive sensitive layer and a pressure-sensitive substrate film layer are sequentially arranged on the fan-shaped interdigital electrode. According to the invention, a sensor array design is adopted, wherein a flexible pressure sensor array unit is designed into a sector shape. The original point of each fan-shaped sensor unit is located at the center position of the finger pulp of the fingerstall of the pulse instrument, so that all array units can be synchronously sampled, the risk that pulse signals cannot be measured due to failure of a single-point sensor is reduced, and the measurement reliability is improved.

The application discloses a microwave network assisted arbitrary-tap T-coil automatic synthesis method, comprising the following steps: firstly, using a microwave network to obtain the limit performance and the optimal topological structure of a circuit under the action of non-ideal factors; then, using the microwave network to consider the change range of the optimal inductance value when the quality factor and the coupling coefficient of the T-coil change in a reasonable range and to take the change range as an optimization area; then, according to the set index and process, combining the extended Wheeler formula and Latin hypercube sampling to obtain initial samples; then, using a Gaussian process regression to establish a proxy model of the concerned index and the parameters; finally, performing global optimization through a multi-path global optimization algorithm to obtain a target T-coil layout. It is verified that the method can efficiently synthesize the optimal T-coil.

A guide pipe device of a chute tube riprap system comprises a guide pipe, the top of the guide pipe is communicated with a stone supply device, the bottom of the guide pipe is provided with a discharge port, a movable bottom plate is hinged to the discharge port, a push rod is fixed to the bottom of the movable bottom plate, and the push rod pushes the movable bottom plate to rotate in the discharge port to adjust the size of the discharge port and the stone throwing direction. The push rod communicates with a remote control unit which communicates with the monitoring module. The movable bottom plate is pushed by the push rod to rotate, so that the size of the discharge port, the stone throwing direction and the falling position and speed of the stone are adjusted, the utilization rate of the discharge port area of the guide pipe device is improved, the throwing and filling range is enlarged, and the frequency of moving the guide pipe device and the workload of later supplementary throwing or leveling are reduced; the remote control unit enables operation to be convenient, and working efficiency is improved; the device is simple in structure, convenient to operate, uniform in throwing and filling, suitable for riprap treatment work of the ocean wind turbine foundation, high in practical application value and good in economic benefit.

The invention discloses an addressable ring oscillator test circuit. The circuit comprises an addressing circuit, a switching circuit, an excitation circuit, a test RO unit group and a frequency dividing circuit. Wherein the test RO unit group comprises a plurality of test RO units, the addressing circuit comprises a column addressing circuit and a row addressing circuit, the column addressing circuit and the row addressing circuit are respectively connected to the test RO unit group through the switching circuit, and the test RO units in the test RO unit group are gated through addresses. And the output end of each test RO unit is connected with a corresponding frequency divider in the frequency dividing circuit. The test circuit further comprises a sensing circuit connected to the test RO unit group. The test RO unit is composed of a NAND gate, a plurality of phase inverters and a driver, and the NAND gate and the plurality of phase inverters are connected end to end and input to the driver.

This invention relates to a compact V-type condenser with a subcooling section, comprising a V-type heat exchanger and a condensing fan mounted above it. The V-type heat exchanger includes a heat exchanger 1 and a heat exchanger 2 arranged symmetrically and inclined. The V-type heat exchanger is divided into a heat exchange section near the condensing fan and a subcooling section away from the condensing fan. The refrigerant is connected through a manifold, which includes an exhaust manifold and a liquid collection manifold located in the heat exchange section, and a subcooling manifold and a return manifold located in the subcooling section. The refrigerant flows from the exhaust manifold through several heat exchange paths into the liquid collection manifold, then into the subcooling manifold, and finally into the return manifold through several more heat exchange paths. The subcooling section further subcools the already liquefied refrigerant. This invention, without increasing the condensing area, improves the internal heat exchange effect of the refrigerant simply by adjusting the refrigerant flow path, effectively increasing the utilization rate of the heat exchanger area, and has significant economic and promotional value.

The utility model discloses an integrated bidirectional switch MOSFET which comprises a first groove group and a second groove group which are symmetrically arranged along the horizontal central axis of an N-epitaxial layer, the first groove group and the second groove group respectively comprise a plurality of same strip-shaped grooves, gate oxide layers grow in the strip-shaped grooves, gate polycrystals are deposited in the gate oxide layers, and the gate polycrystals are deposited in the strip-shaped grooves. The grid polycrystals in the strip-shaped grooves in the first groove group form a first grid of the MOSFET, and the grid polycrystals in the strip-shaped grooves in the second groove group form a second grid of the MOSFET; a first P well layer is formed at the upper part of the N-epitaxial layer outside the first groove group, and a second P well layer is formed at the upper part of the N-epitaxial layer in the second groove group; a first N + active layer is formed at the upper part of the first P well layer, and the first N + active layer is in short circuit with the grid polycrystal in the first groove group to form a first source electrode of the MOSFET; a second N + active layer is formed on the lower portion of the second P well layer, the second N + active layer and the grid polycrystal in the second groove group are in short circuit to form a second source electrode of the MOSFET, and the first source electrode and the second source electrode form a bidirectional switch of the MOSFET.

The invention provides a three-dimensional storage and near storage computing architecture which can be applied to the technical field of circuit design. The three-dimensional storage and near-storage computing architecture comprises a control layer, which comprises a gating module and a driving module; the plurality of storage layers are stacked on the surface of the control layer, and each storage layer comprises a plurality of storage units; wherein the gating module is used for controlling a target storage layer in the plurality of storage layers to be in a working state under the control of a gating signal; and the driving module is used for controlling the target storage unit in the target storage layer to execute read-write operation.

This utility model discloses a three-phase high power density PCB stator winding structure and its motor and miniature fan. Each layer of the PCB coil board in the three-phase high power density PCB stator winding structure is symmetrically divided into six coil regions, each with a 2D printed coil forming six windings. Windings in the same numbered coil region on different layers are connected in series via internal or external interlayer vias to form windings U1, V1, W1, U2, V2, and W2. Two windings 180° apart mechanically constitute one phase. Since the windings are roughly the same shape, the problem of large electromagnetic torque fluctuations is effectively solved, improving the motor's operational stability. Furthermore, the 2D printed coils are spirally wound, resulting in a compact layout, high coil density, and effectively improved area utilization and increased power. Applying this three-phase high power density PCB stator winding structure to motors or miniature fans makes the overall structure more compact and thinner.

The photovoltaic module comprises a first battery piece and a second battery piece which are arranged in the first direction, the first battery piece and the second battery piece are each provided with a front face and a back face which are arranged in a back-to-back mode, and the first battery piece and the second battery piece are each provided with a first welding strip located on the front face and a second welding strip located on the back face; and a bus bar; wherein the bus bar comprises a first part and a second part which are connected along a first direction, and the first part is positioned on one side, far away from the front surface, of the back surface of the first battery piece and is electrically connected with the second welding strip of the first battery piece; one part of the second part is positioned on one side of the back of the second battery piece far away from the front, and the other part of the second part is positioned on one side of the front of the second battery piece far away from the back and electrically connected with the first welding strip of the second battery piece. The area utilization rate and the module power of the photovoltaic module can be improved.

The invention provides a semiconductor device, a manufacturing method thereof and a memory system. The semiconductor device comprises a first semiconductor structure with a peripheral circuit, wherein the first semiconductor structure comprises a substrate, a first dielectric stack layer, a second dielectric stack layer and a conductive column; wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, and a first device structure is formed on the first surface; the first dielectric stack layer is located on the first surface, an interconnection structure is arranged in the first dielectric stack layer, and the first dielectric stack layer is located on the side, away from the substrate, of the first device structure and connected with the first device structure; the second dielectric stack layer is located on the second surface, and a first bonding pad structure is arranged in the second dielectric stack layer and is exposed on the surface, away from the substrate, of the second dielectric stack layer; the conductive pillar extends in a direction perpendicular to the first face and penetrates through the substrate, one end of the conductive pillar extends to the first dielectric stack layer and is connected to the interconnection structure, and the other end of the conductive pillar extends to the second dielectric stack layer and is connected to the first pad structure.

This invention discloses an arithmetic logic circuit suitable for balanced ternary systems, comprising a unary balanced ternary operation circuit, a balanced ternary half-adder circuit, a balanced ternary full-adder circuit, and a balanced ternary multiplier circuit. Single-input logic conversion is achieved through the combination of polarized ternary inverters and transistors. The half-adder consists of a basic unit and a transmission gate, realizing two-bit summation and carry output. The full-adder employs two cascaded half-adders and optimizes the carry path, significantly shortening the critical path and reducing the number of transistors. The multiplier uses the basic unit as the control core and combines it with a standard ternary inverter to achieve accurate multiplication. This invention overcomes the interconnection bottleneck of traditional binary logic, avoids the high hardware overhead of unbalanced ternary logic circuits in signed number calculations, and avoids the accuracy loss of approximate calculations in existing balanced ternary logic circuits. It has advantages such as simplified structure, low latency, low power consumption, and accurate operation, and is suitable for high-performance computing scenarios such as artificial intelligence, big data, and very large-scale integrated circuits.

According to the wafer-level radio frequency integrated circuit structure and the preparation method thereof, the acoustic wave filter and other functional devices are integrated on the same wafer at the same time, miniaturization of a radio frequency front-end module is achieved, the area utilization rate of a chip is greatly increased, the requirement of a mobile terminal for the device size is met, and the manufacturing cost is reduced. Electrical connection among different devices is achieved through the metal interconnection lines in the chip, compared with a traditional packaging mode that a ceramic substrate and an organic substrate are used for electrical interconnection, the interconnection distance is greatly shortened, signal loss and delay caused by parasitic inductance, capacitance and resistance are effectively reduced, and the reliability of the chip is improved. Compared with a traditional substrate interconnection packaging technology, the manufacturing method of the radio frequency front-end module is simple and can be compatible with a standard technology such as a silicon-based CMOS technology, so that the area utilization rate of a chip is increased, and the production cost is reduced.

This invention proposes a multifunctional ceramic packaging substrate and its fabrication method, relating to the field of semiconductor technology. The multifunctional ceramic packaging substrate includes a ceramic core board and a wiring layer; the wiring layer is disposed on the side of the ceramic core board, and multiple chips and multiple passive devices are embedded within the wiring layer, with the chips and passive devices electrically interconnected with the wiring layer. This invention also proposes a fabrication method for the multifunctional ceramic packaging substrate, comprising the following steps: providing a ceramic core board; forming a plurality of interconnect holes through the ceramic core board; embedding corresponding chips and passive devices within the wiring layer; forming a second layer by distributing a plurality of stacked ABF / BT layers outside the first layer, the first and second layers forming an ABF / BT composite layer; distributing a solder resist layer outside the ABF / BT composite layer; and distributing a surface treatment layer outside the solder resist layer. This invention embeds chips and passive devices into the wiring layer, improving circuit reliability and the overall area utilization of the ceramic core board, and reducing signal transmission delay.

The invention provides a non-volatile memory-SRAM (Static Random Access Memory) data transfer unit, a heterogeneous integrated storage system and a chip system. The non-volatile memory-SRAM data transfer unit comprises a non-volatile memory-SRAM (Static Random Access Memory) data transfer unit, the M * N nonvolatile storage units are arranged in a matrix form, and the multiplexing unit is positioned between the M * N nonvolatile storage units arranged in the matrix form and the SRAM storage unit; the M * N non-volatile storage units are used for multiplexing the SRAM storage unit through the multiplexing unit, and the M * N non-volatile storage units are used for multiplexing the SRAM storage unit through the multiplexing unit; wherein M and N are positive integers.

The embodiment of the present disclosure relates to the photovoltaic field, and provides a photovoltaic module. The photovoltaic module comprises a plurality of cell strings and an insulation part. The cell string comprises a plurality of cell pieces arranged along a first direction. The cell string comprises a first surface and a second surface arranged oppositely. The plurality of cell strings comprises a first cell string and a second cell string. The second surface of the second cell string is overlapped on the first surface of the first cell string. The area where the second cell string is overlapped with the first cell string is an overlapping area. The cell piece comprises a first side and a second side arranged oppositely. A plurality of thin grids are arranged on the first side and the second side. The thin grids extend along a second direction. Part of the thin grids are located in the overlapping area. The insulation part is located on the overlapping area and electrically isolates the thin grids in the overlapping area of the first cell string from the thin grids in the overlapping area of the second cell string. The embodiment of the present disclosure can at least improve the power and reliability of the photovoltaic module.

The application discloses an air isolation opposite double PCB power supply structure, which splits power supply circuits into two parallel and opposite independent printed circuit boards according to function modules and strong and weak electric properties, forms an open pure air isolation gap between the boards, and realizes mechanical fixing and electrical interconnection across the gap through an insulating coated conductive support piece. The application completely separates strong and weak electric circuits from the physical layer, eliminates the substrate parasitic coupling interference of traditional multi-layer PCBs by using the low dielectric property of air, and simultaneously considers compactness and rationality of wiring, thereby significantly improving the power supply electromagnetic compatibility and operation stability, and being suitable for high-end customized purification power supply fields. The structure can be matched with a single-point RC coupling suspended star-shaped grounding to realize double-layer noise reduction of the whole machine.