16results about How to "Improve area utilization" patented technology

The invention discloses a transistor structure, a cascode current mirror and a chip, and belongs to the technical field of integrated circuit chips. The transistor structure comprises at least one transistor unit. The transistor unit comprises a substrate and an active region formed on the substrate. The n grid electrodes are arranged on the active region in the first direction, n is an even number, diffusion regions are defined on the two sides of each grid electrode in the first direction, and the diffusion regions between every two adjacent grid electrodes are continuous; wherein the ith grid electrode is connected with the (ni + 1) th grid electrode, and i = 1, 2,..., n / 2. By sharing the diffusion regions, the area utilization rate is improved, wiring is simplified to reduce parasitic resistance and parasitic capacitance effects, and the layout performance is improved.

The application discloses a 3D heterogeneous chip-based attenuator and an attenuation method thereof. The 3D heterogeneous chip-based attenuator comprises a first radio frequency chip and a second radio frequency chip. The first radio frequency chip is provided with a first radio frequency transmission line for transmitting a radio frequency signal, a first coupling member for coupling radio frequency signal energy and a second coupling member for coupling radio frequency signal energy. The first coupling member is electrically connected with an input end of the first radio frequency transmission line, and the second coupling member is electrically connected with an output end of the first radio frequency transmission line. The second radio frequency chip is provided with a second radio frequency transmission line for receiving the radio frequency signal on the first coupling member and outputting the radio frequency signal to the second coupling member. In the application, the first coupling member and the second coupling member can sequentially couple radio frequency signal energy to realize radio frequency signal energy attenuation, that is, the attenuator does not need to install a resistor on the first radio frequency chip when attenuating radio frequency signal energy, which improves the integration of the 3D heterogeneous chip.

The application discloses a wiring method and device applied to a chip and a storage medium, the chip comprising a plurality of functional modules, the functional module comprising a pin area, wherein the wiring method applied to the chip comprises: grouping processing the plurality of functional modules to determine at least one functional group, each functional group comprising a plurality of adjacent functional modules; and performing wiring processing on the functional group, the wiring processing comprising: determining at least one functional module in the functional group as a to-be-wired unit, the to-be-wired unit further comprising an output area; determining a single-layer wiring corresponding to the to-be-wired unit, the single-layer wiring being connected from the pin area of the to-be-wired unit to the output area. The technical scheme can effectively wire the to-be-wired unit, thereby preventing wiring congestion and improving the area utilization rate of the functional module.

The application provides a trench power device with a back source structure and a preparation method thereof. The preparation method comprises the following steps: forming a P-type body region and an N-type drift region on a surface layer of an N-type substrate; forming a trench, wherein the trench extends from the P-type body region to the N-type substrate; forming a gate dielectric layer on a surface of the trench, and filling a gate layer in the trench; forming an isolation layer, and forming a drain through hole in the isolation layer; performing N-type ion implantation on the drain through hole to form an N-type drain region in the N-type drift region; forming a drain electrode; etching a back surface of the N-type substrate to form a source through hole, wherein the source through hole exposes the P-type body region; and depositing a source electrode on the back surface of the N-type substrate and in the source through hole, wherein the source electrode is connected with the N-type substrate and the P-type body region. The drain electrode and the gate electrode are integrated on the front surface of the device, the trench gate structure is adopted to improve the unit density and the channel control ability, and the source electrode is connected with the P-type body region through the back surface deep groove contact, so that the source contact resistance is effectively reduced, and the heat dissipation capacity is improved.

The application discloses a microwave network assisted arbitrary-tap T-coil automatic synthesis method, comprising the following steps: firstly, using a microwave network to obtain the limit performance and the optimal topological structure of a circuit under the action of non-ideal factors; then, using the microwave network to consider the change range of the optimal inductance value when the quality factor and the coupling coefficient of the T-coil change in a reasonable range and to take the change range as an optimization area; then, according to the set index and process, combining the extended Wheeler formula and Latin hypercube sampling to obtain initial samples; then, using a Gaussian process regression to establish a proxy model of the concerned index and the parameters; finally, performing global optimization through a multi-path global optimization algorithm to obtain a target T-coil layout. It is verified that the method can efficiently synthesize the optimal T-coil.

This invention relates to a compact V-type condenser with a subcooling section, comprising a V-type heat exchanger and a condensing fan mounted above it. The V-type heat exchanger includes a heat exchanger 1 and a heat exchanger 2 arranged symmetrically and inclined. The V-type heat exchanger is divided into a heat exchange section near the condensing fan and a subcooling section away from the condensing fan. The refrigerant is connected through a manifold, which includes an exhaust manifold and a liquid collection manifold located in the heat exchange section, and a subcooling manifold and a return manifold located in the subcooling section. The refrigerant flows from the exhaust manifold through several heat exchange paths into the liquid collection manifold, then into the subcooling manifold, and finally into the return manifold through several more heat exchange paths. The subcooling section further subcools the already liquefied refrigerant. This invention, without increasing the condensing area, improves the internal heat exchange effect of the refrigerant simply by adjusting the refrigerant flow path, effectively increasing the utilization rate of the heat exchanger area, and has significant economic and promotional value.

The invention provides a three-dimensional storage and near storage computing architecture which can be applied to the technical field of circuit design. The three-dimensional storage and near-storage computing architecture comprises a control layer, which comprises a gating module and a driving module; the plurality of storage layers are stacked on the surface of the control layer, and each storage layer comprises a plurality of storage units; wherein the gating module is used for controlling a target storage layer in the plurality of storage layers to be in a working state under the control of a gating signal; and the driving module is used for controlling the target storage unit in the target storage layer to execute read-write operation.

This utility model discloses a three-phase high power density PCB stator winding structure and its motor and miniature fan. Each layer of the PCB coil board in the three-phase high power density PCB stator winding structure is symmetrically divided into six coil regions, each with a 2D printed coil forming six windings. Windings in the same numbered coil region on different layers are connected in series via internal or external interlayer vias to form windings U1, V1, W1, U2, V2, and W2. Two windings 180° apart mechanically constitute one phase. Since the windings are roughly the same shape, the problem of large electromagnetic torque fluctuations is effectively solved, improving the motor's operational stability. Furthermore, the 2D printed coils are spirally wound, resulting in a compact layout, high coil density, and effectively improved area utilization and increased power. Applying this three-phase high power density PCB stator winding structure to motors or miniature fans makes the overall structure more compact and thinner.

The invention provides a semiconductor device, a manufacturing method thereof and a memory system. The semiconductor device comprises a first semiconductor structure with a peripheral circuit, wherein the first semiconductor structure comprises a substrate, a first dielectric stack layer, a second dielectric stack layer and a conductive column; wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, and a first device structure is formed on the first surface; the first dielectric stack layer is located on the first surface, an interconnection structure is arranged in the first dielectric stack layer, and the first dielectric stack layer is located on the side, away from the substrate, of the first device structure and connected with the first device structure; the second dielectric stack layer is located on the second surface, and a first bonding pad structure is arranged in the second dielectric stack layer and is exposed on the surface, away from the substrate, of the second dielectric stack layer; the conductive pillar extends in a direction perpendicular to the first face and penetrates through the substrate, one end of the conductive pillar extends to the first dielectric stack layer and is connected to the interconnection structure, and the other end of the conductive pillar extends to the second dielectric stack layer and is connected to the first pad structure.

This invention discloses an arithmetic logic circuit suitable for balanced ternary systems, comprising a unary balanced ternary operation circuit, a balanced ternary half-adder circuit, a balanced ternary full-adder circuit, and a balanced ternary multiplier circuit. Single-input logic conversion is achieved through the combination of polarized ternary inverters and transistors. The half-adder consists of a basic unit and a transmission gate, realizing two-bit summation and carry output. The full-adder employs two cascaded half-adders and optimizes the carry path, significantly shortening the critical path and reducing the number of transistors. The multiplier uses the basic unit as the control core and combines it with a standard ternary inverter to achieve accurate multiplication. This invention overcomes the interconnection bottleneck of traditional binary logic, avoids the high hardware overhead of unbalanced ternary logic circuits in signed number calculations, and avoids the accuracy loss of approximate calculations in existing balanced ternary logic circuits. It has advantages such as simplified structure, low latency, low power consumption, and accurate operation, and is suitable for high-performance computing scenarios such as artificial intelligence, big data, and very large-scale integrated circuits.

According to the wafer-level radio frequency integrated circuit structure and the preparation method thereof, the acoustic wave filter and other functional devices are integrated on the same wafer at the same time, miniaturization of a radio frequency front-end module is achieved, the area utilization rate of a chip is greatly increased, the requirement of a mobile terminal for the device size is met, and the manufacturing cost is reduced. Electrical connection among different devices is achieved through the metal interconnection lines in the chip, compared with a traditional packaging mode that a ceramic substrate and an organic substrate are used for electrical interconnection, the interconnection distance is greatly shortened, signal loss and delay caused by parasitic inductance, capacitance and resistance are effectively reduced, and the reliability of the chip is improved. Compared with a traditional substrate interconnection packaging technology, the manufacturing method of the radio frequency front-end module is simple and can be compatible with a standard technology such as a silicon-based CMOS technology, so that the area utilization rate of a chip is increased, and the production cost is reduced.

This invention proposes a multifunctional ceramic packaging substrate and its fabrication method, relating to the field of semiconductor technology. The multifunctional ceramic packaging substrate includes a ceramic core board and a wiring layer; the wiring layer is disposed on the side of the ceramic core board, and multiple chips and multiple passive devices are embedded within the wiring layer, with the chips and passive devices electrically interconnected with the wiring layer. This invention also proposes a fabrication method for the multifunctional ceramic packaging substrate, comprising the following steps: providing a ceramic core board; forming a plurality of interconnect holes through the ceramic core board; embedding corresponding chips and passive devices within the wiring layer; forming a second layer by distributing a plurality of stacked ABF / BT layers outside the first layer, the first and second layers forming an ABF / BT composite layer; distributing a solder resist layer outside the ABF / BT composite layer; and distributing a surface treatment layer outside the solder resist layer. This invention embeds chips and passive devices into the wiring layer, improving circuit reliability and the overall area utilization of the ceramic core board, and reducing signal transmission delay.

The embodiment of the present disclosure relates to the photovoltaic field, and provides a photovoltaic module. The photovoltaic module comprises a plurality of cell strings and an insulation part. The cell string comprises a plurality of cell pieces arranged along a first direction. The cell string comprises a first surface and a second surface arranged oppositely. The plurality of cell strings comprises a first cell string and a second cell string. The second surface of the second cell string is overlapped on the first surface of the first cell string. The area where the second cell string is overlapped with the first cell string is an overlapping area. The cell piece comprises a first side and a second side arranged oppositely. A plurality of thin grids are arranged on the first side and the second side. The thin grids extend along a second direction. Part of the thin grids are located in the overlapping area. The insulation part is located on the overlapping area and electrically isolates the thin grids in the overlapping area of the first cell string from the thin grids in the overlapping area of the second cell string. The embodiment of the present disclosure can at least improve the power and reliability of the photovoltaic module.

The application discloses an air isolation opposite double PCB power supply structure, which splits power supply circuits into two parallel and opposite independent printed circuit boards according to function modules and strong and weak electric properties, forms an open pure air isolation gap between the boards, and realizes mechanical fixing and electrical interconnection across the gap through an insulating coated conductive support piece. The application completely separates strong and weak electric circuits from the physical layer, eliminates the substrate parasitic coupling interference of traditional multi-layer PCBs by using the low dielectric property of air, and simultaneously considers compactness and rationality of wiring, thereby significantly improving the power supply electromagnetic compatibility and operation stability, and being suitable for high-end customized purification power supply fields. The structure can be matched with a single-point RC coupling suspended star-shaped grounding to realize double-layer noise reduction of the whole machine.

The application relates to the technical field of liquid cooling equipment, and particularly provides a high-heat-flow-density spiral heterogeneous pin-finned liquid cooling plate, which comprises a plurality of heat-dissipating pin-fins, an upper cover shell, a bottom of the upper cover shell being provided with a downwardly-opened accommodating cavity, a lower base plate, the lower base plate being combined with the open cover, the plurality of heat-dissipating pin-fins being arranged in the accommodating cavity and fixedly arranged on the lower base plate, and an outer wall of the lower base plate being used for contacting a high-heat-flow-density equipment; wherein the plurality of heat-dissipating pin-fins are all extended upwards from the bottom of the lower base plate by spiral blades; then the heat-dissipating pin-fins in the form of the spiral blades extending upwards from the bottom are arranged on the lower base plate, so that the cooling liquid is fully contacted with the spiral blades when flowing in the cavity, the contact area between the cooling liquid and the heat-dissipating pin-fins is increased, and the heat exchange efficiency is improved. Furthermore, the heterogeneous pin-fins adopting the pin-finned process can cover a larger range of edges and corners, so that the utilization rate of the base plate area is improved.

This disclosure provides a carry compression circuit, a chip, and an electronic device. The carry compression circuit includes a first selection module and a second selection module. The first selection module is used to perform XOR processing on a first input signal and a second input signal to obtain a first XOR result, select a first carry output signal from the first input signal and a third input signal based on the first XOR result, and output it; and determine an intermediate processing result based on the first XOR result and the third input signal and send it to the second selection module. The second selection module is used to perform XOR processing on the intermediate processing result and a fourth input signal to obtain a second XOR result, and determine a second carry output signal and an XOR output signal based on the second XOR result and the carry input signal, and output them. Embodiments of this disclosure can reduce the number of transistors.