Logic gate cell

Abstract

To provide a small-area and low-power-consuming logic gate cell which is constructed of a circuit of two inverting logic gates connected in series in a layout of four-step diffusion regions. A first inverting logic gate is formed of a small transistor on internal two-step diffusion regions, a second inverting logic gate is formed of external two-step diffusion regions, and output wirings of the second inverting logic gate is formed of second metal layer wirings so that the second metal layer wirings extend over the first inverting logic gate.

Description

BACKGROUND OF THE INVENTION[0001] 1. Field of the Invention[0002] The present invention relates to logic gate cells used as an element in an LSI designed in a standard cell format and falls within the layout design technology of the logic gate cell manufactured in CMOS processes, and particularly to a logic gate cell featuring a small area and low power consumption.[0003] 2. Description of the Related Art[0004] A cell having a circuit arrangement of two inverting logic gates connected is frequently used for a logic gate cell that is an element when an LSI is designed using a standard cell technology. The inverting logic gates here refer to a NAND gate, a NOR gate, a NOT gate, an AND-NOR compound gate and an OR-NAND compound gate. Logic symbols and circuit examples corresponding to the inverting logic gates are respectively shown in FIGS. 1A and 1B through FIGS. 7A and 7B. FIGS. 1A through 7A respectively show the logic symbols and FIGS. 1B through 7B respectively show the circuit ex...

AI Technical Summary

Benefits of technology

0008] Accordingly, an object of the present invention is to provide a high area-utilization and small-area logic gate cell which employs a layout that narrows a cell width (the horizontal length as shown in drawings) instead of lowering the cell height, to realize a low power consuming logic gate cell based on a narrow gate width transistor.

Problems solved by technology

The above methods present the following problems.

Secondly, as the cell height is lowered, there is no choice but to arrange a plurality of transistors horizontally side by side and connect them, to realize a high-power (wide gate width) transistor, and a horizontally elongated cell results, suffering a poor area utilization and the cell area, on the contrary, increases more than that in the high cell height layout.

These problems arise as a result of attempting lower the cell height to reduce the cell area.

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