Wafer thinning method

Abstract

The invention discloses a wafer thinning method, which comprising the steps of: carrying out bonding process on multiple layers of wafers; adding filler in edge gaps of the boned wafers; performing solidification process on the filler; carrying out thinning process on the bonded upmost layer wafer and / or downmost layer wafer; and removing the filler. According to the method provided by the invention, the edges of the wafers cannot be fractured due to stress when thinning the wafers, thereby avoiding scratches and residuals formed on the surfaces of the wafers caused by chippings produced in fracture; and since the trimming process is not needed, the technical process is simplified, the cost is reduced, and the wafer area utilization ratio is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer thinning method. Background technique [0002] In the field of semiconductor manufacturing, since a thinned wafer can be beneficial to packaging, effective transmission of light, etc., the wafer thinning process has become an important process in the field of semiconductor manufacturing, such as the field of integrated circuits. [0003] see Figure 1-4 , figure 1 is a schematic flow chart of the usual wafer thinning method, Figure 2-4 It is a schematic diagram of the cross-sectional structure corresponding to each preparation step of the usual wafer thinning method, and the usual wafer thinning method includes: [0004] Step S11: See figure 2 , performing a bonding process on wafers 101 and 102; [0005] Step S12: See image 3 , performing a trimming process on the bonded wafer 101; [0006] Step S13: See Figure 4 , performing a thinning pr...

AI Technical Summary

Problems solved by technology

[0008] In order to prevent the bonded wafer from breaking during the thinning process, the industry usually adopts a trimming process. Before the thinning process, the edge of the bonded wafer is first ground off, that is, the trimming process is performed. The process requires larger-scale cutting to the inside of the wafer, which will reduce the actual use area of ​​the wafer, thereby reducing the utilization rate of the wafer area and increasing the process cost

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