14 results about "Tunneling field effect transistor" patented technology

The invention relates to a negative capacitance tunneling field effect transistor and a preparation method thereof, belongs to the technical field of field effect transistors, and solves the technical problems of limited tunneling area and small on-state current of an existing tunneling field effect transistor. The transistor comprises a source region, an intrinsic region, a drain region, a gate oxide layer, a metal gate, a drain electrode, a source electrode and an HfO2 ferroelectric layer. And the lengths of the HfO2 ferroelectric layer and the metal gate are smaller than the length of the gate oxide layer. And the doping type of the intrinsic region is the same as that of the drain region and is opposite to that of the source region. The preparation method comprises the steps of sample wafer pretreatment, photoetching, etching, ion implantation, photoresist removal, activation, implantation and doping, gate oxide layer deposition, HfO2 ferroelectric layer preparation, metal gate preparation, oxide layer removal, and source electrode and drain electrode deposition. The invention is used for the tunneling field effect transistor with the short gate structure based on the negative capacitance effect.

The application discloses a kind of Gauss light doping source junctionless type tunneling field effect transistor, comprising: source region, pocket area, channel region, drain region, polar grid, control grid, source, drain, first dielectric layer, second dielectric layer and third dielectric layer;Source region is connected with source and pocket area, and adopts Gauss light doping InAs material;Pocket area is connected with channel region, and is InAs / GaAsSb heterojunction structure;Channel region is connected with drain region;Drain region is connected with drain;First dielectric layer is located on the two sides of source region;Polar grid is located on the first dielectric layer;Second dielectric layer is located on the two sides of a part of channel region;Third dielectric layer is located on the two sides of another part of channel region;Control grid, including tunneling gate and auxiliary gate.The application further discloses a kind of Gauss light doping source junctionless type tunneling field effect transistor's single particle irradiation effect simulation optimization method, can provide more comprehensive simulation data, and device optimization effect is better.

A SnS2 / MoSe2 heterojunction tunneling field effect transistor based on double-gate regulation and its preparation method and application. The present application belongs to the technical field of multifunctional optoelectronic transistors. The purpose of the present application is to solve the technical problem that the heat-activated carriers of the existing tunneling field effect transistor are greatly affected by the environment and have a short service life. The tunneling field effect transistor of the present application uses graphene nanosheet / h-BN nanosheet as the top gate, SiO2 / Si as the bottom gate, and SnS2 / MoSe2 as the heterojunction. Method: First, obtain SnS2, MoSe2, h-BN, graphene nanosheet on the bottom gate by mechanical exfoliation method; then transfer MoSe2, h-BN, graphene nanosheet onto SnS2 nanosheet in sequence by dry transfer method; then evaporate metal bonding layer / Au electrode layer to obtain gate, drain and source, and obtain tunneling field effect transistor after annealing. It is applied to the field of logic circuit components.

A self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor and its fabrication method, namely, using hot-wall chemical vapor deposition technology, in n + n-type 4H-SiC substrates are grown sequentially ‑ Type 4H-SiC drift region, p + A p-type 4H-SiC shielding layer and an n-type 4H-SiC carrier extension layer 1 are constructed; an n-type Si carrier extension layer 2 is grown using low-pressure chemical vapor deposition to construct a Si / 4H-SiC heterojunction; and a p-type Si bulk region and an n-type Si carrier extension layer 2 are formed using ion implantation. + Type Si source layer and n ‑ The device employs a Si channel layer; edge trenches are etched, and then a planar main gate and two auxiliary gates are fabricated using low-pressure chemical vapor deposition (LPCVD); electrodes are then deposited. In this invention, an accumulation layer channel is formed at the bottom of the main gate oxide layer, and an inversion layer channel is formed inside the auxiliary gate oxide layer, allowing electrons to transport in parallel. The auxiliary gate voltage regulates the Si / 4H-SiC heterojunction barrier to achieve tunneling, reducing specific on-resistance. During reverse recovery, this heterojunction isolates the transport paths of tail-state electrons and holes in the drift region, preventing recombination, reducing reverse recovery loss, and improving static and dynamic performance.

The application provides a hybrid conduction mechanism surrounding gate transistor, which comprises a surrounding gate MOSFET device, a second source region and a second drain region; the surrounding gate MOSFET device comprises a substrate, a first source region and a first drain region; the first source region and the first drain region are doped with first ions; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, and the height of the second source region and the second drain region is not lower than the height of the substrate between the first source region and the first drain region; the second drain region is doped with the first ions, and the second source region is doped with second ions. The technical scheme solves the problem of bottom parasitic channel current leakage of the surrounding gate MOSFET device, and by additionally arranging the second source region and the second drain region, a tunneling field effect transistor (TFET) device structure is connected in parallel at the bottom of the traditional surrounding gate MOSFET device, so that the surrounding gate channel diffusion drift current and the bottom channel band-to-band tunneling current are hybridly conducted, and better super-steep switching characteristics are obtained.

The invention provides a tunneling field effect transistor with an adjustable and controllable tunneling area and a manufacturing method of the tunneling field effect transistor. The tunneling field effect transistor comprises a source layer, a drain layer, a vertical channel part and a gate stack, wherein the source layer, the drain layer, the vertical channel part and the gate stack are vertically stacked on a substrate; the vertical channel part is epitaxially grown; the source layer is provided with a bottom and a boss protruding from the bottom in the vertical direction; the drain layer is arranged above the source layer; the epitaxial channel part comprises a first part which is arranged between the source layer and the drain layer and connects the source layer and the drain layer, a second part which extends from the first part to the side wall of the boss, and a third part which further extends to the surface of the bottom of the source layer; and the gate stack on the channel part extends to the surfaces of the second part and the third part of the channel part. The channel part and the source layer can be regulated and controlled by the epitaxial lamination layer, so that the tunneling area is regulated, and the on-state current is improved.

The invention provides a tunneling field effect transistor with a vertical channel, a preparation method of the tunneling field effect transistor and electronic equipment. The transistor comprises a substrate, a first source-drain layer, a channel layer and a second source-drain layer, a first transverse groove surrounding the first channel region and a second transverse groove surrounding the second channel region are formed between the first source-drain layer and the second source-drain layer; a gate dielectric layer; and a gate layer including a first gate region parallel to the surface of the substrate and a second gate region extending in a vertical direction. According to the invention, the tunneling field effect transistor with the vertical channel is realized, the area occupied by the device in the horizontal direction is reduced, and the density of the device is improved; and meanwhile, the control effect on the tunneling effect of the channel layer is improved by utilizing the ring gate design, the first channel region and the second channel region are combined, the preparation of the channel with the controllable length is realized, meanwhile, self-alignment during the preparation of the gate layer is formed, the requirement of the device on a photoetching process is effectively reduced, and the performance of the device is improved.

A tunneling field effect transistor includes a gate electrode, a tunneling field active layer, a first electrode, and a second electrode disposed on a base substrate; the tunneling field active layer includes a first-type active layer and a second-type active layer that are stacked, wherein the first-type active layer includes a first-type channel region and a first source-drain region, the second-type active layer includes a second-type channel region and a second source-drain region, an orthographic projection of the first-type channel region on the base substrate is completely overlapped with an orthographic projection of the second-type channel region on the base substrate, the first source-drain region is located at a side of the tunneling field active layer and is connected with the first electrode.

The invention provides a preparation method of a fin type tunneling field effect transistor, and belongs to the technical field of micro-nano electronics. A traditional planar TFET device and a FinFET structure are combined, the advantage of low off-state current can be kept while on-state current can be improved, bipolar current is restrained, namely, an expansion region is prepared in a source region in a self-alignment mode, so that a tunneling junction is formed at the gate-source overlapping position, tunneling current is improved, and meanwhile, through a thick side wall prepared before source-drain epitaxy, the tunneling efficiency is improved. An under-coverage area structure is formed at the drain terminal to suppress bipolar current; meanwhile, the main body of the substrate region of the device is still lightly doped high-resistance silicon, so that the advantage of low off-state current of the tunneling field effect transistor is maintained. Besides, the preparation method is based on a standard fin type tunneling field effect transistor process flow of an advanced node, only one photoetching plate is additionally arranged on the premise of not changing a basic process flow, and the potential of realizing large-scale production is maintained.

The application discloses an embedded semiconductor random access memory structure and a control method thereof, and belongs to the technical field of semiconductor memories. The memory structure comprises a ferroelectric memory cell for storing information and a tunneling field effect transistor connected with the memory cell, and the tunneling field effect transistor is used for controlling the ferroelectric memory cell and performing write operation and read operation. A plurality of the memory structures form a semiconductor memory array, and the control method comprises write 0, write 1, read and rewrite steps. The application utilizes the unidirectional conduction characteristic and extremely low leakage current characteristic of the tunneling field effect transistor, can reduce the operating voltage and power consumption of the memory array, and can improve the memory integration density. The application is suitable for manufacturing of semiconductor memory chips, and the control method and circuit are relatively simple.

The application discloses an embedded semiconductor random access memory structure and a control method thereof, and belongs to the technical field of semiconductor memories. The memory structure comprises a ferroelectric memory cell for storing information and a tunneling field effect transistor connected with the memory cell, and the tunneling field effect transistor is used for controlling the ferroelectric memory cell and performing write operation and read operation. A plurality of the memory structures form a semiconductor memory array, and the control method comprises write 0, write 1, read and rewrite steps. The application utilizes the unidirectional conduction characteristic and extremely low leakage current characteristic of the tunneling field effect transistor, can reduce the operating voltage and power consumption of the memory array, and can improve the memory integration density. The application is suitable for manufacturing of semiconductor memory chips, and the control method and circuit are relatively simple.

The invention provides a novel high-k gate dielectric source region extending double-gate tunnel field effect transistor which comprises a source region, a channel region and a drain region which are sequentially arranged from left to right, the left side of the channel region is a thin end, the right side of the channel region is a thick end, the source region is embedded in the thin end of the channel region, a low-k insulator layer is arranged between the right side of the source region and the channel region, and the drain region is embedded in the low-k insulator layer. The thick end of the channel region is connected with the drain region with the same thickness; the upper side and the lower side of the channel region are both covered with high-k gate media. The left side of the source region is provided with a source electrode; one side, far away from the channel region, of the high-k gate dielectric layer is provided with a gate electrode; a drain electrode is arranged on the right side of the drain region; the low-k insulator layer is prepared from a low-k insulator material, and the high-k gate dielectric layer is prepared from a high-k insulator material; and the source region, the channel region and the drain region are prepared from silicon. The problems that the ratio of on-state current to switching current of the double-gate tunnel field effect transistor is small, and the sub-threshold swing is large can be solved.

The invention provides a stacked transistor, a preparation method thereof, a device and electronic equipment. The method comprises the following steps: forming a channel structure on a substrate; the channel structure comprises a front channel structure and a back channel structure; depositing an insulating material on the surface of the first source-drain region of the stacked transistor to form a first inner side wall; transversely etching the first semiconductor material in the channel structure on the first inner side wall to form a first channel groove; performing source-drain epitaxial growth in the first source-drain region and the first channel groove to form a first source-drain structure; depositing an insulating material on the surface of a second source-drain region of the stacked transistor to form a second inner side wall; performing source-drain epitaxial growth in the second source-drain region to form a second source-drain structure; forming a front transistor based on the front channel structure; overturning the wafer and thinning the substrate; and forming a back transistor based on the back channel structure. According to the invention, compatibility of the stacked transistor and the tunneling field effect transistor can be realized.

A germanium-source double-gate tunnel field-effect transistor (Ge-source-DG-TFET) comprising: a channel region with a length of 50 nm and a silicon layer thickness of 12 nm, wherein the channel region is weakly p-doped with a concentration of 1 × 10¹⁶ cm⁻³; a germanium source region p-doped with a concentration of 1 × 10²⁰ cm⁻³ to facilitate the band-to-band tunneling process; a drain region n-doped with a concentration of 5 × 10¹⁸ cm⁻³; a heterodielectric gate oxide structure with a thickness of 2 nm, wherein the heterodielectric gate oxide structure comprises: a 30 nm long low-dielectric constant (low-k) SiO₂ region on the drain region side, and a high-dielectric constant HfO₂ region arranged on the source region side. is;and a source-pocket structure with a length of 6 nm and a doping concentration of 2 × 1019 cm-3, positioned between the germanium source region and the channel region.