48 results about "Tunneling field effect transistor" patented technology

Disclosed is an embedded semiconductor random access memory structure, including a hafnium oxide-based ferroelectric storage element suitable for storing information, and a tunneling field effect transistor connected to the storage element. The tunneling field effect transistor is suitable for controlling the hafnium oxide-based ferroelectric storage element to perform read and write operations. A semiconductor memory array can be formed by repeating the above memory structures. A control method for the memory structure includes steps of writing 0, writing 1, reading, and writing back.

The application relates to the technical field of semiconductor devices, and discloses a biosensor based on a parallel tunneling junction vertical tunneling field effect transistor and a preparation method thereof. The sensor comprises a stepped drain region, drain contacts arranged on the two sides of the drain region, a stepped channel layer arranged on the top of the drain region, source regions arranged on the two sides of the channel layer, source contacts arranged on the top of each source region, a groove arranged on the top layer of the channel layer, a gate dielectric layer arranged in the groove, a gate metal arranged on the upper surface of the gate dielectric layer at the bottom of the groove, and a cavity formed between the gate metal and the gate dielectric layer, which is a biomolecule detection cavity. The preparation method comprises the following steps: etching the drain region and the channel layer to obtain a target shape and a groove structure, embedding the source region and an oxide layer, etching part of the oxide layer and embedding the gate metal, etching the oxide layer on the two sides of the gate metal and growing the gate dielectric layer, forming the biomolecule detection cavity, and metalizing part positions of the source region and the drain region to obtain a final structure. The device current and the sensitivity of biomolecule detection are improved.

The invention relates to a negative capacitance tunneling field effect transistor and a preparation method thereof, belongs to the technical field of field effect transistors, and solves the technical problems of limited tunneling area and small on-state current of an existing tunneling field effect transistor. The transistor comprises a source region, an intrinsic region, a drain region, a gate oxide layer, a metal gate, a drain electrode, a source electrode and an HfO2 ferroelectric layer. And the lengths of the HfO2 ferroelectric layer and the metal gate are smaller than the length of the gate oxide layer. And the doping type of the intrinsic region is the same as that of the drain region and is opposite to that of the source region. The preparation method comprises the steps of sample wafer pretreatment, photoetching, etching, ion implantation, photoresist removal, activation, implantation and doping, gate oxide layer deposition, HfO2 ferroelectric layer preparation, metal gate preparation, oxide layer removal, and source electrode and drain electrode deposition. The invention is used for the tunneling field effect transistor with the short gate structure based on the negative capacitance effect.

The invention discloses an undoped tunneling junction line tunneling field effect transistor and a preparation method thereof. The line tunneling field effect transistor comprises a substrate, a drain electrode, an N + Si layer, SiO2 isolation, intrinsic Si, an L-shaped metal structure, intrinsic Ge, a grid electrode, a first oxide layer and a second oxide layer, stacking drain electrodes on the two sides of the N + Si layer on the substrate; intrinsic Si is stacked on the N + Si layer, and SiO2 isolation is stacked on the two sides of the intrinsic Si; intrinsic Ge is stacked on the two sides of the upper portion of the intrinsic Si, and a grid electrode is arranged between the intrinsic Ge; a second oxide layer covers the upper part of the SiO2 isolator and the outer side of the intrinsic Ge; high-work-function metal is stacked on the outer side of the second oxide layer and above the intrinsic Ge to form an L-shaped metal structure; a source electrode is formed above the intrinsic Ge, and a back gate is formed on the outer side of the second oxide layer. According to the invention, the line tunnel junction is formed on the intrinsic Ge, so that the on-state current of the transistor is improved, the sub-threshold swing is reduced, and the switching performance is improved.

The application discloses a kind of Gauss light doping source junctionless type tunneling field effect transistor, comprising: source region, pocket area, channel region, drain region, polar grid, control grid, source, drain, first dielectric layer, second dielectric layer and third dielectric layer;Source region is connected with source and pocket area, and adopts Gauss light doping InAs material;Pocket area is connected with channel region, and is InAs / GaAsSb heterojunction structure;Channel region is connected with drain region;Drain region is connected with drain;First dielectric layer is located on the two sides of source region;Polar grid is located on the first dielectric layer;Second dielectric layer is located on the two sides of a part of channel region;Third dielectric layer is located on the two sides of another part of channel region;Control grid, including tunneling gate and auxiliary gate.The application further discloses a kind of Gauss light doping source junctionless type tunneling field effect transistor's single particle irradiation effect simulation optimization method, can provide more comprehensive simulation data, and device optimization effect is better.

A SnS2 / MoSe2 heterojunction tunneling field effect transistor based on double-gate regulation and its preparation method and application. The present application belongs to the technical field of multifunctional optoelectronic transistors. The purpose of the present application is to solve the technical problem that the heat-activated carriers of the existing tunneling field effect transistor are greatly affected by the environment and have a short service life. The tunneling field effect transistor of the present application uses graphene nanosheet / h-BN nanosheet as the top gate, SiO2 / Si as the bottom gate, and SnS2 / MoSe2 as the heterojunction. Method: First, obtain SnS2, MoSe2, h-BN, graphene nanosheet on the bottom gate by mechanical exfoliation method; then transfer MoSe2, h-BN, graphene nanosheet onto SnS2 nanosheet in sequence by dry transfer method; then evaporate metal bonding layer / Au electrode layer to obtain gate, drain and source, and obtain tunneling field effect transistor after annealing. It is applied to the field of logic circuit components.

The invention belongs to the technical field of transistors, and particularly relates to a tunneling field effect transistor, a preparation method thereof, a photon chip and optical communication equipment. According to the tunneling field effect transistor, the tunnel junction is formed in the tunneling field active layer, the tunnel junction has a certain junction area and is perpendicular to the gate electrode, the distance of a tunneling channel is further shortened through the strong control force of the gate electrode on the whole tunnel junction, the on-state current of the tunneling field effect transistor can be improved, and the power consumption of a device can be reduced. Meanwhile, according to the design mode, the reconfigurable characteristic of the field tunneling effect transistor can be conveniently achieved, so that the flexibility and adaptability of the device are improved, and the design mode is crucial for developing smaller and more energy-saving circuits.

The application discloses a biosensor based on an inverted T-shaped negative capacitance tunneling field effect transistor, and mainly solves the problems of low sensitivity and complex manufacturing process in the prior art. The biosensor comprises, from bottom to top, a substrate (1), a channel region (4), a gate insulating dielectric layer (5), a gate ferroelectric layer (7), a gate titanium nitride layer (8), a gate metal layer (9), a source region (3) and a conductive layer (11). The channel region is provided with drain regions (6) on both sides, the drain regions are provided with isolation grooves (2) on both sides, the gate insulating dielectric layer is provided with biological filling layers (10) on both sides of a vertical part, the channel region adopts an inverted T-shaped structure, the gate insulating dielectric layer adopts a symmetrical L-shaped structure, and the gate metal layer is composed of a lower metal hafnium and an upper metal aluminum. The biosensor has high sensitivity and on-state current, can effectively inhibit short channel effect and bipolar effect, has simple manufacturing process and low manufacturing cost, and can be used for label-free detection of biomolecules.

A semiconductor tunnel FET (field effect transistor) including a plurality of nanosheet channels disposed between a first source / drain region and a second source / drain region. The first source / drain region includes a p-type material; and the second source / drain region includes an n-type material.

The invention relates to the technical field of semiconductor devices, in particular to a biosensor of a tunneling field effect transistor based on a barrier gate structure, which comprises a silicon substrate, an insulating layer, a channel, a gate dielectric layer, a source electrode, a drain electrode, a gate electrode, a biological nano cavity and a biological dielectric layer, the silicon substrate, the insulating layer, the channel and the gate dielectric layer are sequentially stacked from bottom to top; the source electrode and the drain electrode are distributed on two sides of the channel, are in contact with the channel and the gate dielectric layer, and are laminated on the upper surface of the insulating layer; the end part, close to the source electrode, of the channel is a P + doped region, and the end part, close to the drain electrode, of the channel is graphene; the end part, close to the P + doped region, of the graphene is an N + doped region, and the middle part of the graphene is a P barrier region; the biological nanometer cavity and the grid electrode are sequentially stacked on the upper surface, right facing the P barrier region, of the grid dielectric layer. The biological medium layer is stacked on the side face, close to the source electrode, of the biological nanometer cavity and makes contact with the grid electrode. Off-state current is reduced, power consumption is reduced, the switching current ratio is increased, and the problem that a biosensor in the prior art is low in sensitivity is solved.

According to the transistor and the electronic equipment, the GaAsSb / InGaAs heterojunction material is adopted, adjustment of GaAsSb / InGaAs on an energy band structure and a device structure can be more flexible by adjusting parameters such as the doping concentration of the P + type GaAsSb layer, the In component in the InGaAs layer and the side face inclination angles of the InGaAs layer and the P + type GaAsSb layer, the tunneling probability of carriers can be effectively increased, the grid control capacity can be enhanced, and the device performance can be improved. Therefore, the subthreshold swing of the tunneling field effect transistor can be reduced and the conduction current can be increased, so that the device performance of the GaAsSb / InGaAs tunneling field effect transistor can be remarkably improved on the premise that the preparation complexity of the device is not increased.

A tunneling field effect transistor is provided. The tunneling field effect transistor includes a semiconductor layer disposed on a substrate and having a first semiconductor region and a second semiconductor region. A band gap of the first semiconductor region is smaller than a band gap of the second semiconductor region, and a work function of the first semiconductor region is greater than a work function of the second semiconductor region. A gate overlapping the semiconductor layer is disposed over or under the semiconductor layer. A source and a drain are connected to the first semiconductor region and the second semiconductor region, respectively. The first semiconductor region has a first conductivity type source region in a region adjacent to the source and a first channel region overlapping the gate, and the second semiconductor region has a second conductivity type drain region in a region adjacent to the drain and a second channel region overlapping the gate. In the on state, the conduction band potential energy of the first channel region is equal to or higher than the conduction band potential energy of the second channel region.

Asymmetry may be used to adjust electrical characteristics of tunneling field effect transistors (TFETs). An exemplary TFET includes a gate stack disposed over a semiconductor layer, a source and a drain disposed in the semiconductor layer. The gate stack includes a gate electrode disposed on a gate dielectric. The gate stack is disposed between the source and the drain. The source has a first conductivity type, and the drain has a second conductivity type different from the first conductivity type. The gate stack is asymmetric. For example, a gate stack has an asymmetric gate dielectric, an asymmetric gate electrode, an asymmetric gate foot, an asymmetric sidewall, or a combination thereof. In some embodiments, the source and drain have asymmetric profiles. In some embodiments, the semiconductor layer is a semiconductor fin, and the gate stack wraps the semiconductor fin. The embodiment of the invention also discloses a tunneling field effect transistor and a manufacturing method thereof.

A self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor and its fabrication method, namely, using hot-wall chemical vapor deposition technology, in n + n-type 4H-SiC substrates are grown sequentially ‑ Type 4H-SiC drift region, p + A p-type 4H-SiC shielding layer and an n-type 4H-SiC carrier extension layer 1 are constructed; an n-type Si carrier extension layer 2 is grown using low-pressure chemical vapor deposition to construct a Si / 4H-SiC heterojunction; and a p-type Si bulk region and an n-type Si carrier extension layer 2 are formed using ion implantation. + Type Si source layer and n ‑ The device employs a Si channel layer; edge trenches are etched, and then a planar main gate and two auxiliary gates are fabricated using low-pressure chemical vapor deposition (LPCVD); electrodes are then deposited. In this invention, an accumulation layer channel is formed at the bottom of the main gate oxide layer, and an inversion layer channel is formed inside the auxiliary gate oxide layer, allowing electrons to transport in parallel. The auxiliary gate voltage regulates the Si / 4H-SiC heterojunction barrier to achieve tunneling, reducing specific on-resistance. During reverse recovery, this heterojunction isolates the transport paths of tail-state electrons and holes in the drift region, preventing recombination, reducing reverse recovery loss, and improving static and dynamic performance.

The present disclosure provides a transistor and an electronic device, adopts GaAsSb / InGaAs heterojunction material, can adjust the doping concentration of the P+ type GaAsSb layer, the In component in the InGaAs layer, and the side inclination angle of the InGaAs layer and the P+ type GaAsSb layer and other parameters, so that GaAsSb / InGaAs is more flexible in the adjustment of the energy band structure and the device structure, can effectively increase the tunneling probability of the carrier, enhance the gate control ability, so as to reduce the subthreshold swing of the tunneling field effect transistor and increase the on-current, therefore, the present disclosure can realize the significant improvement of the device performance of the GaAsSb / InGaAs tunneling field effect transistor without increasing the complexity of the device preparation.

The application provides a hybrid conduction mechanism surrounding gate transistor, which comprises a surrounding gate MOSFET device, a second source region and a second drain region; the surrounding gate MOSFET device comprises a substrate, a first source region and a first drain region; the first source region and the first drain region are doped with first ions; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, and the height of the second source region and the second drain region is not lower than the height of the substrate between the first source region and the first drain region; the second drain region is doped with the first ions, and the second source region is doped with second ions. The technical scheme solves the problem of bottom parasitic channel current leakage of the surrounding gate MOSFET device, and by additionally arranging the second source region and the second drain region, a tunneling field effect transistor (TFET) device structure is connected in parallel at the bottom of the traditional surrounding gate MOSFET device, so that the surrounding gate channel diffusion drift current and the bottom channel band-to-band tunneling current are hybridly conducted, and better super-steep switching characteristics are obtained.

The present invention provides a tunneling field effect transistor, a preparation method thereof, and a photodetector, which relate to the field of optoelectronic devices. The tunneling field effect transistor includes a substrate, and an insulating layer, a conductive layer, a dielectric layer, a heterojunction layer, and a packaging layer that are sequentially stacked on one side of the substrate; the heterojunction layer includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is stacked on the dielectric layer, at least a part of the second semiconductor layer is stacked on the first semiconductor layer, and the other part of the second semiconductor layer is stacked on the dielectric layer; the first semiconductor layer includes a tin disulfide layer, the second semiconductor layer includes a hafnium disulfide layer, and the packaging layer includes a hafnium oxide layer. The present invention uses plasma oxidation technology to perform packaging treatment on hafnium disulfide with ultra-high carrier characteristics, forming a hafnium oxide dielectric layer with a high dielectric constant, ensuring a high-quality interface, and then realizing the tunneling characteristics of the field effect transistor, laying a foundation for finally realizing low-power tunneling devices of high-performance nanomaterials in the future.

The application relates to the field of biosensors, and particularly relates to a biosensor based on a graphene double-material gate tunneling field effect transistor, which comprises a graphene channel, a source electrode, a drain electrode, an insulating medium layer, a silicon substrate, a gate medium layer, a first gate electrode, a second gate electrode, a biological medium layer and a biological nanocavity; the silicon substrate, the insulating medium layer, the graphene channel and the gate medium layer are sequentially stacked from bottom to top; the source electrode and the drain electrode are located on the left and right sides of the graphene channel; the biological medium layer and the second gate electrode are respectively stacked on the left and right end portions of the upper surface of the gate medium layer, and the biological medium layer is hollow to form the biological nanocavity; the first gate electrode is stacked on the upper surface of the biological medium layer; the work functions of the metal materials of the first gate electrode and the second gate electrode are different. The application can comprehensively control the energy band of the graphene channel, can realize energy band tunneling between the graphene without doping the graphene, has a relatively simple manufacturing process, and has high sensitivity.

A Schottky barrier tunneling field effect transistor biosensor with a sunken grid electrode and bidirectional current conduction comprises a channel, a groove is formed in the middle of the channel, protruding parts are arranged on the two sides of the groove, source electrodes are arranged on the tops of the protruding parts respectively, the two source electrodes and a drain electrode form bidirectional current conduction, and the drain electrode current of the device is increased; a concave gate dielectric layer is arranged at the upper part in the groove, so that the off-state current of the device is reduced; a grid electrode is arranged above the sunken grid electrode dielectric layer, biomolecule detection cavities are formed in the two sides of the grid electrode and above the grid electrode dielectric layer, and a drain electrode is arranged below the channel; the two sources and the drain on the two sides of the grid form bidirectional current conduction, the drain current sensitivity and the drain current sensitivity of the device are improved, the off-state current when K is equal to 1 is 2.1 * 10 <-18 > A / mu m, and compared with a traditional structure, the off-state current is reduced by 2.2 times; when K is equal to 12, the turn-on current of the transistor is 2.6 * 10 <-6 > which is reduced by 113% compared with 2.3 * 10 <-6 > of a traditional structure, and the transistor has the advantages of low off-state current, high drain current sensitivity and simple manufacturing process.

The present invention provides a gate-all-around tunneling field-effect transistor, comprising: a substrate; the substrate comprising: a first epitaxial region, a second epitaxial region, a first channel region, a second channel region and a third channel region; a first epitaxial layer formed in the first epitaxial region; a second epitaxial layer formed in the second epitaxial region; a plurality of first channel layers stacked in a direction away from the substrate, and two adjacent first channel layers are separated by a channel cavity; wherein the first channel layer comprises a first channel portion, a second channel portion and a third channel portion; an inner sidewall filled in the channel cavity of the first channel region and the third channel region; a second channel layer, a gate dielectric layer and a control gate; all formed in the second channel region; wherein the first channel portion is doped with a first ion, and the second channel layer is doped with a second ion; the types of the first ion and the second ion are different; so as to solve the problem of how to increase the on-state current of the gate-all-around tunneling field-effect transistor.

The invention provides a tunneling field effect transistor with an adjustable and controllable tunneling area and a manufacturing method of the tunneling field effect transistor. The tunneling field effect transistor comprises a source layer, a drain layer, a vertical channel part and a gate stack, wherein the source layer, the drain layer, the vertical channel part and the gate stack are vertically stacked on a substrate; the vertical channel part is epitaxially grown; the source layer is provided with a bottom and a boss protruding from the bottom in the vertical direction; the drain layer is arranged above the source layer; the epitaxial channel part comprises a first part which is arranged between the source layer and the drain layer and connects the source layer and the drain layer, a second part which extends from the first part to the side wall of the boss, and a third part which further extends to the surface of the bottom of the source layer; and the gate stack on the channel part extends to the surfaces of the second part and the third part of the channel part. The channel part and the source layer can be regulated and controlled by the epitaxial lamination layer, so that the tunneling area is regulated, and the on-state current is improved.

The invention provides a tunneling field effect transistor with a vertical channel, a preparation method of the tunneling field effect transistor and electronic equipment. The transistor comprises a substrate, a first source-drain layer, a channel layer and a second source-drain layer, a first transverse groove surrounding the first channel region and a second transverse groove surrounding the second channel region are formed between the first source-drain layer and the second source-drain layer; a gate dielectric layer; and a gate layer including a first gate region parallel to the surface of the substrate and a second gate region extending in a vertical direction. According to the invention, the tunneling field effect transistor with the vertical channel is realized, the area occupied by the device in the horizontal direction is reduced, and the density of the device is improved; and meanwhile, the control effect on the tunneling effect of the channel layer is improved by utilizing the ring gate design, the first channel region and the second channel region are combined, the preparation of the channel with the controllable length is realized, meanwhile, self-alignment during the preparation of the gate layer is formed, the requirement of the device on a photoetching process is effectively reduced, and the performance of the device is improved.

The present invention proposes a tunneling field effect transistor, a preparation method thereof and a photodetector, which relate to the field of photoelectric devices. The tunneling field effect transistor includes a substrate and an insulating layer, and a conductive layer, a dielectric layer and a heterostructure layer stacked on the insulating layer in sequence, the heterostructure layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is stacked on the dielectric layer, a part of the second semiconductor layer is stacked on the first semiconductor layer, and the other part of the second semiconductor layer is stacked on the dielectric layer, the first semiconductor layer includes a tin disulfide layer, and the second semiconductor layer includes a tin diselenide layer. The technical solution of the present invention effectively suppresses carrier recombination at the interface by forming a depletion region on tin disulfide; the device has a depletion region of about 10 7 The on / off ratio is 240 nm, and it exhibits an ultra-high responsivity of 37.5 A / W and a wide spectrum detection feature from ultraviolet to visible light, and is expected to become the next generation of high-efficiency optoelectronic devices.

Device comprising the following: an n-hetero-junction tunnel field-effect transistor, n-heTFET, with a source electrode (1107), a channel (1108) and a drain electrode (1109), wherein (a) the channel (1108) has a principal axis corresponding to the channel length and a secondary axis corresponding to the channel width and orthogonal to the principal axis, (b) the channel length is less than 10 nm and the channel width is less than 4 nm, (c) the source electrode (1107) is positively doped and has a first conduction band, (d) the drain electrode (1109) is negatively doped and the drain electrode (1109) has a second conduction band whose energy is higher than that of the first conduction band, wherein (e) the source electrode (1107) InAs and the drain electrode (1109) GaSb, or the source electrode (1107) Si and the drain electrode (1109) InAs or SiGe, or the source electrode (1107) GaAsSb and the drain electrode (1109) InAsSb or the source electrode (1107) InGaAs and the drain electrode (1109) InP.

A tunneling field effect transistor includes a gate electrode, a tunneling field active layer, a first electrode, and a second electrode disposed on a base substrate; the tunneling field active layer includes a first-type active layer and a second-type active layer that are stacked, wherein the first-type active layer includes a first-type channel region and a first source-drain region, the second-type active layer includes a second-type channel region and a second source-drain region, an orthographic projection of the first-type channel region on the base substrate is completely overlapped with an orthographic projection of the second-type channel region on the base substrate, the first source-drain region is located at a side of the tunneling field active layer and is connected with the first electrode.

The invention discloses a biosensor with a brim-shaped vertical tunneling field effect transistor and a preparation method thereof, and the sensor comprises a substrate, drain region contacts are arranged at two ends of the upper surface of the substrate, a drain region is arranged on the upper surface of the substrate between the drain region contacts, a T-shaped channel is arranged on the upper surface of the drain region, and high dielectric constant oxide layers are arranged at two sides of the bottom end of a vertical region of the channel. Gate metal is arranged on one side, far away from the channel, of each high-dielectric-constant oxide layer to form a bent biomolecule detection cavity, a horizontal region of the channel is embedded in a source region, the source region serves as an outer brim, the channel serves as an inner brim to form a brim-shaped structure, and an active region contact is arranged on the upper surface of the source region; a drain region, a channel and a source region gradually grow on a substrate through epitaxial growth, then a biomolecule detection cavity and a high dielectric constant oxide layer are formed through atomic layer deposition and etching, and finally a grid electrode, a source region contact and a drain region contact are deposited; the sensor has the advantages of high conduction current, sensitivity in biomolecule detection, low voltage requirement, low power consumption and simple preparation process.

A content addressable memory device including a memory cell array including a plurality of memory cells, each of which has a ferroelectric tunnel field effect transistor (FeTFET), and a match amplifier connected to the plurality of memory cells through a plurality of match lines may be provided. The FeTFET includes a first doped region including a first conductivity type, a second doped region including a second conductivity type different from the first conductivity type, a channel region formed between the first doped region and the second doped region, and a gate formed on the channel region and including a ferroelectric layer.

A tunneling field effect transistor having a buried drain structure is provided. The tunneling field effect transistor comprises a semiconductor pattern disposed on a substrate and including a thin part at one end, a thick part at the other end, and a step between the thin part and the thick part. A drain electrode is disposed on the thin part, a source electrode is disposed on the thick part, and a gate electrode is disposed on the thick part between the drain electrode and the source electrode. A gate insulating layer is disposed between the semiconductor pattern and the gate electrode and between a sidewall of the step of the semiconductor pattern and the drain electrode. The semiconductor pattern has a drain region of a first conductivity type induced by generation of a charge plasma of the first conductivity type in an area adjacent to the drain electrode, and a source region of a second conductivity type induced by generation of a charge plasma of the second conductivity type in an area adjacent to the source electrode, and a channel region between the source region and the drain region. A thickness of the drain electrode is lower than a height of the step of the semiconductor pattern.

The invention discloses a novel bipolar tunneling field effect transistor, and relates to the technical field of semiconductors. The insulating layer is positioned on the upper surface of the substrate; the source region, the channel region, the base region and the emitter region are all located on the upper surface of the insulating layer, and the source region, the channel region, the base region and the emitter region are sequentially arranged on the upper surface of the insulating layer and make contact with one another; wherein the source region, the channel region and the base region form a p-i-n structure of the tunneling field effect transistor, and the channel region, the base region and the emitter region form a PNP structure of the tunneling field effect transistor; the source electrode is located on the upper surface of the source region; the gate oxide layer is located on the upper surface of the channel region, and the gate electrode is located on the upper surface of the gate oxide layer; and the emitter is located on the upper surface of the emitter region. The performance of the tunneling field effect transistor can be improved.

The application provides a preparation method of a tunneling field effect transistor and the tunneling field effect transistor, and relates to the technical field of transistor preparation. The preparation method comprises the following steps: patterning and depositing a first low-dimensional semiconductor material film on a substrate; depositing a first hard mask film; spin-coating photoresist on the surface of the first hard mask film, removing the first hard mask film in a preset pattern area through exposure and development; depositing a second low-dimensional semiconductor material film and a second hard mask film, so that the second low-dimensional semiconductor material film outside the preset pattern area is covered by the second hard mask film and the first hard mask film to form a sandwich structure; and placing the device in a solution, only retaining the second low-dimensional semiconductor material film in the preset pattern area under the action of the solution and water bath ultrasonic waves, so as to obtain the tunneling field effect transistor. The above method can accurately control the appearance and size of the tunneling field effect transistor, ensure the pattern integrity and edge neatness, and improve the stability and repeatability of the electrical performance.