15results about "Time-delay networks" patented technology

Enhanced Bucket Brigade Delay (BBD) circuits which more readily support cascaded configurations. A gain control mechanism is utilized in combination with an attenuation coupling network between subsequent BBD stages to achieve significantly longer delays than are achievable by the single BBD device, without introducing excessive noise or increased power dissipation associated with the need of reconstructing and biasing the intermediate signal between BBD devices.

Enhanced Bucket Brigade Delay (BBD) circuits which more readily support cascaded configurations. A gain control mechanism is utilized in combination with an attenuation coupling network between subsequent BBD stages to achieve significantly longer delays than are achievable by the single BBD device, without introducing excessive noise or increased power dissipation associated with the need of reconstructing and biasing the intermediate signal between BBD devices.

The invention belongs to the technical field of integrated circuits, and particularly relates to a broadband low-amplitude error delayer. The delayer comprises an input matching network, an output matching network, a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a delay reference network, the input matching network is connected with one end of the first single-pole double-throw switch, and the other end of the first single-pole double-throw switch is connected with the input end of the delay unit and the input end of the delay reference network. One end of the second single-pole double-throw switch is connected with the output matching network, and the other end is connected with the input end of the delay unit and the output end of the delay reference network; the delayer designed by the invention has a wide-band large-frequency delay function, and has a good application prospect.

The present invention relates to the field of beamforming integrated circuits, and provides a hybrid multi-beamforming circuit structure, including: a power divider, receiving a first data stream for dividing the first data stream into a plurality of second data streams; and a power combiner, receiving the second data streams and combining the plurality of second data streams into a third data stream, where an input port of an FTVAP circuit is connected to an output port of the power divider, and an output port of the FTVAP circuit is connected to an input port of the power combiner, to control an amplitude, a phase, and time delay of the second data streams. A BTVAP circuit is connected to an input port of the power divider to control an amplitude, a phase, and time delay of the first data stream, or the BTVAP circuit is connected to an output port of the power combiner to control an amplitude, a phase, and time delay of the third data stream. The present invention is provided with a simple and proper structure, greatly improving an integration degree and reducing costs. The present invention is used in a phased array, implementing multi-beamforming and beam scanning.

According to a band-pass filter, n represents a natural number equal to or more than one, and the band-pass filter includes: an input terminal (1) to receive an input of an RF signal; a multi-phase splitter (3) to split the RF signal input to the input terminal into n RF signals whose phases each differ by 360 degrees / n; n signal paths (17 to 20) to receive from the multi-phase splitter, sample, and hold one of the n RF signals whose phases each differ by the 360 degrees / n, and output the held signal, the n signal paths being connected to the multi-phase splitter, and each signal path including a sample hold element including two switches; a multi-phase synthesizer (4) to synthesize n signals output from the n signal paths, the multi-phase synthesizer (4) being connected to the n signal paths; an output terminal (2) to output the signals to be synthesized by the multi-phase synthesizer; and a clock signal source (21) to output a clock signal (S1) for driving all of switches.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

A system for filter enhancement, preferably including one or more analog taps and a controller, and optionally including one or more couplers. The system is preferably configured to integrate with a filter, such as a passband filter or other frequency-based filter. The system can be configured to integrate with an RF communication system, an RF front end, or any other suitable RF circuitry. A method for filter enhancement, preferably including configuring one or more analog taps, and optionally including calibrating a system for filter enhancement and / or receiving temperature information.

According to a band-pass filter, n represents a natural number equal to or more than one, and the band-pass filter includes: an input terminal to receive an input of an RF signal; a multi-phase splitter to split the RF signal into n RF signals whose phases each differ by 360 degrees / n; n signal paths to receive from the multi-phase splitter, sample, and hold one of the n RF signals, and output the held signal, the n signal paths being connected to the multi-phase splitter, and each signal path including a sample hold element including two switches; a multi-phase synthesizer to synthesize n signals output from the n signal paths, the multi-phase synthesizer being connected to the n signal paths; an output terminal to output the signals to be synthesized by the multi-phase synthesizer; and a clock signal source to output a clock signal for driving all of switches.

The invention relates to a high-precision anti-interference wireless charging current demodulation circuit and method. The CS sampling circuit comprises a sampling resistor, a first amplification unit and a second amplification unit; the input end of the RC low-pass filter circuit is connected with the output end of the CS sampling circuit, and the RC low-pass filter circuit comprises a blocking capacitor, a direct current bias module, a first filter branch and a second filter branch, and the first filter branch and the second filter branch are arranged in parallel; the comparator integrating circuit comprises a comparison circuit and an integrating circuit, and the comparison circuit is connected with the output end of the first filtering branch and the output end of the second filtering branch and receives threshold voltage providing a reversal point; the input end of the anti-peak filter circuit is connected with the output end of the integrating circuit, and the anti-peak filter circuit comprises a first RC time delay circuit, a first phase inverting circuit, a second RC time delay circuit, a second phase inverting circuit and an SR latch which are coupled and connected. According to the invention, the output current decoding waveform has the advantage of power supply disturbance resistance, and the situation that the current decoding is easy to turn over by mistake is avoided.

In many embodiments of the invention, a tap delay line phase detector circuit includes a delay chain including a plurality of delay cells connected in series, each delay cell configured to introduce a predetermined time delay to a reference clock signal, a plurality of registers positioned at tap points along the delay chain, each register configured to sample a delayed version of the reference clock signal after a successive delay cell, a high-speed clock configured to provide timing signals to the plurality of registers, and a plurality of edge detectors configured to analyze outputs from the plurality of registers to determine clock transition timing, wherein the plurality of edge detectors generate edge detection signals that indicate timing relationships between the reference clock signal and the high-speed clock.

Methods, devices, and systems for clock circuit correction. In one aspect, a circuit includes a first input configured to receive a first signal and a second input configured to receive a second signal. The circuit includes a first line coupled to the first input, the first line includes a plurality of first inverters and a second line coupled to the second input, the second line includes a plurality of second inverters. The circuit includes a crossover circuit coupled to the first line at a first node and the second line at a second node. The crossover circuit generates a first correction signal with the first signal from the first node passing through a crossover inverter within the crossover circuit and provides the first correction signal to the second node on the second line to correct the second signal.

The invention is notably directed to a method of processing data. The method relies on a memory device having a crossbar array structure. The latter includes K×L cells, which interconnect K rows and Z columns. The cells include respective memory systems, which store respective A-bit weights. The memory systems are connected to respective compute units, which are configured as interleaved switched-capacitor analogue multipliers and adders. According to the proposed method, input signals encoding respective M-bit input words are synchronously applied to respective ones of the K rows. The compute units are operated according to a 3-phase clocking scheme, with a view to obtaining MAC results for each of the L columns, where K≥2, L>2, N≥2, and M≥2. Remarkably, the 3-phase clocking scheme is here set to perform n×m partial multiplications, in the analogue domain, according to a specific bit partition, so as to obtain n×m partial output signals in output of each of the compute units. This partition decomposes each of the N-bit weights into n groups of bits and each of the M-bit input words into m groups of bits. Each of the n groups and the m groups includes at least one bit. However, at least one of the n groups and / or the m groups includes at least two bits, whereby N+M>n+m≥3. Moreover, the MAC results are obtained by summing the partial output signals obtained by the compute units for each of the Z columns. The summed output signals are converted into digital signals encoding partial values. The partial values are shifted according to corresponding bit positions, which are set in accordance with the bit partition, and the shifted values are finally added, so as to recompose the desired output vector components. The invention is further directed to related apparatuses and systems.

The utility model discloses a spark suppression circuit based on an RC (Resistance-Capacitance) delay network, which comprises a power supply input end positive electrode B +, a power supply input end negative electrode B-, an RC delay network circuit, a power switch circuit, a transistor control circuit and a second capacitor C2, the power input end positive electrode B + is connected with the power input end negative electrode B-through the RC delay network circuit, the power switch circuit comprises a power tube U1 and a power resistor R7, one end of the power resistor R7 is connected with the power input end negative electrode B-, the other end of the power resistor R7 is connected with the D level of the power tube U1, and the G level of the power tube U1 is connected with the power input end positive electrode B + through the transistor control circuit. The D pole of the power tube U1 is connected with a system ground wire PGND, and the S pole of the power tube U1 is connected with the negative pole B-of the power supply input end; the spark phenomenon at the moment of circuit connection can be effectively suppressed, the scheme is simple and reliable, the circuit is more stable and simpler, and the cost is remarkably reduced.

A time delay circuit includes a first port, a second port, a reference path coupled between the first and second ports, a delay path coupled between the first and second ports, and a control circuit configured to activate one of the reference path and the delay path. The reference path includes a series transistor and a first inductor connected in parallel with the series transistor. The delay path includes a first shunt transistor, a second inductor connected in parallel with the first shunt transistor, and a first impedance inverter coupled between the first port and the first shunt transistor.

For critical path monitoring in an integrated circuit (IC), a system includes a data flip-flop configured to receive a data input and a clock input, and generate a first data output and a first clock output. A data delay path generates a delayed data output. An output flip-flop, coupled to the data delay path generates a second data output and a second clock output. A time-to-digital converter (TDC), coupled to the data delay path, includes a comparator bank that compares the delayed data output against reference levels and generates a code. An encoder, coupled to the comparator bank converts the code into a binary code representing the time delay. A minimum delay search coupled to the TDC includes a control circuit, configured to dynamically adjust the supply voltage and other parameters of the IC based on the timing margins and delay settings identified by the minimum delay search.