35results about "Time-delay networks" patented technology

The invention relates to the technical field of delay module design, in particular to a multi-channel broadband radio frequency signal delay device and method, and the method comprises the steps: sampling an input multi-channel broadband radio frequency signal, converting an analog signal into a digital signal, carrying out the filtering of the sampled digital signal, and outputting a filtered signal; screening out a frequency component of a target frequency band; converting the filtered digital signals into two paths of I / Q complex digital signals; writing the converted two paths of I / Q complex digital signals into a synchronous FIFO (First In First Out) storage module in an AXIS flow form; performing interpolation processing on the two I / Q complex digital signals read from the FIFO storage module; and IQ modulation is carried out on the digital signal after interpolation processing, and the digital signal is converted into an analog radio frequency signal to be output. Accurate control of multi-channel broadband radio frequency signal delay is realized, and strict requirements on signal delay precision in different application scenes can be met.

Enhanced Bucket Brigade Delay (BBD) circuits which more readily support cascaded configurations. A gain control mechanism is utilized in combination with an attenuation coupling network between subsequent BBD stages to achieve significantly longer delays than are achievable by the single BBD device, without introducing excessive noise or increased power dissipation associated with the need of reconstructing and biasing the intermediate signal between BBD devices.

Enhanced Bucket Brigade Delay (BBD) circuits which more readily support cascaded configurations. A gain control mechanism is utilized in combination with an attenuation coupling network between subsequent BBD stages to achieve significantly longer delays than are achievable by the single BBD device, without introducing excessive noise or increased power dissipation associated with the need of reconstructing and biasing the intermediate signal between BBD devices.

A system for filter enhancement, preferably including one or more analog taps and a controller, and optionally including one or more couplers. The system is preferably configured to integrate with a filter, such as a passband filter or other frequency-based filter. The system can be configured to integrate with an RF communication system, an RF front end, or any other suitable RF circuitry. A method for filter enhancement, preferably including configuring one or more analog taps, and optionally including calibrating a system for filter enhancement and / or receiving temperature information.

The invention belongs to the technical field of integrated circuits, and particularly relates to a broadband low-amplitude error delayer. The delayer comprises an input matching network, an output matching network, a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a delay reference network, the input matching network is connected with one end of the first single-pole double-throw switch, and the other end of the first single-pole double-throw switch is connected with the input end of the delay unit and the input end of the delay reference network. One end of the second single-pole double-throw switch is connected with the output matching network, and the other end is connected with the input end of the delay unit and the output end of the delay reference network; the delayer designed by the invention has a wide-band large-frequency delay function, and has a good application prospect.

The present invention relates to the field of beamforming integrated circuits, and provides a hybrid multi-beamforming circuit structure, including: a power divider, receiving a first data stream for dividing the first data stream into a plurality of second data streams; and a power combiner, receiving the second data streams and combining the plurality of second data streams into a third data stream, where an input port of an FTVAP circuit is connected to an output port of the power divider, and an output port of the FTVAP circuit is connected to an input port of the power combiner, to control an amplitude, a phase, and time delay of the second data streams. A BTVAP circuit is connected to an input port of the power divider to control an amplitude, a phase, and time delay of the first data stream, or the BTVAP circuit is connected to an output port of the power combiner to control an amplitude, a phase, and time delay of the third data stream. The present invention is provided with a simple and proper structure, greatly improving an integration degree and reducing costs. The present invention is used in a phased array, implementing multi-beamforming and beam scanning.

A system for reducing clock jitter may include first jitter reducing circuitry. The first jitter reducing circuitry may be arranged between an input clock signal node carrying an input clock signal and an output clock signal node carrying an output clock signal. The first jitter reducing circuitry may include a first intermediate input clock signal node and a first intermediate output clock signal node. The first jitter reducing circuitry may include a first clock delay circuit, which may be configured to: (1) delay a first intermediate input clock signal received on the first intermediate input clock signal node by an odd integer multiple of one half of a period, and (2) invert the first intermediate input clock signal. The first jitter reducing circuitry may also include a first connection, which may be from the first intermediate output clock signal node to the first intermediate input clock signal node.

The invention discloses a multi-channel amplitude-phase delay control device, and particularly relates to the field of multi-channel signal control. Comprising at least two radio frequency link units used for performing amplitude phase delay processing on an input radio frequency signal to obtain an analog signal; the input end of the synthesis link unit is connected with all the radio frequency link units, and the synthesis link unit is used for synthesizing all the analog signals to obtain a synthesis signal; the input end of the monitoring unit is connected with the synthesis link unit, and the monitoring unit is used for dividing the synthesis signal into an output signal and a coupling signal and converting the coupling signal into a digital signal; the output end of the logic processing unit is respectively connected with the radio frequency link unit, the monitoring unit and the synthesis link unit, and the logic processing unit is used for correspondingly converting the control instruction into control signals of the radio frequency link unit, the monitoring unit and the synthesis link unit; the input end of the logic processing unit is connected with the output end of the monitoring unit and used for adjusting the control signal according to the digital signal. And the control precision can be improved.

The present invention relates to the field of beam forming integrated circuits. Provided is a hybrid multi-beam forming circuit structure. The structure comprises: a power divider, which receives a first data stream and equally divides the first data stream into a plurality of second data streams; a power combiner, which receives the second data streams and combines the plurality of second data streams into a third data stream; a fine-tuning-with-VAP circuit, wherein an input end thereof is connected to an output end of the power divider, an output end thereof is connected to an input end of the power combiner, and the fine-tuning-with-VAP circuit is configured to control the amplitude, phase and time delay of each second data stream; and a beam-tuning-with-VAP circuit, which is connected to an input end of the power divider and is configured to control the amplitude, phase and time delay of the first data stream, or is connected to an output end of the power combiner and is configured to control the amplitude, phase and time delay of the third data stream. The structure of the present invention is simple and rational, thereby greatly improving the integration level and reducing costs; and the present invention is applied to a phased array, thereby realizing multi-beam forming and beam scanning.

An integrated circuit includes a clock input pad that receives a clock signal from an external source. The integrated circuit includes a core logic and an input driver coupled between the clock input pad and the core logic and configured to provide the clock input signal to the core logic. The input driver includes a filter including a plurality of inverter stages coupled in series. The input driver includes an NMOS capacitor coupled between a first pair of the inverter stages. The input driver includes a PMOS capacitor coupled between a second pair of the inverter stages.

According to a band-pass filter, n represents a natural number equal to or more than one, and the band-pass filter includes: an input terminal (1) to receive an input of an RF signal; a multi-phase splitter (3) to split the RF signal input to the input terminal into n RF signals whose phases each differ by 360 degrees / n; n signal paths (17 to 20) to receive from the multi-phase splitter, sample, and hold one of the n RF signals whose phases each differ by the 360 degrees / n, and output the held signal, the n signal paths being connected to the multi-phase splitter, and each signal path including a sample hold element including two switches; a multi-phase synthesizer (4) to synthesize n signals output from the n signal paths, the multi-phase synthesizer (4) being connected to the n signal paths; an output terminal (2) to output the signals to be synthesized by the multi-phase synthesizer; and a clock signal source (21) to output a clock signal (S1) for driving all of switches.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

The invention relates to a method and apparatus for reducing filter delay spread in an interface IP. The integrated circuit includes a clock input board that receives a clock signal from an external source. The integrated circuit includes a core logic and an input driver coupled between a clock input pad and the core logic and configured to provide a clock input signal to the core logic. The input driver includes a filter including a plurality of inverter stages coupled in series. The input driver includes an NMOS capacitor coupled between the first pair of inverter stages. The input driver includes a PMOS capacitor coupled between the second pair of inverter stages.

A system for filter enhancement, preferably including one or more analog taps and a controller, and optionally including one or more couplers. The system is preferably configured to integrate with a filter, such as a passband filter or other frequency-based filter. The system can be configured to integrate with an RF communication system, an RF front end, or any other suitable RF circuitry. A method for filter enhancement, preferably including configuring one or more analog taps, and optionally including calibrating a system for filter enhancement and / or receiving temperature information.

The invention is notably directed to a method of processing data. The method relies on a memory device having a crossbar array structure. The latter includes K×L cells, which interconnect K rows and Z columns. The cells include respective memory systems, which store respective A-bit weights. The memory systems are connected to respective compute units, which are configured as interleaved switched-capacitor analogue multipliers and adders. According to the proposed method, input signals encoding respective M-bit input words are synchronously applied to respective ones of the K rows. The compute units are operated according to a 3-phase clocking scheme, with a view to obtaining MAC results for each of the L columns, where K≥2, L>2, N≥2, and M≥2. Remarkably, the 3-phase clocking scheme is here set to perform n×m partial multiplications, in the analogue domain, according to a specific bit partition, so as to obtain n×m partial output signals in output of each of the compute units. This partition decomposes each of the N-bit weights into n groups of bits and each of the M-bit input words into m groups of bits. Each of the n groups and the m groups includes at least one bit. However, at least one of the n groups and / or the m groups includes at least two bits, whereby N+M>n+m≥3. Moreover, the MAC results are obtained by summing the partial output signals obtained by the compute units for each of the Z columns. The summed output signals are converted into digital signals encoding partial values. The partial values are shifted according to corresponding bit positions, which are set in accordance with the bit partition, and the shifted values are finally added, so as to recompose the desired output vector components. The invention is further directed to related apparatuses and systems.

According to a band-pass filter, n represents a natural number equal to or more than one, and the band-pass filter includes: an input terminal to receive an input of an RF signal; a multi-phase splitter to split the RF signal into n RF signals whose phases each differ by 360 degrees / n; n signal paths to receive from the multi-phase splitter, sample, and hold one of the n RF signals, and output the held signal, the n signal paths being connected to the multi-phase splitter, and each signal path including a sample hold element including two switches; a multi-phase synthesizer to synthesize n signals output from the n signal paths, the multi-phase synthesizer being connected to the n signal paths; an output terminal to output the signals to be synthesized by the multi-phase synthesizer; and a clock signal source to output a clock signal for driving all of switches.

The invention aims to provide a Preisach type hysteresis compensation circuit of a functional material device, which belongs to the technical field of functional material devices, and comprises a finite number of P operator equivalent circuit modules established by referring to a Preisach model based on the inverse hysteresis characteristic of the functional material device, a first reverse adder, a first reverse module, a second reverse adder, a second reverse module and a third reverse adder; wherein half of the P operator equivalent circuit module is connected in parallel with the first reverse adder to form a first branch; one end of the parallel structure of the remaining P operator equivalent circuit modules is connected with the first reverse module, and the other end is sequentially connected with the second reverse adder and the second reverse module to form a second branch; and connecting the first branch and the second branch in parallel to a third reverse adder to obtain the Preisach type hysteresis compensation circuit of the functional material device. According to the invention, the energy consumption can be effectively reduced, and the requirement of carbon emission reduction is met.

The invention relates to a high-precision anti-interference wireless charging current demodulation circuit and method. The CS sampling circuit comprises a sampling resistor, a first amplification unit and a second amplification unit; the input end of the RC low-pass filter circuit is connected with the output end of the CS sampling circuit, and the RC low-pass filter circuit comprises a blocking capacitor, a direct current bias module, a first filter branch and a second filter branch, and the first filter branch and the second filter branch are arranged in parallel; the comparator integrating circuit comprises a comparison circuit and an integrating circuit, and the comparison circuit is connected with the output end of the first filtering branch and the output end of the second filtering branch and receives threshold voltage providing a reversal point; the input end of the anti-peak filter circuit is connected with the output end of the integrating circuit, and the anti-peak filter circuit comprises a first RC time delay circuit, a first phase inverting circuit, a second RC time delay circuit, a second phase inverting circuit and an SR latch which are coupled and connected. According to the invention, the output current decoding waveform has the advantage of power supply disturbance resistance, and the situation that the current decoding is easy to turn over by mistake is avoided.

In many embodiments of the invention, a tap delay line phase detector circuit includes a delay chain including a plurality of delay cells connected in series, each delay cell configured to introduce a predetermined time delay to a reference clock signal, a plurality of registers positioned at tap points along the delay chain, each register configured to sample a delayed version of the reference clock signal after a successive delay cell, a high-speed clock configured to provide timing signals to the plurality of registers, and a plurality of edge detectors configured to analyze outputs from the plurality of registers to determine clock transition timing, wherein the plurality of edge detectors generate edge detection signals that indicate timing relationships between the reference clock signal and the high-speed clock.

Methods, devices, and systems for clock circuit correction. In one aspect, a circuit includes a first input configured to receive a first signal and a second input configured to receive a second signal. The circuit includes a first line coupled to the first input, the first line includes a plurality of first inverters and a second line coupled to the second input, the second line includes a plurality of second inverters. The circuit includes a crossover circuit coupled to the first line at a first node and the second line at a second node. The crossover circuit generates a first correction signal with the first signal from the first node passing through a crossover inverter within the crossover circuit and provides the first correction signal to the second node on the second line to correct the second signal.

This bandpass filter comprises: an input terminal (1) that receives an RF signal as an input; a multi-phase distributor (3) that divides the RF signal input to the input terminal into n RF signals having phases differing by 360 deg / n, where n is a natural number greater than or equal to 1; n signal paths (17-20) that are connected to the multi-phase distributor and each have a sample-and-hold element with two switches, each of the n signal paths sampling and holding one of the n RF signals with phases differing by 360 deg / n from the multi-phase distributor and outputting the held signal; a multi-phase synthesizer (4) that is connected to the n signal paths and synthesizes n signals output from the n signal paths; an output terminal (2) that outputs a signal obtained by the synthesizing by the multi-phase synthesizer; and a clock signal source (21) that outputs a clock signal (S1) that drives all the switches.

Various embodiments of a precise programming algorithm and apparatus for precisely and rapidly depositing the correct amount of charge on floating gates of non-volatile memory cells within a vector-matrix multiplication (VMM) array in an artificial neural network are disclosed. Accordingly, the selected cell can be programmed very precisely to maintain one of the N different values.

The application provides a kind of ultra-wideband small size low insertion loss reconfigurable radio frequency delay ware, it is related to the technical field of delay ware chip, including two switchable adjustable attenuation units and multiple adjustable delay units connected together;The input end of the first switchable adjustable attenuation unit is the radio frequency input end, and the output end of the second switchable adjustable attenuation unit is the radio frequency output end, and multiple adjustable delay units are connected between the first switchable adjustable attenuation unit and the second switchable adjustable attenuation unit;The switchable adjustable attenuation unit adopts MOS tube switch array, and the MOS tube switch array includes n MOS tubes with different widths in parallel, and the adjustment of attenuation and impedance is realized by switching the MOS tube switch array;The adjustable delay unit adopts T type Π type combination LC network.The application has the advantages of expanding the working frequency band, reducing the insertion loss of large delay and reducing the area.

The invention is notably directed to a method of processing data. The method relies on a memory device having a crossbar array structure. The latter includes K×L cells, which interconnect K rows and Z columns. The cells include respective memory systems, which store respective A-bit weights. The memory systems are connected to respective compute units, which are configured as interleaved switched-capacitor analogue multipliers and adders. According to the proposed method, input signals encoding respective M-bit input words are synchronously applied to respective ones of the K rows. The compute units are operated according to a 3-phase clocking scheme, with a view to obtaining MAC results for each of the L columns, where K≥2, L>2, N≥2, and M≥2. Remarkably, the 3-phase clocking scheme is here set to perform n×m partial multiplications, in the analogue domain, according to a specific bit partition, so as to obtain n×m partial output signals in output of each of the compute units. This partition decomposes each of the N-bit weights into n groups of bits and each of the M-bit input words into m groups of bits. Each of the n groups and the m groups includes at least one bit. However, at least one of the n groups and / or the m groups includes at least two bits, whereby N+M>n+m≥3. Moreover, the MAC results are obtained by summing the partial output signals obtained by the compute units for each of the Z columns. The summed output signals are converted into digital signals encoding partial values. The partial values are shifted according to corresponding bit positions, which are set in accordance with the bit partition, and the shifted values are finally added, so as to recompose the desired output vector components. The invention is further directed to related apparatuses and systems.

The utility model discloses a spark suppression circuit based on an RC (Resistance-Capacitance) delay network, which comprises a power supply input end positive electrode B +, a power supply input end negative electrode B-, an RC delay network circuit, a power switch circuit, a transistor control circuit and a second capacitor C2, the power input end positive electrode B + is connected with the power input end negative electrode B-through the RC delay network circuit, the power switch circuit comprises a power tube U1 and a power resistor R7, one end of the power resistor R7 is connected with the power input end negative electrode B-, the other end of the power resistor R7 is connected with the D level of the power tube U1, and the G level of the power tube U1 is connected with the power input end positive electrode B + through the transistor control circuit. The D pole of the power tube U1 is connected with a system ground wire PGND, and the S pole of the power tube U1 is connected with the negative pole B-of the power supply input end; the spark phenomenon at the moment of circuit connection can be effectively suppressed, the scheme is simple and reliable, the circuit is more stable and simpler, and the cost is remarkably reduced.

A time delay circuit includes a first port, a second port, a reference path coupled between the first and second ports, a delay path coupled between the first and second ports, and a control circuit configured to activate one of the reference path and the delay path. The reference path includes a series transistor and a first inductor connected in parallel with the series transistor. The delay path includes a first shunt transistor, a second inductor connected in parallel with the first shunt transistor, and a first impedance inverter coupled between the first port and the first shunt transistor.

The invention discloses a biological filter circuit capable of shortening stabilization time, and belongs to the field of signal filter circuits. The biological filter circuit provided by the invention is composed of a detection circuit, a time delay circuit, a selection circuit and an analog filter. According to the circuit, two filters which can be switched to work and are different in cut-off frequency are arranged in an analog filter, through cooperation of a detection circuit, a time delay circuit and a selection circuit, when signal input is detected, the filter with the high cut-off frequency is used for rapidly stabilizing signals, and after the filters are stabilized, the filter is switched to the filter with the low cut-off frequency through a switch; and the cut-off frequency is shifted to a frequency interval suitable for detecting the biological signal, so that the stable reaching time of the filter is shortened. The biological filter circuit has a good noise suppression effect on biological signals.

The invention provides an ultra-wide-band small-size low-insertion-loss reconfigurable radio frequency delayer, and relates to the technical field of delayer chips, and the ultra-wide-band small-size low-insertion-loss reconfigurable radio frequency delayer comprises two switch switching adjustable attenuation units and a plurality of adjustable delay units which are connected in series; the input end of the first switching adjustable attenuation unit is a radio frequency input end, the output end of the second switching adjustable attenuation unit is a radio frequency output end, and the plurality of adjustable delay units are connected in series between the first switching adjustable attenuation unit and the second switching adjustable attenuation unit; the switch-switching adjustable attenuation unit adopts an MOS tube switch array, the MOS tube switch array comprises n MOS tubes which are connected in parallel and have different widths, and the adjustment of attenuation and impedance is realized by performing switch-switching on the MOS tube switch array; and the adjustable delay unit adopts a T-shaped and n-shaped combined LC network. The invention has the advantages of expanding the working frequency band, reducing the insertion loss of large time delay and reducing the area.