144 results about "Clock tree" patented technology

The invention discloses an RFSOC-based FAST core array distributed collaborative observation and data fusion method and system, and the method comprises the steps: S1, system initialization: a master node RFSOC generates a global clock, achieves the phase synchronization of multiple board cards through an SYSREF differential signal, and completes the calibration of a three-stage clock tree; s2, signal acquisition and preprocessing: directly sampling a 3-8GHz radio frequency signal through an ADC (Analog to Digital Converter), and performing digital down-conversion to obtain a baseband signal; s3, intelligent resource scheduling: identifying a signal type based on an ESN (Echo State Neural Network), and dynamically allocating FPGA logic resources through an improved ant colony algorithm; s4, heterogeneous calculation acceleration: executing a 128-channel digital beam forming pipeline on the FPGA; s5, cross-domain data fusion; s6, collaborative observation planning; and S7, outputting data. The method is suitable for multi-beam synthesis, cross-region joint observation and mass data real-time processing scenes, and provides key technical support for solving the frontier scientific problems such as rapid radio storm origin and black hole activity monitoring.

The invention relates to the technical field of high-speed digital interfaces, and discloses a JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation, and the system comprises a main node which generates and dynamically distributes clock signals, and constructs a dynamic clock tree structure; the slave equipment is used for realizing cascade error elimination through a distributed compensation mechanism; the dynamic phase compensation engine adopts a hybrid phase detection framework and is combined with a digital-to-time converter (TDC) and an analog phase-locked loop (PLL); and the environment parameter compensation module is used for collecting temperature, voltage and operation time in real time, and calculating phase compensation quantity through a formula that delta phi = alpha * (T-T0) + beta * (V-V0) + gamma * delta t. On the aspect of synchronization precision, the phase error of a single device can be smaller than or equal to + / -200ps, the strict scene requirement is effectively met, the environment adaptability is high, the defects of traditional fixed compensation can be overcome, cascade error accumulation can be efficiently restrained through distributed compensation of slave devices, and on the aspect of real-time performance, an online calibration module can conduct real-time calibration without interrupting services.

The invention discloses a Multi-Point CTS-based chip clock design optimization method, and relates to the technical field of chip clock design optimization, and the method comprises the following steps: using a hardware description language VHDL to compile RTL codes describing circuit behaviors, using a DC EDA tool of Synopsys to convert the RTL codes into a logic netlist, using a standard algorithm H-Tree to construct a preliminary clock tree structure layout, and using the standard algorithm H-Tree to construct the logic netlist. Obtaining a primary clock tree topological graph; a Multi-Point CTS method is introduced, a plurality of clock sources are adopted to optimize the initial clock tree topological graph, and an optimized clock tree topological graph is obtained; a static time sequence analysis tool PrimeTime is adopted to analyze the optimized clock tree topological graph, and a time sequence analysis result is obtained; identifying the longest path from a clock source to a register in the optimized clock tree topological graph according to a time sequence analysis result, marking the longest path as a critical path, and finding the optimal position for placing a buffer in the critical path by adopting a heuristic search algorithm; and calculating a difference value between the actual delay and the maximum allowable delay of the optimized clock tree topological graph by using PrimeTime again.

The invention discloses a time sequence convergence method and device based on a clock tree, and relates to the technical field of circuit design. The method comprises the following steps: performing automatic layout on devices; determining a time sequence path needing to be optimized in the one-to-many structure time sequence path; performing establishment time sequence margin optimization, and determining a setting pattern of useful clock skew adjustment based on the optimized establishment time sequence margin; determining the number of buffers based on the setting pattern of useful clock skew adjustment and the optimized setup time sequence margin, and generating a clock tree; on the basis of the generated clock tree, determining whether the time sequence violation of the retention time of the time sequence path needing to be optimized meets a preset requirement or not, and if the preset requirement is not met, adjusting the setting pattern of the useful clock skew adjustment, and returning to the step of generating the clock tree; and completing automatic wiring based on the clock tree meeting the predetermined requirement. According to the invention, the problem of power consumption increase caused by restoration of Hold time sequence violation can be solved.

The invention provides a clock tree verification method and device, a computer readable storage medium and computing device.The clock tree verification method comprises the steps that a connection reference model is constructed, and the connection reference model comprises information of clocks in a clock tree, the connection relation between the clocks and the initial value of a control signal; the information of the clock comprises a reference period and a reference burr expected value of the clock, and each control signal is used for controlling a connection relation between at least one clock; randomly updating the value of the at least one control signal, and updating the reference period and the reference burr expected value according to the updated value of the at least one control signal; and detecting each clock according to the updated reference period and the reference burr expected value. The invention provides a scheme for improving clock tree verification convenience and accuracy.

A clock distribution network includes an input control circuit and a clock tree. The input control circuit is configured to generate a control input clock signal based on an input clock signal and a low power mode signal. The clock tree is configured to generate an output clock signal by buffering the control input clock signal. When the low power mode signal is enabled, the input control circuit is configured to change a DC level of the control input clock signal.

The embodiment of the invention provides a clock calibration circuit. The circuit comprises a first sampling circuit; the second sampling circuit is connected with the first sampling circuit in series; the first sampling circuit comprises a phase-locked loop (PLL); a first duty cycle calibrator DCC connected in series with the PLL; a first phase interpolator PI connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmission driver connected in series with the first data serializer; the first data serializer is connected with the first DCC in series, the second data serializer is connected with the first DCC in series, the second sending driver is connected with the second data serializer in series, and the PLL is used for outputting a clock signal so as to drive the first data serializer to send data to be sent to the first sending driver and drive the second data serializer to send a feedforward clock signal to the second sending driver; and the second sending driver is used for sending the feed-forward clock signal to the first receiving driver of the second sampling circuit so as to determine the feed-forward clock signal as a sampling clock of the second sampling circuit.

The invention relates to a satellite-borne super-large-scale digital phased array system based on a JESD204B clock synchronization network, and the system comprises a radio frequency antenna layer which is used for receiving and transmitting electromagnetic waves in a space, and completing the mutual conversion of a radio frequency signal and a space electromagnetic wave; the sub-array baseband layer is used for realizing S-band 64-path intermediate frequency signal sampling, transmitting and digital domain multi-beam synthesis in a transceiving link, realizing data transmission with the mother board clock layer, and completing a reconstruction function of a baseband module signal processing FPGA (Field Programmable Gate Array) through a low-speed interface; the mother board clock layer serves as a function of realizing data summarization and distribution and performs task scheduling and management on the whole digital phased array system, and a JESD204B clock tree network is designed in the board and is distributed to a synchronous clock of each baseband module so as to indicate a target signal to complete synchronous sampling and emission output. By adopting the system, access, efficient tracking and accurate pointing of massive ground users can be realized.

The invention discloses a clock tree comprehensive optimization method and system based on layered region division and buffer insertion, and the method carries out the clock tree comprehensive optimization through a layered buffer insertion mode, and comprises the steps: firstly, taking all registers as basic units, carrying out the rectangular region cutting of a circuit, and inserting a bottom buffer at a geometric center point; then taking the upper layer buffer as a basic unit, dividing a circuit area by using a rhombus grid division method, inserting a middle layer buffer at a geometric center point, and finally inserting a top layer buffer according to an H-tree structure; after the buffers are inserted, the positions of the buffers are dynamically adjusted, so that delay minimization and deflection control of the global clock tree are achieved, meanwhile, the number of the buffers is effectively reduced, power consumption is reduced, and design efficiency is improved.

The invention discloses a PCIe interface chip layout and wiring method, and belongs to the field of chip design automation. In order to reduce adverse effects of Setup violation and Hold violation on chip performance, when physical layout arrangement of a PCIe interface chip is placed and a clock tree is synthesized, an IP core receiving side interface signal and register information associated with an IP core internal receiving side are captured, and a register associated with the IP core internal receiving side is placed according to the IP core direction, so that the chip performance is improved. And according to the delay length of the data path of the receiving side interface in the IP core, the delay length of the clock path of the receiving side interface in the IP core, and the delay length of the data path between the registers associated with the receiving side in the IP core, constraining the clock length of the registers associated with the receiving side. The method is applied to the field of chip design, and the chip has better performance and power consumption and smaller area.

A method may include generating a first clock path, wherein a first clock control logic (CCL) is connected between a mesh and a first sequential gate. The method may include disconnecting the first CCL from the first sequential gate in the first clock path, and connecting the mesh to the first sequential gate, and generating a second clock path, wherein the mesh is connected to a second CCL. The method may include generating a first clock tree in the first clock path, the first clock tree being connected to the first sequential gate, and connecting the first CCL between the mesh and the first clock tree. Finally, the method may include generating a second clock tree in the second clock path between the second CCL and a second sequential gate.

The invention relates to the technical field of electronic design automation, in particular to a concurrent clock optimization and data optimization method and tool, computer equipment, a medium and a program. The concurrent clock optimization and data optimization method comprises the following steps: providing a clock optimizer, and constructing a clock tree; initial skew on the clock tree is obtained, and the clock optimizer carries out balance processing on the clock tree based on the initial skew, so that the clock tree obtains useful skew; integrating the clock optimizer and the data optimizer to obtain a concurrent optimizer; and simultaneously performing data optimization on the balanced clock tree by using a concurrent optimizer, and performing clock optimization on the balanced clock tree based on the useful skew. The problem that an existing optimization tool is poor in clock tree optimization efficiency is solved.

The invention aims to provide a method for relieving on-chip voltage drop by reserving low-layer metal wiring resources in a power supply network. The method comprises the following steps: reserving a deployment area of bottom-layer metal resources in a chip layout stage; correcting the deployment area; and using the metal resources in the deployment area according to a chip analysis result after wiring is completed. In the layout wiring and clock tree synthesis stage, the low-layer metal wiring resources are reserved to be used for communicating the power supply tracks of the adjacent standard units, so that the problem that the voltage drop exceeds the standard due to overlarge low-layer metal resistance is effectively relieved by flexibly starting the reserved wiring resources in the later stage of chip design.

The invention provides a time sequence optimization method and device for convergence preposition, equipment, a medium and a product, and relates to the technical field of computers, in particular to the field of artificial intelligence and chips. According to the specific implementation scheme, all modules are combined into subsystems in a lightweight manner for time sequence analysis, and a cross-module time sequence violation path is obtained; performing path grouping on each cross-module time sequence violation path to obtain at least one path group; according to the time violation value of each cross-module time sequence violation path, allocating a repair weight to each path packet; determining a delay constraint compensation value of each path group according to an actual routing value of each cross-module time sequence violation path in the path end point module; according to each time delay constraint compensation value, each repair weight and the boundary constraint information and clock tree intervention information of the high-repair-level module, a subsystem-level optimization script is generated, and module-level layout and wiring optimization is carried out, so that the time sequence performance and reliability of chip design are improved, later large-scale modification is avoided, and the design efficiency is improved.

The disclosed device includes various circuit blocks and a clock tree for sending a clock signal to the circuit blocks. The clock tree includes various clock drivers. The device also includes a control circuit that power gates, in response to one of the circuit blocks being power gated, a portion of the clock tree that includes one of the clock drivers. Various other methods, systems, and computer-readable media are also disclosed.

The invention relates to the technical field of industrial automation control, in particular to a data acquisition method and system based on a digital metering technology, and the method sequentially comprises the following steps: 1, carrying out the dynamic calibration of a sensor; 2, constructing a phase compensation clock tree; 3, establishing a temperature-humidity-vibration three-factor coupled error compensation model, determining the interaction weight of each factor through an orthogonal test method, and updating a compensation coefficient on line by adopting a recursive least square method with a forgetting factor; and step 4, generating a transmission priority according to the product of the data change rate and the health degree index, dynamically allocating a transmission bandwidth based on a network quality evaluation value calculated based on the time delay change rate and the packet loss rate, and performing compressed coding of a lead code mark on high-priority data. The method not only improves the precision of the system, but also optimizes the data processing and transmission efficiency, and provides an effective solution for high-precision data acquisition in a large-scale and complex environment.

The invention provides a gated clock circuit, a chip and electronic equipment. The gated clock circuit comprises a signal control module and a clock tree module, the signal control module generates a clock tree signal according to a source clock signal and input signals and output signals of all the single-bit D triggers; the clock tree module generates a plurality of sub-clock signals according to the clock tree signal; when the input signals and the output signals of all the single-bit D triggers are the same, the generated clock tree signal prevents the propagation of the source clock signal; when the input signal and the output signal of any single-bit D trigger are different, the generated clock tree signal enables the clock tree module to generate a plurality of sub-clock signals. The working state of the clock tree module is controlled through the signal control module, so that when the single-bit D flip-flop does not work, the clock tree module stops clock propagation, dynamic power consumption generated by clock flip-flop is saved, and the problem of how to reduce the dynamic power consumption generated by the single-bit D flip-flop in a chip is solved.

A clock tree 900 comprises a first clock buffer 906 electrically connected to a second clock buffer 910. The first clock buffer comprises a first transistor 972, a second transistor 974, a first resis

The invention provides a python-based clock tree visualization implementation method and system, and relates to the technical field of integrated circuits, and the method comprises the steps: reading an sdc file, extracting all clock information according to a grammar rule of the sdc file, and storing the clock information into a first dictionary according to names; reading the netlist, obtaining port information of all modules, and storing the port information into a second dictionary according to the names of the modules; reading a file of the library file, extracting port information of each module, and supplementing the port information to a second dictionary; all clock paths in the sdc are traced, and a fourth dictionary only containing all clock paths is generated; according to the fourth dictionary, dividing and drawing a port connection relationship in each module according to the modules, and forming a circuit diagram of each module; and developing a graphical interface for displaying the drawn circuit diagram, and setting functional keys in the interface. According to the method, a complete clock path and an integrally designed clock structure can be presented, a graphical interface can be provided, and the clock structure and the clock path can be visually viewed.

Methods, systems, and devices for techniques for clock coordination with reduced power and latency at a memory system are described. The described techniques provide for a memory system to delay the initiation of a decoding clock at the origin of a clock tree. For example, the memory system may initiate a command / address (CA) clock at a first time corresponding to reception of a CS signal, and may initiate the decoding clock at a second time following the first time by one or more unit intervals of the internal clock. Further, the described techniques provide for the memory system to buffer a first set of CA and buffer a second set of the CA bits according to respective unit intervals of the CA clock such that all the CA bits may be decoded at the decoder according to a single edge of the decoding clock.

A photoelectric conversion device is provided. The device includes a pixel array in which pixels are arranged, a drive controller configured to drive the pixel array, a horizontal transfer unit configured to sequentially output analog signals respectively output from columns of the pixel array, an AD converter configured to convert an analog signal output from the horizontal transfer unit into a digital signal, a first clock generator configured to generate a clock signal used to control an operation of the drive controller, and a second clock generator configured to generate a clock signal used to control the horizontal transfer unit and the AD converter. A clock tree in which a clock signal is distributed from the first clock generator and a clock tree in which a clock signal is distributed from the second clock generator form clock trees different from each other.

The invention discloses a gated clock conversion method, device and system for realizing a double-edge clock selection circuit based on a frequency multiplication clock. The method comprises the following steps: acquiring design information of a to-be-converted circuit; generating a frequency multiplication clock signal based on the clock input signal; constructing a combinational logic circuit; constructing a clock enabling generation logic based on the frequency multiplication clock signal, the post comb, the pre comb, the gating signal and the edge selection signal; a clock input terminal of the timing device is connected to the frequency multiplication clock signal, and an output of the clock enable generation logic is connected to a clock enable terminal of the timing device. According to the invention, the output of the combinational logic driven by the frequency multiplication clock sampling frequency dividing circuit is utilized, so that the function of selecting the rising edge and the falling edge is realized on the clock enabling pin of the register, the clock tree on the register is very clean, the higher frequency on an FPGA (Field Programmable Gate Array) is realized, and the hold timing is easier to converge.

The application discloses a kind of integrated circuit clock tree optimization method and system based on graph neural network and reinforcement learning, comprising the following steps: step S1: construct graph structure generation module, according to integrated circuit layout to construct the graph structure with register as node, with timing path as edge;Step S2: construct GNN feature extraction module, for the high-dimensional graph embedding representation of the feature vector of register node according to the graph structure constructed;Step S3: construct reinforcement learning network decision module, for receiving current node embedding representation vector and generating specific action after data processing;Step S4: construct timing verification and reward calculation module, for evaluating the updated circuit state, and obtaining reward signal to be used for the training of reinforcement learning network decision module;Step S5: constantly train reinforcement learning network decision module, until training is completed, finally obtain optimized register node feature vector, that is, optimized clock tree.

The invention discloses a partition-based multi-thread clock tree construction method, and belongs to the field of integrated circuits. Dividing according to the modules, the positions and the number of loads; executing the insertion of a buffer, and dividing the clock tree into an upper part and a lower part; wherein the upper sub-tree is from a root node of the clock tree to a newly inserted buffer, and the lower sub-tree is from the newly inserted buffer to a real clock tree load; the division is used as multiple threads, a buffer is used as a root node of a lower sub-tree, and the multiple threads are established to respectively process construction and balance of the tree; and processing the upper sub-tree, taking the next level of the buffer as a temporary load of the upper sub-tree so as to optimize the buffer of the upper sub-tree, and adding the maximum delay of the sub-tree corresponding to the root node of the clock tree in the current upper sub-tree to the delay of the buffer. According to the multi-thread method, the higher speed-up ratio is obtained, and meanwhile good consistency with a single-thread result is maintained.

The invention relates to a chip design index generation model training method and device and computer equipment. The method comprises the following steps: acquiring a physical design parameter configuration set; respectively inputting each physical design parameter configuration into a layout analysis tool, a clock tree analysis tool and a wiring analysis tool to obtain a chip design index; generating a new physical design parameter configuration and a new physical design parameter configuration set according to the chip design indexes; returning to execute the step of respectively inputting each physical design parameter configuration into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool until the chip design index corresponding to any physical design parameter configuration meets the preset index requirement, and obtaining a target chip design index; and according to the target chip design index and the corresponding physical design parameter configuration, determining a training sample, and training a chip design index generation model by using the training sample. By adopting the method, the chip design efficiency can be improved.

In some aspects, a device includes a gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal. The device further includes a switching circuit having an output, wherein the switching circuit is configured to switch a logic state at the output of the switching circuit based on the enable signal. The device further includes a multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, and the second input of the multiplexer is coupled to the output of the switching circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal and couple the selected one of the first input and the second input to the output of the multiplexer.

A processing device identifies a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution. The processing device further identifies one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution. In addition, the processing device receives a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies, and generates the circuit design according to the selection.

Embodiments of the present disclosure provide a method and apparatus for evaluating a clock tree, a device and a storage medium. The method comprises: on the basis of a set of structural parameters for a plurality of portions of a clock tree, automatically determining a candidate clock tree structure for the clock tree, wherein each structural parameter in the set of structural parameters is used for defining a structure of one of the plurality of portions; obtaining circuit configuration information associated with the candidate clock tree structure, wherein the circuit configuration information indicates a connection relationship between circuit units in the candidate clock tree structure; and based at least on the circuit configuration information, determining the clock performance of the candidate clock tree structure. Therefore, automatic evaluation and verification of a clock tree design can be realized.

The application relates to the technical field of integrated circuits and provides a built-in self-test circuit and method for a chip. The circuit comprises a control bidirectional selector for establishing a control path relationship among a plurality of objects to be tested; a data bidirectional selector for establishing a data path relationship; a management component for performing independent clock gating operations on input clock trees of the plurality of objects to be tested and performing independent system reset operations on input reset signals; and a test component for coordinating the components to set the control path relationship and the data path relationship among one or more objects to be tested according to a serial relationship, a parallel relationship or a serial-parallel mixed application relationship and to perform testing. Thus, various communication protocols and interface standards can be adapted, and the requirements of chip design development and chip testing for shortening chip testing time and fast response to changes can be met.

The invention relates to the technical field of electronic design automation, in particular to a layout area division method, a clock tree construction method, computer medium equipment and a program product. The method comprises the following steps: providing a layout area, and dividing the layout area into a plurality of square blocks which are in unit length and are distributed in an array manner; acquiring side length information of two adjacent sides of the layout area; performing grading processing on the layout area based on the side length information so as to divide the layout area into four secondary areas which are close in area and are composed of square blocks, and performing iteration grading processing on the obtained secondary areas until the area of the secondary areas is 4 * 3, 3 * 3 or 3 * 4, and the unit of the area is the product of the unit length; and dividing the secondary region into corresponding sub-regions, and then dividing the sub-regions into unit regions of which the areas are equal to the areas of the square blocks so as to complete division of the layout region. The problem that a traditional layout area division method can only divide 4 < n > unit areas is solved.