93 results about "Clock tree" patented technology

The invention discloses an RFSOC-based FAST core array distributed collaborative observation and data fusion method and system, and the method comprises the steps: S1, system initialization: a master node RFSOC generates a global clock, achieves the phase synchronization of multiple board cards through an SYSREF differential signal, and completes the calibration of a three-stage clock tree; s2, signal acquisition and preprocessing: directly sampling a 3-8GHz radio frequency signal through an ADC (Analog to Digital Converter), and performing digital down-conversion to obtain a baseband signal; s3, intelligent resource scheduling: identifying a signal type based on an ESN (Echo State Neural Network), and dynamically allocating FPGA logic resources through an improved ant colony algorithm; s4, heterogeneous calculation acceleration: executing a 128-channel digital beam forming pipeline on the FPGA; s5, cross-domain data fusion; s6, collaborative observation planning; and S7, outputting data. The method is suitable for multi-beam synthesis, cross-region joint observation and mass data real-time processing scenes, and provides key technical support for solving the frontier scientific problems such as rapid radio storm origin and black hole activity monitoring.

The invention discloses a time sequence convergence method and device based on a clock tree, and relates to the technical field of circuit design. The method comprises the following steps: performing automatic layout on devices; determining a time sequence path needing to be optimized in the one-to-many structure time sequence path; performing establishment time sequence margin optimization, and determining a setting pattern of useful clock skew adjustment based on the optimized establishment time sequence margin; determining the number of buffers based on the setting pattern of useful clock skew adjustment and the optimized setup time sequence margin, and generating a clock tree; on the basis of the generated clock tree, determining whether the time sequence violation of the retention time of the time sequence path needing to be optimized meets a preset requirement or not, and if the preset requirement is not met, adjusting the setting pattern of the useful clock skew adjustment, and returning to the step of generating the clock tree; and completing automatic wiring based on the clock tree meeting the predetermined requirement. According to the invention, the problem of power consumption increase caused by restoration of Hold time sequence violation can be solved.

The invention relates to a satellite-borne super-large-scale digital phased array system based on a JESD204B clock synchronization network, and the system comprises a radio frequency antenna layer which is used for receiving and transmitting electromagnetic waves in a space, and completing the mutual conversion of a radio frequency signal and a space electromagnetic wave; the sub-array baseband layer is used for realizing S-band 64-path intermediate frequency signal sampling, transmitting and digital domain multi-beam synthesis in a transceiving link, realizing data transmission with the mother board clock layer, and completing a reconstruction function of a baseband module signal processing FPGA (Field Programmable Gate Array) through a low-speed interface; the mother board clock layer serves as a function of realizing data summarization and distribution and performs task scheduling and management on the whole digital phased array system, and a JESD204B clock tree network is designed in the board and is distributed to a synchronous clock of each baseband module so as to indicate a target signal to complete synchronous sampling and emission output. By adopting the system, access, efficient tracking and accurate pointing of massive ground users can be realized.

A method may include generating a first clock path, wherein a first clock control logic (CCL) is connected between a mesh and a first sequential gate. The method may include disconnecting the first CCL from the first sequential gate in the first clock path, and connecting the mesh to the first sequential gate, and generating a second clock path, wherein the mesh is connected to a second CCL. The method may include generating a first clock tree in the first clock path, the first clock tree being connected to the first sequential gate, and connecting the first CCL between the mesh and the first clock tree. Finally, the method may include generating a second clock tree in the second clock path between the second CCL and a second sequential gate.

The invention provides a time sequence optimization method and device for convergence preposition, equipment, a medium and a product, and relates to the technical field of computers, in particular to the field of artificial intelligence and chips. According to the specific implementation scheme, all modules are combined into subsystems in a lightweight manner for time sequence analysis, and a cross-module time sequence violation path is obtained; performing path grouping on each cross-module time sequence violation path to obtain at least one path group; according to the time violation value of each cross-module time sequence violation path, allocating a repair weight to each path packet; determining a delay constraint compensation value of each path group according to an actual routing value of each cross-module time sequence violation path in the path end point module; according to each time delay constraint compensation value, each repair weight and the boundary constraint information and clock tree intervention information of the high-repair-level module, a subsystem-level optimization script is generated, and module-level layout and wiring optimization is carried out, so that the time sequence performance and reliability of chip design are improved, later large-scale modification is avoided, and the design efficiency is improved.

The invention relates to the technical field of industrial automation control, in particular to a data acquisition method and system based on a digital metering technology, and the method sequentially comprises the following steps: 1, carrying out the dynamic calibration of a sensor; 2, constructing a phase compensation clock tree; 3, establishing a temperature-humidity-vibration three-factor coupled error compensation model, determining the interaction weight of each factor through an orthogonal test method, and updating a compensation coefficient on line by adopting a recursive least square method with a forgetting factor; and step 4, generating a transmission priority according to the product of the data change rate and the health degree index, dynamically allocating a transmission bandwidth based on a network quality evaluation value calculated based on the time delay change rate and the packet loss rate, and performing compressed coding of a lead code mark on high-priority data. The method not only improves the precision of the system, but also optimizes the data processing and transmission efficiency, and provides an effective solution for high-precision data acquisition in a large-scale and complex environment.

The invention provides a gated clock circuit, a chip and electronic equipment. The gated clock circuit comprises a signal control module and a clock tree module, the signal control module generates a clock tree signal according to a source clock signal and input signals and output signals of all the single-bit D triggers; the clock tree module generates a plurality of sub-clock signals according to the clock tree signal; when the input signals and the output signals of all the single-bit D triggers are the same, the generated clock tree signal prevents the propagation of the source clock signal; when the input signal and the output signal of any single-bit D trigger are different, the generated clock tree signal enables the clock tree module to generate a plurality of sub-clock signals. The working state of the clock tree module is controlled through the signal control module, so that when the single-bit D flip-flop does not work, the clock tree module stops clock propagation, dynamic power consumption generated by clock flip-flop is saved, and the problem of how to reduce the dynamic power consumption generated by the single-bit D flip-flop in a chip is solved.

A clock tree 900 comprises a first clock buffer 906 electrically connected to a second clock buffer 910. The first clock buffer comprises a first transistor 972, a second transistor 974, a first resis

The invention provides a python-based clock tree visualization implementation method and system, and relates to the technical field of integrated circuits, and the method comprises the steps: reading an sdc file, extracting all clock information according to a grammar rule of the sdc file, and storing the clock information into a first dictionary according to names; reading the netlist, obtaining port information of all modules, and storing the port information into a second dictionary according to the names of the modules; reading a file of the library file, extracting port information of each module, and supplementing the port information to a second dictionary; all clock paths in the sdc are traced, and a fourth dictionary only containing all clock paths is generated; according to the fourth dictionary, dividing and drawing a port connection relationship in each module according to the modules, and forming a circuit diagram of each module; and developing a graphical interface for displaying the drawn circuit diagram, and setting functional keys in the interface. According to the method, a complete clock path and an integrally designed clock structure can be presented, a graphical interface can be provided, and the clock structure and the clock path can be visually viewed.

Methods, systems, and devices for techniques for clock coordination with reduced power and latency at a memory system are described. The described techniques provide for a memory system to delay the initiation of a decoding clock at the origin of a clock tree. For example, the memory system may initiate a command / address (CA) clock at a first time corresponding to reception of a CS signal, and may initiate the decoding clock at a second time following the first time by one or more unit intervals of the internal clock. Further, the described techniques provide for the memory system to buffer a first set of CA and buffer a second set of the CA bits according to respective unit intervals of the CA clock such that all the CA bits may be decoded at the decoder according to a single edge of the decoding clock.

A photoelectric conversion device is provided. The device includes a pixel array in which pixels are arranged, a drive controller configured to drive the pixel array, a horizontal transfer unit configured to sequentially output analog signals respectively output from columns of the pixel array, an AD converter configured to convert an analog signal output from the horizontal transfer unit into a digital signal, a first clock generator configured to generate a clock signal used to control an operation of the drive controller, and a second clock generator configured to generate a clock signal used to control the horizontal transfer unit and the AD converter. A clock tree in which a clock signal is distributed from the first clock generator and a clock tree in which a clock signal is distributed from the second clock generator form clock trees different from each other.

The invention discloses a gated clock conversion method, device and system for realizing a double-edge clock selection circuit based on a frequency multiplication clock. The method comprises the following steps: acquiring design information of a to-be-converted circuit; generating a frequency multiplication clock signal based on the clock input signal; constructing a combinational logic circuit; constructing a clock enabling generation logic based on the frequency multiplication clock signal, the post comb, the pre comb, the gating signal and the edge selection signal; a clock input terminal of the timing device is connected to the frequency multiplication clock signal, and an output of the clock enable generation logic is connected to a clock enable terminal of the timing device. According to the invention, the output of the combinational logic driven by the frequency multiplication clock sampling frequency dividing circuit is utilized, so that the function of selecting the rising edge and the falling edge is realized on the clock enabling pin of the register, the clock tree on the register is very clean, the higher frequency on an FPGA (Field Programmable Gate Array) is realized, and the hold timing is easier to converge.

The application discloses a kind of integrated circuit clock tree optimization method and system based on graph neural network and reinforcement learning, comprising the following steps: step S1: construct graph structure generation module, according to integrated circuit layout to construct the graph structure with register as node, with timing path as edge;Step S2: construct GNN feature extraction module, for the high-dimensional graph embedding representation of the feature vector of register node according to the graph structure constructed;Step S3: construct reinforcement learning network decision module, for receiving current node embedding representation vector and generating specific action after data processing;Step S4: construct timing verification and reward calculation module, for evaluating the updated circuit state, and obtaining reward signal to be used for the training of reinforcement learning network decision module;Step S5: constantly train reinforcement learning network decision module, until training is completed, finally obtain optimized register node feature vector, that is, optimized clock tree.

The invention discloses a partition-based multi-thread clock tree construction method, and belongs to the field of integrated circuits. Dividing according to the modules, the positions and the number of loads; executing the insertion of a buffer, and dividing the clock tree into an upper part and a lower part; wherein the upper sub-tree is from a root node of the clock tree to a newly inserted buffer, and the lower sub-tree is from the newly inserted buffer to a real clock tree load; the division is used as multiple threads, a buffer is used as a root node of a lower sub-tree, and the multiple threads are established to respectively process construction and balance of the tree; and processing the upper sub-tree, taking the next level of the buffer as a temporary load of the upper sub-tree so as to optimize the buffer of the upper sub-tree, and adding the maximum delay of the sub-tree corresponding to the root node of the clock tree in the current upper sub-tree to the delay of the buffer. According to the multi-thread method, the higher speed-up ratio is obtained, and meanwhile good consistency with a single-thread result is maintained.

A processing device identifies a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution. The processing device further identifies one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution. In addition, the processing device receives a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies, and generates the circuit design according to the selection.

Embodiments of the present disclosure provide a method and apparatus for evaluating a clock tree, a device and a storage medium. The method comprises: on the basis of a set of structural parameters for a plurality of portions of a clock tree, automatically determining a candidate clock tree structure for the clock tree, wherein each structural parameter in the set of structural parameters is used for defining a structure of one of the plurality of portions; obtaining circuit configuration information associated with the candidate clock tree structure, wherein the circuit configuration information indicates a connection relationship between circuit units in the candidate clock tree structure; and based at least on the circuit configuration information, determining the clock performance of the candidate clock tree structure. Therefore, automatic evaluation and verification of a clock tree design can be realized.

The application relates to the technical field of integrated circuits and provides a built-in self-test circuit and method for a chip. The circuit comprises a control bidirectional selector for establishing a control path relationship among a plurality of objects to be tested; a data bidirectional selector for establishing a data path relationship; a management component for performing independent clock gating operations on input clock trees of the plurality of objects to be tested and performing independent system reset operations on input reset signals; and a test component for coordinating the components to set the control path relationship and the data path relationship among one or more objects to be tested according to a serial relationship, a parallel relationship or a serial-parallel mixed application relationship and to perform testing. Thus, various communication protocols and interface standards can be adapted, and the requirements of chip design development and chip testing for shortening chip testing time and fast response to changes can be met.

The invention relates to the technical field of electronic design automation, in particular to a layout area division method, a clock tree construction method, computer medium equipment and a program product. The method comprises the following steps: providing a layout area, and dividing the layout area into a plurality of square blocks which are in unit length and are distributed in an array manner; acquiring side length information of two adjacent sides of the layout area; performing grading processing on the layout area based on the side length information so as to divide the layout area into four secondary areas which are close in area and are composed of square blocks, and performing iteration grading processing on the obtained secondary areas until the area of the secondary areas is 4 * 3, 3 * 3 or 3 * 4, and the unit of the area is the product of the unit length; and dividing the secondary region into corresponding sub-regions, and then dividing the sub-regions into unit regions of which the areas are equal to the areas of the square blocks so as to complete division of the layout region. The problem that a traditional layout area division method can only divide 4 < n > unit areas is solved.

The invention relates to the technical field of pessimism elimination algorithms, in particular to a public path pessimism margin removal method, product and method and a storage medium, and the method comprises the steps: providing a clock tree, traversing the clock tree, and generating an index table, a sequence table and a hierarchical table based on information obtained through traversing; generating a line segment tree based on the sequence table and the hierarchical table; for a starting point and an ending point of any given time sequence path, obtaining a nearest common node through line segment tree query; and determining a sub-tree modified in the optimization process based on the nearest common node, correspondingly modifying an index table, a sequence table and / or a hierarchical table, and then carrying out common path pessimistic margin removal analysis to remove pessimistic margin. The method provided by the invention can solve the technical problem that the current public path pessimistic margin removal method consumes much time.

The embodiment of the invention provides a clock tree generation method and a chip, and relates to the technical field of integrated circuits, and the method comprises the steps: determining a plurality of groups of sub-clock trees according to the node position of a clock tree and a preset grouping rule; and performing clock wiring based on the multiple groups of sub-clock trees and the selectable driving units to obtain a clock tree, the number of clock tree nodes in each group of sub-clock trees being determined according to the driving capability and the driving distance of the selectable driving units. Therefore, the problem of large clock skew caused by the fact that nodes in a clock tree deviate from a symmetrical structure due to the fact that various devices exist in a chip in a traditional Htree clock can be solved, and the effect of high-speed and stable transmission of clock signals is achieved.

The application relates to a code generation method, device and equipment based on a chip clock tree prototype graph. The method comprises the following steps: obtaining a clock tree prototype graph of to-be-generated code, analyzing the clock tree prototype graph, obtaining the type of components in the clock tree prototype graph and the connection relationship of the components, and generating the code corresponding to the clock tree prototype graph according to the type of the components and the connection relationship of the components. According to the type of the components and the connection relationship of the components, the code corresponding to the clock tree prototype graph can be directly and accurately generated. Chip design engineers do not need to design the corresponding code while designing the clock tree prototype graph. The code corresponding to the clock tree prototype graph can be automatically generated by only maintaining or modifying the clock tree prototype graph.

The invention belongs to the technical field of electronic design automation, and provides a statistical method of a gating register, electronic equipment and a storage medium, the method comprises the following steps: starting from a top layer module of circuit design, taking a root clock port on the top layer module as an initial node, and traversing a clock tree of the circuit design along a clock signal propagation direction; key-value pairs are maintained in a pre-created mapping container through traversal, the flattened net is stored as keys, and a clock gating unit set corresponding to the flattened net is stored as values; based on a flattening line net connected with a sink pin of a register in the circuit design, a target clock gating unit set corresponding to the register is determined in the mapping container, clock gating units in the target clock gating unit set are associated with the register, and the sink pin is a clock signal input end. According to the method, the information of the gating register can be accurately counted, and the time complexity of counting is optimized.

The present application relates to the technical field of electronic design automation, in particular to a concurrent clock optimization and data optimization method, tool, computer device, medium and program. The concurrent clock optimization and data optimization method comprises providing a clock optimizer and constructing a clock tree; obtaining an initial skew on the clock tree, and the clock optimizer performs balancing processing on the clock tree based on the initial skew, so that the clock tree obtains a useful skew; integrating the clock optimizer and a data optimizer to obtain a concurrent optimizer; using the concurrent optimizer to simultaneously perform data optimization on the balanced clock tree, and clock optimization on the balanced clock tree based on the useful skew. The existing optimization tool has poor efficiency for clock tree optimization.

Multi-phase clock generators, memory devices, and methods of generating multi-phase clocks are provided. The multi-phase clock generator includes a first variable delay line and a second variable delay line; a first phase splitter configured to phase split a first phase-delayed clock output from a clock tree to output a first divided clock and a third divided clock; a second phase splitter configured to phase split a second phase-delayed clock output from the clock tree to output a second divided clock and a fourth divided clock; a first duty cycle detector configured to detect a first duty cycle error between the first divided clock and the third divided clock; and a second duty cycle detector configured to detect a second duty cycle error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty cycle error, and the second variable delay line is controlled according to the second duty cycle error.

The disclosed apparatus includes various circuit blocks and a clock tree for sending clock signals to the circuit blocks. The clock tree includes various clock drivers. The apparatus also includes control circuitry to power gate a portion of the clock tree including one of the clock drivers in response to one of the circuit blocks being power gated. Various other methods, systems, and computer readable media are also disclosed.

Embodiments of the present application provide a circuit logic synthesis parameter optimization method, device, equipment and medium, the method comprises: obtaining initial clock uncertainty parameter and initial clock conversion time parameter; according to initial clock uncertainty parameter, initial clock conversion time parameter and preset optimization model, determine optimization clock uncertainty parameter and optimization clock conversion time parameter;According to optimization clock uncertainty parameter and optimization clock conversion time parameter, determine timing score and area score;In the case where timing score and area score meet the preset score condition, according to optimization clock uncertainty parameter and optimization clock conversion time parameter, determine target clock uncertainty parameter and target clock conversion time parameter;In this way, the optimized clock uncertainty parameter and clock conversion time parameter can be accurately calculated.The problem of parameter setting depending on experience and lacking scientificity is solved, and the accuracy and reliability of clock tree design are improved.

The invention provides an ultrasonic application-specific integrated circuit top-layer architecture and an ultrasonic chip. The ultrasonic application-specific integrated circuit top-layer architecture comprises a central digital IO interface; the digital control hub is connected to the central digital IO interface; the ultrasonic core array comprises a first ultrasonic core area and a second ultrasonic core area which are split along a horizontal axis mirror image; the peripheral digital module comprises a first peripheral digital unit and a second peripheral digital unit, and the first peripheral digital unit and the second peripheral digital unit are arranged on the two sides of the ultrasonic core array respectively; wherein the ultrasonic sub-array in the first ultrasonic core area is connected with the digital control hub through the first peripheral digital unit on one hand and is directly connected with the digital control hub on the other hand; and the ultrasonic sub-array in the second ultrasonic core area is connected with the digital control hub through the second peripheral digital unit and is directly connected with the digital control hub. According to the invention, the stage number of the clock tree is reduced through zone control of the ultrasonic core zone, and the signal delay difference is reduced.

This invention discloses a distributed collaborative observation and data fusion method and system for the FAST core array based on RFSOC, comprising: S1 System initialization: The master node RFSOC generates a global clock, and achieves phase synchronization of multiple boards through SYSREF differential signals, completing a three-level clock tree calibration; S2 Signal acquisition and preprocessing: 3-8GHz radio frequency signals are directly sampled by an ADC and digitally down-converted to baseband signals; S3 Intelligent resource scheduling: Signal types are identified based on an echo state neural network (ESN), and FPGA logic resources are dynamically allocated through an improved ant colony algorithm; S4 Heterogeneous computing acceleration: A 128-channel digital beamforming pipeline is executed on the FPGA; S5 Cross-domain data fusion; S6 Collaborative observation planning; S7 Data output. This invention is applicable to scenarios involving multi-beamforming, cross-regional joint observation, and real-time processing of massive amounts of data, providing key technical support for solving cutting-edge scientific problems such as the origin of fast radio bursts and monitoring black hole activity.

The application belongs to the technical field of integrated circuits, and provides a clock tree generation method, a medium and an electronic device. The method comprises the following steps: obtaining a netlist file of a circuit; identifying a clock network according to a network identifier in the netlist file. Then, the type of a device is identified according to the identification information of the device in the netlist file, and the pin information of the device is determined. The clock link is determined according to the connection relationship of the device in the netlist file. Furthermore, the flow direction of the clock signal can be determined according to the clock link and the pin information of the device. Therefore, the electronic device can automatically draw a clock tree, and the circuit development efficiency is improved.

The utility model discloses a kind of PCIE optical fiber communication boards for special components, including FPGA, FPGA is integrally connected with synchronous clock input interface, three-way digital optical fiber receiving interface, SMA input interface, TypeC interface group, independent SDRAM storage unit and optical signal output port by function interface;FPGA is coordinated each above-mentioned component module work, realizes the protocol conversion of PCIE protocol and optical fiber communication, data encoding and decoding, cache management function.The utility model innovatively adopts mixed clock domain architecture, organically combines synchronous clock tree and asynchronous data channel, simultaneously supports the mixed networking mode of copper cable and optical fiber through photoelectric composite interface design, while guaranteeing high-speed data transmission, effectively reduce the electromagnetic interference influence in transmission path;In addition, the multi-protocol conversion engine and hardware acceleration module integrated in FPGA further improve the processing efficiency and flexibility of system.