63 results about "Clock tree" patented technology

The invention discloses a time sequence convergence method and device based on a clock tree, and relates to the technical field of circuit design. The method comprises the following steps: performing automatic layout on devices; determining a time sequence path needing to be optimized in the one-to-many structure time sequence path; performing establishment time sequence margin optimization, and determining a setting pattern of useful clock skew adjustment based on the optimized establishment time sequence margin; determining the number of buffers based on the setting pattern of useful clock skew adjustment and the optimized setup time sequence margin, and generating a clock tree; on the basis of the generated clock tree, determining whether the time sequence violation of the retention time of the time sequence path needing to be optimized meets a preset requirement or not, and if the preset requirement is not met, adjusting the setting pattern of the useful clock skew adjustment, and returning to the step of generating the clock tree; and completing automatic wiring based on the clock tree meeting the predetermined requirement. According to the invention, the problem of power consumption increase caused by restoration of Hold time sequence violation can be solved.

A method may include generating a first clock path, wherein a first clock control logic (CCL) is connected between a mesh and a first sequential gate. The method may include disconnecting the first CCL from the first sequential gate in the first clock path, and connecting the mesh to the first sequential gate, and generating a second clock path, wherein the mesh is connected to a second CCL. The method may include generating a first clock tree in the first clock path, the first clock tree being connected to the first sequential gate, and connecting the first CCL between the mesh and the first clock tree. Finally, the method may include generating a second clock tree in the second clock path between the second CCL and a second sequential gate.

The invention provides a python-based clock tree visualization implementation method and system, and relates to the technical field of integrated circuits, and the method comprises the steps: reading an sdc file, extracting all clock information according to a grammar rule of the sdc file, and storing the clock information into a first dictionary according to names; reading the netlist, obtaining port information of all modules, and storing the port information into a second dictionary according to the names of the modules; reading a file of the library file, extracting port information of each module, and supplementing the port information to a second dictionary; all clock paths in the sdc are traced, and a fourth dictionary only containing all clock paths is generated; according to the fourth dictionary, dividing and drawing a port connection relationship in each module according to the modules, and forming a circuit diagram of each module; and developing a graphical interface for displaying the drawn circuit diagram, and setting functional keys in the interface. According to the method, a complete clock path and an integrally designed clock structure can be presented, a graphical interface can be provided, and the clock structure and the clock path can be visually viewed.

Methods, systems, and devices for techniques for clock coordination with reduced power and latency at a memory system are described. The described techniques provide for a memory system to delay the initiation of a decoding clock at the origin of a clock tree. For example, the memory system may initiate a command / address (CA) clock at a first time corresponding to reception of a CS signal, and may initiate the decoding clock at a second time following the first time by one or more unit intervals of the internal clock. Further, the described techniques provide for the memory system to buffer a first set of CA and buffer a second set of the CA bits according to respective unit intervals of the CA clock such that all the CA bits may be decoded at the decoder according to a single edge of the decoding clock.

The invention discloses a gated clock conversion method, device and system for realizing a double-edge clock selection circuit based on a frequency multiplication clock. The method comprises the following steps: acquiring design information of a to-be-converted circuit; generating a frequency multiplication clock signal based on the clock input signal; constructing a combinational logic circuit; constructing a clock enabling generation logic based on the frequency multiplication clock signal, the post comb, the pre comb, the gating signal and the edge selection signal; a clock input terminal of the timing device is connected to the frequency multiplication clock signal, and an output of the clock enable generation logic is connected to a clock enable terminal of the timing device. According to the invention, the output of the combinational logic driven by the frequency multiplication clock sampling frequency dividing circuit is utilized, so that the function of selecting the rising edge and the falling edge is realized on the clock enabling pin of the register, the clock tree on the register is very clean, the higher frequency on an FPGA (Field Programmable Gate Array) is realized, and the hold timing is easier to converge.

The application discloses a kind of integrated circuit clock tree optimization method and system based on graph neural network and reinforcement learning, comprising the following steps: step S1: construct graph structure generation module, according to integrated circuit layout to construct the graph structure with register as node, with timing path as edge;Step S2: construct GNN feature extraction module, for the high-dimensional graph embedding representation of the feature vector of register node according to the graph structure constructed;Step S3: construct reinforcement learning network decision module, for receiving current node embedding representation vector and generating specific action after data processing;Step S4: construct timing verification and reward calculation module, for evaluating the updated circuit state, and obtaining reward signal to be used for the training of reinforcement learning network decision module;Step S5: constantly train reinforcement learning network decision module, until training is completed, finally obtain optimized register node feature vector, that is, optimized clock tree.

The invention discloses a partition-based multi-thread clock tree construction method, and belongs to the field of integrated circuits. Dividing according to the modules, the positions and the number of loads; executing the insertion of a buffer, and dividing the clock tree into an upper part and a lower part; wherein the upper sub-tree is from a root node of the clock tree to a newly inserted buffer, and the lower sub-tree is from the newly inserted buffer to a real clock tree load; the division is used as multiple threads, a buffer is used as a root node of a lower sub-tree, and the multiple threads are established to respectively process construction and balance of the tree; and processing the upper sub-tree, taking the next level of the buffer as a temporary load of the upper sub-tree so as to optimize the buffer of the upper sub-tree, and adding the maximum delay of the sub-tree corresponding to the root node of the clock tree in the current upper sub-tree to the delay of the buffer. According to the multi-thread method, the higher speed-up ratio is obtained, and meanwhile good consistency with a single-thread result is maintained.

The application relates to the technical field of integrated circuits and provides a built-in self-test circuit and method for a chip. The circuit comprises a control bidirectional selector for establishing a control path relationship among a plurality of objects to be tested; a data bidirectional selector for establishing a data path relationship; a management component for performing independent clock gating operations on input clock trees of the plurality of objects to be tested and performing independent system reset operations on input reset signals; and a test component for coordinating the components to set the control path relationship and the data path relationship among one or more objects to be tested according to a serial relationship, a parallel relationship or a serial-parallel mixed application relationship and to perform testing. Thus, various communication protocols and interface standards can be adapted, and the requirements of chip design development and chip testing for shortening chip testing time and fast response to changes can be met.

The invention relates to the technical field of pessimism elimination algorithms, in particular to a public path pessimism margin removal method, product and method and a storage medium, and the method comprises the steps: providing a clock tree, traversing the clock tree, and generating an index table, a sequence table and a hierarchical table based on information obtained through traversing; generating a line segment tree based on the sequence table and the hierarchical table; for a starting point and an ending point of any given time sequence path, obtaining a nearest common node through line segment tree query; and determining a sub-tree modified in the optimization process based on the nearest common node, correspondingly modifying an index table, a sequence table and / or a hierarchical table, and then carrying out common path pessimistic margin removal analysis to remove pessimistic margin. The method provided by the invention can solve the technical problem that the current public path pessimistic margin removal method consumes much time.

The embodiment of the invention provides a clock tree generation method and a chip, and relates to the technical field of integrated circuits, and the method comprises the steps: determining a plurality of groups of sub-clock trees according to the node position of a clock tree and a preset grouping rule; and performing clock wiring based on the multiple groups of sub-clock trees and the selectable driving units to obtain a clock tree, the number of clock tree nodes in each group of sub-clock trees being determined according to the driving capability and the driving distance of the selectable driving units. Therefore, the problem of large clock skew caused by the fact that nodes in a clock tree deviate from a symmetrical structure due to the fact that various devices exist in a chip in a traditional Htree clock can be solved, and the effect of high-speed and stable transmission of clock signals is achieved.

The application relates to a code generation method, device and equipment based on a chip clock tree prototype graph. The method comprises the following steps: obtaining a clock tree prototype graph of to-be-generated code, analyzing the clock tree prototype graph, obtaining the type of components in the clock tree prototype graph and the connection relationship of the components, and generating the code corresponding to the clock tree prototype graph according to the type of the components and the connection relationship of the components. According to the type of the components and the connection relationship of the components, the code corresponding to the clock tree prototype graph can be directly and accurately generated. Chip design engineers do not need to design the corresponding code while designing the clock tree prototype graph. The code corresponding to the clock tree prototype graph can be automatically generated by only maintaining or modifying the clock tree prototype graph.

The invention belongs to the technical field of electronic design automation, and provides a statistical method of a gating register, electronic equipment and a storage medium, the method comprises the following steps: starting from a top layer module of circuit design, taking a root clock port on the top layer module as an initial node, and traversing a clock tree of the circuit design along a clock signal propagation direction; key-value pairs are maintained in a pre-created mapping container through traversal, the flattened net is stored as keys, and a clock gating unit set corresponding to the flattened net is stored as values; based on a flattening line net connected with a sink pin of a register in the circuit design, a target clock gating unit set corresponding to the register is determined in the mapping container, clock gating units in the target clock gating unit set are associated with the register, and the sink pin is a clock signal input end. According to the method, the information of the gating register can be accurately counted, and the time complexity of counting is optimized.

Multi-phase clock generators, memory devices, and methods of generating multi-phase clocks are provided. The multi-phase clock generator includes a first variable delay line and a second variable delay line; a first phase splitter configured to phase split a first phase-delayed clock output from a clock tree to output a first divided clock and a third divided clock; a second phase splitter configured to phase split a second phase-delayed clock output from the clock tree to output a second divided clock and a fourth divided clock; a first duty cycle detector configured to detect a first duty cycle error between the first divided clock and the third divided clock; and a second duty cycle detector configured to detect a second duty cycle error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty cycle error, and the second variable delay line is controlled according to the second duty cycle error.

The disclosed apparatus includes various circuit blocks and a clock tree for sending clock signals to the circuit blocks. The clock tree includes various clock drivers. The apparatus also includes control circuitry to power gate a portion of the clock tree including one of the clock drivers in response to one of the circuit blocks being power gated. Various other methods, systems, and computer readable media are also disclosed.

The invention provides an ultrasonic application-specific integrated circuit top-layer architecture and an ultrasonic chip. The ultrasonic application-specific integrated circuit top-layer architecture comprises a central digital IO interface; the digital control hub is connected to the central digital IO interface; the ultrasonic core array comprises a first ultrasonic core area and a second ultrasonic core area which are split along a horizontal axis mirror image; the peripheral digital module comprises a first peripheral digital unit and a second peripheral digital unit, and the first peripheral digital unit and the second peripheral digital unit are arranged on the two sides of the ultrasonic core array respectively; wherein the ultrasonic sub-array in the first ultrasonic core area is connected with the digital control hub through the first peripheral digital unit on one hand and is directly connected with the digital control hub on the other hand; and the ultrasonic sub-array in the second ultrasonic core area is connected with the digital control hub through the second peripheral digital unit and is directly connected with the digital control hub. According to the invention, the stage number of the clock tree is reduced through zone control of the ultrasonic core zone, and the signal delay difference is reduced.

The application belongs to the technical field of integrated circuits, and provides a clock tree generation method, a medium and an electronic device. The method comprises the following steps: obtaining a netlist file of a circuit; identifying a clock network according to a network identifier in the netlist file. Then, the type of a device is identified according to the identification information of the device in the netlist file, and the pin information of the device is determined. The clock link is determined according to the connection relationship of the device in the netlist file. Furthermore, the flow direction of the clock signal can be determined according to the clock link and the pin information of the device. Therefore, the electronic device can automatically draw a clock tree, and the circuit development efficiency is improved.

The utility model discloses a kind of PCIE optical fiber communication boards for special components, including FPGA, FPGA is integrally connected with synchronous clock input interface, three-way digital optical fiber receiving interface, SMA input interface, TypeC interface group, independent SDRAM storage unit and optical signal output port by function interface;FPGA is coordinated each above-mentioned component module work, realizes the protocol conversion of PCIE protocol and optical fiber communication, data encoding and decoding, cache management function.The utility model innovatively adopts mixed clock domain architecture, organically combines synchronous clock tree and asynchronous data channel, simultaneously supports the mixed networking mode of copper cable and optical fiber through photoelectric composite interface design, while guaranteeing high-speed data transmission, effectively reduce the electromagnetic interference influence in transmission path;In addition, the multi-protocol conversion engine and hardware acceleration module integrated in FPGA further improve the processing efficiency and flexibility of system.

The invention relates to the technical field of circuits, in particular to a timing constraint text checking method and device and electronic equipment. Obtaining at least one initial time sequence constraint text corresponding to the target circuit; identifying each initial time sequence constraint text, and extracting clock information corresponding to at least one target clock included in the target circuit; generating an initial clock tree structure according to the clock information corresponding to each target clock; checking each target clock according to the initial clock tree structure, and determining an error type corresponding to the initial clock tree structure; and according to the error type, correcting the initial clock tree structure to generate a target clock tree structure. Finally, an accurate and compliant clock tree is obtained, a reliable clock model is provided for subsequent time sequence analysis and chip function verification, and design errors and iteration cost are reduced. Therefore, high efficiency and accuracy of SDC verification are realized.

This application provides a synthesis method, storage medium, and program product for H-type clock trees, relating to the field of chip design. The method classifies each clock unit in the clock structure according to the number of flip-flops it covers; determines the number of H-type clock trees and their generation order based on different types of clock units and clock source types; uses a weighted clustering algorithm to determine the starting point and mounting point position of each H-type clock tree according to the number of H-type clock trees and their generation order; and constructs the corresponding H-type clock tree according to the starting point and mounting point position of each H-type clock tree. The H-type clock tree structure design of this application can effectively reduce unnecessary clock buffers and wiring capacitors, controlling power consumption at its source. It is applicable to clock structures with multiple clock sources and complex clock logic, and is suitable for large-scale high-performance integrated circuit design, providing a more efficient and reliable clock design solution for related design work.

Methods and apparatus for improving a data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to trigger to capture write data or output read data based on a data clock; and a command decoder configured to detect a data clock pause command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to inhibit triggering based on the data clock in response to the command decoder detecting the data clock pause command. The host includes a memory controller configured to provide a data clock pause command to the memory via the link while the data clock is synchronized between the host and the memory.

The application discloses a circuit timing repair method and system for pre-simulation and post-simulation, and the method comprises the following steps: obtaining a path violating timing constraints in a circuit through timing analysis software; determining whether timing requirements can be met by modifying the delay of combination logic and the setup time parameter and the hold time parameter of a terminal register; if not, the clock tree delay of a starting point register or a terminal register is modified, timing information is analyzed, a path violating timing is obtained again, and then the determination is made; if yes, the setup time parameter and the hold time parameter of the combination logic and the terminal register are modified to meet the setup time constraints and the hold time constraints; finally, a netlist and a delay file meeting timing requirements after repair are extracted and provided for pre-simulation and post-simulation. The application aims at pre-simulation and post-simulation of a chip design after preliminary physical design to accelerate the timing and functional verification progress of the chip.

The application aims to provide a power network reserved low-layer metal wiring resource alleviating on-chip voltage drop method, which comprises the following steps: reserving a deployment area of a low-layer metal resource in a chip layout stage; correcting the deployment area; and using the metal resource in the deployment area according to chip analysis results after wiring is completed. In the layout and wiring and clock tree synthesis stages, the low-layer metal wiring resource is reserved for connecting the power supply tracks of adjacent standard cells, so that the problem of excessive voltage drop caused by excessive low-layer metal resistance can be effectively alleviated by flexibly enabling the reserved wiring resource in the late stage of chip design.

An analyzer for capturing resistance voltage drop and an analysis method thereof are provided. The analysis method for capturing resistance voltage drop includes receiving circuit layout information and package model information, parsing a plurality of circuit blocks corresponding to a plurality of bump current sources in a circuit according to the circuit layout information and the package model information, calculating at least one critical circuit block according to current demand values of each bump current source and each corresponding circuit block, and analyzing a clock tree architecture of the at least one critical circuit block to obtain design structure adjustment information.

Various embodiments provide for cloning a clock gate based on input / output switching activity of clocked circuit elements gated by the clock gate, where the cloning can be performed as part of a clock tree generation or optimization process performed by an electronic design automation (EDA) software.

The present application relates to the technical field of industrial automation control, and more particularly to a data acquisition method and system based on digital metrology technology, wherein the method sequentially performs the following steps: step 1: performing sensor dynamic calibration; step 2: constructing a phase compensation clock tree; step 3: establishing a temperature-humidity-vibration three-factor coupled error compensation model, determining the interaction weight of each factor by orthogonal test method, and updating the compensation coefficient online by using the recursive least square method with a forgetting factor; step 4: generating transmission priority according to the product of data change rate and health index, dynamically allocating transmission bandwidth based on network quality evaluation value calculated by delay change rate and packet loss rate, and implementing preamble marked compression encoding for high priority data. This method not only improves the accuracy of the system, but also optimizes the data processing and transmission efficiency, providing an effective solution for high-precision data acquisition in large-scale and complex environments.

The present application relates to the technical field of semiconductors, and provides a chip system and an electronic apparatus, used for improving the clock quality of a chip system having a 3D structure, and improving the chip performance. The chip system comprises a first die and at least one second die; the first die is coupled to the second die by means of an inter-die interconnection interface; and the first die and the second die are each provided with a plurality of timing devices. The chip system further comprises a clock tree; the clock tree is disposed in the first die; and the clock tree can be coupled to clock input ends of the timing devices on the second die by means of the inter-die interconnection interface and interconnection metal lines to provide a clock signal for the timing devices on the second die. In this way, distribution of the clock tree across different dies can be avoided, thereby reducing the effect of cross chip variation on the clock signal of the chip system, improving the clock signal quality of the chip system, and improving the chip performance.

The application provides a clock tree architecture, a clock signal transmission method and equipment. The clock tree architecture comprises a clock source, a frequency divider and a clock tree. The clock source is used to generate a clock signal. The frequency divider is used to reduce a target clock frequency of the clock signal generated by the clock source to a first clock frequency to obtain a to-be-transmitted clock signal. The first clock frequency is half of the target frequency. The clock tree is used to receive the to-be-transmitted clock signal and transmit the to-be-transmitted clock signal to a target module. A timing logic circuit of the clock tree is implemented by using double-edge registers and double-edge gate units. The application can save power consumption of clock signal transmission, enhance reliability of clock signal transmission and have higher applicability.

The invention relates to the technical field of integrated circuits and provides a built-in self-test circuit and method for a chip. The circuit comprises a control bidirectional selector which is used for constructing a control path relation among a plurality of objects to be tested; the data bidirectional selector is used for constructing a data path relationship; the management component is used for executing independent clock gating operation on respective input clock trees of the plurality of to-be-tested objects and executing independent system reset operation on respective input reset signals of the plurality of to-be-tested objects; and the test component is used for coordinating the components so as to set a control path relationship and a data path relationship among one or more objects to be tested according to a serial relationship, a parallel relationship or a serial-parallel mixed application relationship and test. Therefore, the method is beneficial to adapting to various communication protocols and interface standards, and meets the requirements of chip design and development and chip testing for shortening the chip testing time and quickly responding to changes.

This application provides a method, system, device, and medium for automatically generating chip clock control code, effectively solving the problems of low efficiency, low design reliability, and low accuracy in chip clock design and implementation. The method includes: obtaining a user-provided structured file containing a chip clock tree structure; identifying and extracting various hardware elements from the structured file according to preset mapping rules; establishing an initial netlist topology based on the ports / modules and corresponding signal connections in the various hardware elements; automatically sorting the signal connections in the initial netlist topology using target merging rules to obtain a netlist topology diagram; executing a target code language generation strategy to obtain various instantiated codes based on the netlist topology diagram and corresponding connection signals; and assembling the various instantiated codes to obtain the control code corresponding to the chip clock.

This application discloses a method for merging comprehensive constraint files and an electronic device. The method may include: obtaining comprehensive constraint files corresponding to multiple modules, wherein the multiple modules are obtained by chip segmentation; parsing the comprehensive constraint file corresponding to each module to obtain the basic clock tree corresponding to the module; merging all basic clock trees according to the connection relationship information between the multiple modules to obtain the target clock tree corresponding to the chip; and generating the target comprehensive constraint file corresponding to the chip according to the target clock tree. The entire process is automated, reducing manpower and time, improving the speed of merging comprehensive constraint files, and improving the accuracy of merging comprehensive constraint files.