Estimation method and system of clock tree delay time in specified integrated circuit

Abstract

The invention discloses an estimation method and system of clock tree delay time in a specified integrated circuit, wherein the method comprises the following steps of: obtaining a netlist and a layout relative to the clock tree in the specified integrated circuit; extracting the number of load time sequence apparatuses connected with the clock tree according to the netlist relative to the clock tree; extracting a physical distribution region area of the load time sequence apparatuses connected with the clock tree according to the layout relative to the clock tree; estimating the delay time of the clock tree according to the relation among the number of the load time sequence apparatuses, the physical distribution region area of the load time sequence apparatuses and the clock tree delay time in the historical data of the same process with the specified integrated circuit. An audit flow is reduced to days from weeks by using the improved specified integrated circuit design method, a designer can rapidly find and solve the problem; and therefore, the design time is reduced, and the design efficiency is improved.

Description

Technical field [0001] The present invention generally relates to integrated circuit design, and more specifically, to a method and system for estimating the delay time of a time tree and the arrival time of a clock signal in an application specific integrated circuit. Background technique [0002] In the field of integrated circuit technology, an application specific integrated circuit (ASIC) refers to an integrated circuit designed and manufactured in response to specific user requirements and specific electronic system requirements. ASIC is characterized by the needs of specific users. Compared with general integrated circuits in mass production, it has the advantages of smaller size, lower power consumption, improved reliability, improved performance, enhanced confidentiality, and cost reduction. [0003] figure 1 The current ASIC design process is shown. In step S101, a Gate Level Netlist is generated, and in step S102, a layout (Full Placment) is performed. This step refers t...

AI Technical Summary

Problems solved by technology

Typically, clock tree insertion itself is time-consuming, and such an iterative process greatly extends the design cycle

[0006] On the other hand, as the scale of ASICs becomes larger, the work of clock tree insertion itself becomes more and more time-consuming

For a very large-scale application-specific integrated circuit with tens of millions of gates, if the design method of flattening is adopted, the time-consuming of clock tree insertion is often calculated in days or even weeks; this situation increases the difficulty of finding and solving problems. time cost

[0007] The above two problems will cause the product design cycle to be too long, and may miss favorable market opportunities

Images