508 results about "Test design" patented technology

A design structure embodied in a machine readable storage medium for at designing, manufacturing, and/or testing a design is disclosed for initializing expansion adapters installed in a computer system having similar expansion adapters that include detecting an expansion adapter installed in a computer system having a plurality of expansion adapters, the detected expansion adapter having an option ROM containing initialization code, identifying similar expansion adapters installed in the computer system that correspond to the detected expansion adapter, each of the identified similar expansion adapters having an option ROM containing initialization code, disabling the option ROM of each of the identified similar expansion adapters, and initializing the plurality of expansion adapters installed in the computer system without executing the initialization code of the identified similar expansion adapters.

The invention concerns a method for assigning a value to at least one data item of a test case instance. The invention is characterized in that the method comprises steps of selecting an input data item from a test design library, the library comprising a plurality of input data items and information about semantics and/or data type of the input data items and assigning the selected input data item as a value of data item of the test case instance. Also an arrangement and a computer readable media comprising a computer executable program are disclosed.

A method and system for well test optimization provides test parameters and variation range therefor, independently from preliminarily reservoir and downhole fluid data; and repeatedly executes the test for each parameter to obtain real-time measured data, and interpreted data that is compared to the variation range for meeting a test objective. A method and system for well test design and interpretation, includes a testing manager having testing hardware/gauge metrology; a geological model; dynamic/static engineering data acquisition; and a reservoir model generator. A method and system for well test design and interpretation generates a test plan and an initial reservoir model and data from real/near-real-time, surface/downhole/manual data, aggregated data based on quality control/assurance, and optimization data based thereon and simulated downhole data; models/interprets the optimization data to meet test objectives for terminating/continuing the test plan; modifies the optimization; and/or generates reports from the modeling/interpretation when terminating the test plan.

The invention discloses a high-rigidity and light-weight design method considering uncertainty of a slide block mechanism of a press machine. The high-rigidity and light-weight design method comprises the steps of: establishing a high-rigidity and light-weight design model considering the uncertainty of the slide block mechanism of the press machine; adopting an optimized Latin hypercube sampling method for a test design, obtaining a target function response value corresponding to each sample point through collaborative simulation and building a Kriging agent model; converting an uncertain target function into a certain target function based on an order relation of interval numbers; and calculating a target function interval by utilizing an internal structure analysis way, finding a Pareto optimal solution collection of a converted certain optimal problem by utilizing a multi-target genetic algorithm, if the precision requirement is not satisfied, performing important sampling at the place where the extreme value of the target function interval locates, and updating the target function sample collection and the agent model to perform iterative optimization. The high-rigidity and light-weight design method considering uncertainty of the slide block mechanism of the press machine, disclosed by the invention, has the advantages of establishing the uncertain optimization model of the slide block mechanism according with the practical project for solving and really realizing the light-weight and high-rigidity design of the slide block mechanism.

The present invention relates a test example generating method based on relationship, comprising the following steps of: selecting the test point of each control of a graphical user interface to be tested, according to types; taking the value of each control according to a principle that all levels of each factor are taken and assembling the related controls completely, and then combining; generating a test example according to the reference relation of the function to be tested and the example template; combining the test examples to generate all test examples of the function to be tested. With boundary value testing and equivalence testing, the method carries out strict, normative and comprehensive test point design according to the common controls in an interface test. The test designing points of each type of controls are solidified into a group of test example generating criterion for citing and expanding. The example is designed with a control relation graph and a function relation graph according to the analysis of control relativity and function relativity, so that the selection of the input value of the test example has more pertinences, thereby being capable of greatly improving the efficiency and the quality of GUI test designing.

Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change. The already placed chip design is pruned to create a set of valid flops and valid scan chains based on a set of pruning rules. A unified flop database is generated containing physical location and connection information for the new flops and the set of valid flops. A change file for the new flops, selected valid flops, and valid scan chains associated with the selected valid flops is generated meeting allocation and placement sensitive signal connection rules. The new flops are connected to the selected valid flops allowing design for test requirements to be met

The invention proposes a novel prediction method for service life migration of a lithium ion battery. The method comprises: a capacity degradation database of batteries with the same temperature, thesame multiplying power, and different formulas is established; after determination of a target battery, a battery similar to a capacity degradation rule of the target battery is selected based on a similarity measure; and then on the basis of the deep learning method, cross-formula battery service life migration prediction is carried out to realize prediction of the residual cycle life of the target battery. Meanwhile, with consideration of the economic target and irreversibility of battery life degradation, the design of the battery cycle life test is optimized and the battery test design issaved. With the method, the accurate residual life prediction of the lithium ion battery is realized; the test time and the test load of the service life testing at the research and development stageare reduced substantially; the research and development cycle of new products is shortened; the research and development costs are lowered; and the reliability and safety of the system are improved.

The invention discloses an automatic test method and an automatic test system on the basis of WEB interfaces. The automatic test method includes extracting test use case data from databases by the aid of a server according to received test execution requests initiated by users and generating test tasks; invoking a test executor and executing tests; analyzing test results and then generating test reports. The test use case data conform to conditions. The automatic test method and the automatic test system in an embodiment of the invention have the advantage that test personnel can carry out automatic test design, execution and management on the WEB interface of various projects without mastering coding technologies.

One of the examples is to define and use the concept of “Logs/Traces Profile” and “System Logs/Traces Profile” (including a role and the log and trace file locations), and incorporate them within the test design document. Each test design document can be associated to each test case to highlight which logs and traces need to be collected during its execution. In this way, the testers will know which logs and traces to provide to the code developers, when addressing an issue. In this way, developer can investigate the bug, understand them, and be able to fix the problem, especially due to timing, synchronization, and concurrency.

A system and method for generating test frames in specification-based testing by using a path-coverage criterion is provided. The method includes receiving a test design as an input, and constructing a context-free grammar graph, based on the test design. The method further includes analyzing the context-free grammar graph to generate a first set of paths, and emitting a set of test frames as an output, based on the first set of paths.

In scan test circuit design, a plurality of flipflop circuits (102a, 102b or 102c) driven with each of final-stage elements 101f of a clock tree T are connected in series, to form a sub-scan chain. Also, sub-scan chains smallest in the relative difference in the number of stages of delay elements existing from the clock supply point S of the clock tree T (i.e., sub-scan chains different by one stage) are connected to each other. Further, sub-scan chains are connected so that data shift be made from a flipflop circuit larger in clock delay to a flipflop circuit smaller in clock delay. This reduces the number of delay elements inserted in data lines of a shift register for hold time guarantee in shift operation of the scan shift register, and suppresses power consumption.

Techniques for programmatically coordinating, and synchronizing execution of, automated testing in event-driven systems. One or more user-provided test system event listeners listen for generated events and updates test system status accordingly. A user-provided test suite definition invokes a test framework interface, thereby defining the structure of a test suite. This test suite is executed, referring to the test system status to determine when to move to a next stage (e.g., to a next test case or next test module). Test system status may also be updated directly from a test case or test module (e.g., when the test designer determines that the tested code will not generate events that can be leveraged for test status information).

The invention provides a model-based gasoline engine calibration method, belongs to the technical field of gasoline engines, and designs and develops a statistical model based gasoline engine calibration method mainly for a dynamic property optimized calibration process of a gasoline engine. The model-based gasoline engine calibration method comprises the following steps: (1), design of test operating points, (2) establishment of a mathematical statistics model and (3), optimization of calibrating procedure design, wherein firstly, relatively fewer test points can be selected in a test design phase so as to reduce workload; then an engine statistical model is established with a mathematical statistics method after related data are acquired; and finally, optimized calibration is performed on the basis of the statistical model. Under the premise that the performance of the gasoline engine is improved without loss of calibration accuracy, the model-based gasoline engine calibration method has the advantages as follows: time is saved, the cost is reduced, the output torque is increased, and the problems that the traditional manual calibration method is time-consuming, labor-consuming and low in efficiency and the conventional automatic optimized calibration equipment is complicated in technology and expensive are solved.

Methods, articles of manufacture and apparatus for testing design layouts. Design layout software may be configured to display a layout diagram in a first area of a graphical user interface (GUI) screen. Parameters for testing the layout may be entered in a second area of the GUI screen. Upon receiving one or more test parameters, the layout software may be configured to identify portions of the layout that do not conform to design rules based on the test parameters.

The invention relates to a bamboo forest carbon sequestration capacity measuring and carbon sequestration capacity improving fertilizer preparation method, which comprises the following six steps: 1, test design: selecting a bamboo forest sample plot, setting and processing a test area, then sampling, determining and computing; measurement and computation of annual respiration carbon emission amount of bamboo forest: measuring soil respiration rate, computing greenhouse gas CO2 emission flux and CO2 emission amount in soil annular accumulated respiration and determining no-root respiration soil CO2 emission amount; 3, measurement and estimation of bamboo forest vegetation carbon storage; 4, measurement and computation of soil carbon storage; 5, computation of bamboo forest annual net carbon fixation amount; and 6, optimum fertilizer preparation for improving bamboo forest carbon sequestration capacity. Through fertilizer application according to the optimum fertilizer preparation scheme obtained in the method disclosed by the invention, the carbon sequestration capacity of the bamboo forest can be obviously improved, and the invention provides an effective and feasible novel scheme for solving the greenhouse effect caused by the increase of atmospheric CO2 concentration.

The invention relates to a test case design efficiency promotion method and system. The test case design efficiency promotion method comprises the following steps: classifying a business system into a plurality of business categories according to the business type, respectively classifying each business category into a plurality of business subclasses, wherein each business subclass comprises a plurality of business modules; acquiring a plurality of test cases designed by each business module, wherein each test case respectively comprises a plurality of test attributes; establishing a public case library in a catalogue form by utilizing a case management tool according to the business category and the business subclass corresponding to each test case; selecting a test case to test the to-be-tested test module according to a test condition; updating the public case library when any test case is modified. The test case in the public test case library corresponding to the module involved by the demand needs to be called for the specific test demand task, the test case does not need to be repeatedly designed, and the test work efficiency can be greatly improved.

The invention discloses an optimization method of capturing power consumption in a scan test. The optimization method of capturing power consumption in the scan test comprises the following steps: generating a netlist with a scan chain; grouping gating control clock units; designing a power constrain unit; combining with the generated netlist with the scan chain, conducting chip layout design which comprises a floorpan, a layout, a clock tree sythesis and wiring; reading a gate-level netlist with a scan structure, a process library, a timing sequence constrain file and a test protocol into an automatic test vector generating tool after the chip layout design is completed, conducting testability design rule checking, and generating a test vector; and conducting gate-level simulation to the test vector generated. By means of the optimization method of capturing the power consumption in the scan test, the capturing power consumption in a test process can be reduced significantly, the reduction of coverage or the sharp increase of the quantity of test vectors is not generated, changing of a test design process is needless, and realization is easy.

The test design cost of a circuit capable of accessing an external memory is reduced. There is included a built-in self-test circuit for use in testing an external memory separately from a memory controller for performing memory control in response to an access request to the external memory capable of being coupled to a memory interface, and a TAP controller is used to control the built-in self-test circuit and referring to a test result. There is adopted a multiplexer for switchably selecting the memory controller or the built-in self-test circuit as a circuit for coupling to the memory interface in accordance with control information externally inputted through the TAP controller. The built-in self-test circuit programmably generates and outputs a pattern for a memory test in accordance with an instruction inputted through the TAP controller, and compares data read from the external memory with an expected value.

In an approach to selecting a set of test resources for testing a computer program including untested computer program code, one or more computer processors retrieve a time stamp for an untested computer program code, wherein the time stamp is indicative of a time of generation of the untested computer program code. The one or more computer processors calculate, based, at least in part, on the retrieved time stamp, an accuracy risk factor for the untested computer program code. The one or more computer processors select, based, at least in part, on the calculated accuracy risk factor, a set of one or more test resources from a pool of test resources.

A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.