237 results about "Test design" patented technology

The invention provides an execution method and device for a test case in a verification platform, equipment and a storage medium, and the method comprises the steps: obtaining a target test case constructed by an interpreted language, and starting the execution of the target test case on the verification platform; the target test case is a program for providing an excitation component for verification of the to-be-tested design file; in response to execution of the target test case, generating a test trigger instruction through the flow controller, and transmitting the test trigger instruction to a sequence control tool in the verification platform through the socket interface; a sequence control tool is used for analyzing the test trigger instruction, the starting and excitation sending sequence of an excitation assembly in the execution process of the target test case is controlled through an analysis result, an excitation execution result is obtained, and the sequence control tool is compiled through a compilation type language; and the excitation execution result is transmitted to the flow controller through the socket interface to be output. According to the application, multi-language compatibility is realized by adopting the socket interface.

The invention discloses a simulation test method and device, computer equipment and a storage medium, and relates to the technical field of semiconductors, and the method comprises the steps: carrying out the simulation test of a to-be-tested design, and carrying out the decrement counting of a work clock of the to-be-tested design based on a preset timer; detecting an output result of the to-be-tested design; and if the output result is not detected when the counting is finished, stopping the simulation test of the to-be-tested design. According to the method, whether the to-be-tested design has the abnormal state or not is judged by detecting the output condition of the to-be-tested design in real time, and simulation is automatically stopped if the abnormal condition exists. The overtime detection time does not need to be set, and the management of the test case is simplified, so that the simulation test efficiency is improved, the promotion of the verification task is accelerated, and the problem of easy suspension in the simulation test process is solved.

The invention discloses a software and hardware decoupling analogue simulation test system, belongs to the technical field of vehicle analogue simulation test, and solves the technical problem that a traditional test system often neglects the actual situation in the operation process due to excessive consideration from the theoretical perspective. The system comprises an environment simulation module which is used as an integrated tool and platform for realizing automobile virtual research and development through an analog simulation technology, integrates an automobile driving environment model, a vehicle-mounted environment sensing model and a traffic model, and provides a three-dimensional digital virtual test scene modeling and editing function; the vehicle dynamics simulation module is used for providing vehicle dynamics simulation, scene construction, sensor construction and data interface construction; and the evaluation index and evaluation software module is used for receiving results output by the environment simulation module and the vehicle dynamics simulation module and outputting a report. The invention focuses on simulating the working condition, road condition and scene of a real vehicle to test the designed algorithm model, software and hardware, so as to find and solve problems as soon as possible.

The invention provides an optimization method for metal surface laser cladding process parameters, and relates to the technical field of metal processing optimization, and the optimization method comprises the following process steps: step 1, determining an optimization target which is mainly used for determining a performance target of a cladding process and determining a quality target of the cladding process; 2, preliminary parameter selection and test design are mainly used for determining the cladding process parameter range and constructing a test model; step 3, test implementation and data acquisition; 4, data analysis and parameter optimization; and 5, verification and feedback adjustment are carried out. An orthogonal table is constructed by setting an orthogonal test, an optimal parameter combination is obtained by utilizing range analysis, a regression model equation can also be constructed by setting a response curved surface method test, and parameters are substituted into regression model parameters for operation, so that the optimal parameter combination can be obtained, the parameter optimization efficiency can be effectively improved, and the method is suitable for large-scale popularization and application. Meanwhile, records and experiences can be formed, and the method is widely applied to production practice.

The invention discloses a post-pumping air tank robustness collaborative design method considering hydraulic parameter time-varying characteristics, which comprises the following steps: defining a hydraulic parameter uncertainty fluctuation interval of a water delivery system in a full life cycle, and setting a body structure decision variable range of a post-pumping air tank; performing combined sampling in the water conservancy parameter uncertainty fluctuation interval and the body structure decision variable range by using a test design method to generate an initial sample set; performing steady-state and transient-state coupling simulation on the initial sample set, constructing a constant-flow operation condition of the water delivery system by using a hydraulic equation, updating a water pump working point and pipeline pressure distribution, performing transient simulation by using a characteristic line method to obtain a hydraulic response index, and training to obtain a water hammer response agent model; constructing a robustness optimization objective function based on failure probability constraint; and performing global optimization on the target function by using an intelligent optimization algorithm, calling the water hammer response agent model to perform random simulation, evaluating a failure probability, and outputting a target design scheme.

The invention relates to the technical field of integrated circuit design and verification, and discloses a chip simulation verification acceleration method, device and equipment and a storage medium, and the method comprises the steps: obtaining simulation analysis of a tested design file and excitation, obtaining a corresponding simulation result, analyzing a module occupying the most simulation time and memory according to the simulation result, and obtaining a simulation result; the method comprises the following steps of: decomposing a simulation process of a whole chip into a plurality of simulation operation tasks by combining a design requirement and a function definition of the chip; distributing the disassembled operation tasks to a multi-core processor for block simulation; and setting a dynamic performance optimization option DPO, performing multiple tests to collect data, and generating a simulation verification result based on a simulation result and an original design expectation. According to the method, the to-be-tested design is disassembled for layered compiling simulation, and the DPO is set for dynamic performance optimization, so that the simulation speed is increased, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.

The method for determining the heat pipe reactor rotary drum test period comprises the following steps: providing a jamming probability of a rotary drum driving mechanism of a heat pipe reactor and a common cause jamming probability of the rotary drum driving mechanism; establishing a fault tree model, and calculating the failure probability of the drum driving mechanism and the importance of the drum driving mechanism jamming basic event and the drum driving mechanism common cause jamming basic event; establishing a reference curve of the failure probability and the importance degree of the drum driving mechanism along with the change of the test period; and taking a test period corresponding to an intersection point of the two reference curves as a reference test period of the heat pipe reactor drum cycle test. According to the method, periodic test design of the drum driving mechanism can be guided in a quantitative calculation mode, and the reactor economy is optimized. The invention further provides a computing device.

The invention provides a multi-stress reliability enhancement test method based on a support vector machine. Comprising the steps of training a support vector machine model representing a mapping relation between multiple stress and failure characteristic quantities, constructing a scoring model containing three factors for multiple stress test candidate points, and selecting a point with the lowest score from the multiple stress test candidate points for testing. And obtaining a final multi-stress limit envelope corresponding to the failure characteristic quantity threshold value by using the latest support vector machine model. On the basis of saving a large amount of test overhead and retaining the core characteristics of the reliability enhancement test, the reliability enhancement test efficiency is improved. A pre-cured test design of a traditional reliability strengthening test is changed into a dynamic sequential test design, a single stress limit is changed into a multi-stress limit, and a discrete boundary is changed into a continuous boundary.

The invention provides a part lightweight design method based on a random forest model, and the method comprises the steps: defining a design variable and a response target, and generating a sample point through a test design sampling method; geometric modeling and updating, finite element preprocessing, solving calculation and result extraction are automatically completed through parameterized scripts, and a sample data set is formed; independently training a random forest regression model for each performance response by using the sample data set, and constructing a quality rapid calculation model; verifying the random forest agent model until all agent models meet preset precision requirements; on the basis of the proxy model, constructing an optimization problem, carrying out optimization solution by adopting a multi-objective optimization algorithm, and outputting a Pareto optimal solution set; and selecting a candidate design scheme from the Pareto optimal solution set, executing high-precision finite element simulation, comparing a prediction result and a simulation result of the proxy model, and if an error is within an acceptable range and all performances meet design requirements, determining a final lightweight design scheme.

The invention relates to the technical field of automobile software testing, and discloses a software test case automatic generation method and system based on a language AI large model, and the method comprises the steps: extracting a position path, a function name and a test design direction content from user input information, generating a configuration file through a preset Prompt template, and calling the AI large model to interpret the user intention. Function, performance and regulation analysis tasks are split, an AI large model is utilized to integrate information, test design analysis is carried out, classification and redundant content cutting are carried out, self-check evaluation is completed, a formatted Markdown test design file is generated and then converted into a mind map, an engineer checks the mind map, manual modification and optimization are carried out according to needs, and the method is simple and convenient. The modified mind map is converted into a Markdown file, a formatted test case file is generated, the difference of the Markdown file before and after modification is compared through an AI large model, a Prompt template is updated, according to the method, the test case can be efficiently generated, manpower dependence is reduced, and therefore the adaptability of the test case is guaranteed.

The invention provides a small sample AI proxy model construction method based on sensitivity analysis and supplementary sampling, and the method comprises the steps: carrying out the global sensitivity analysis through the automatic simulation process of parameterized parts of wind power equipment in combination with test design, and removing insensitive variables, thereby guaranteeing the accuracy and standardization of a sample, avoiding the invalid consumption of irrelevant variables, and achieving the automatic simulation of the parameterized parts of the wind power equipment. Latin hypercube sampling is adopted based on key variables, a core design area is uniformly covered, the number of initial simulation times is greatly reduced, the cost is controlled, the problem that the generalization ability is poor due to uneven small sample distribution is solved, a deep neural network regression model is trained through a training set, the strong nonlinear fitting ability of the deep neural network regression model adapts to a complex mapping relation, the core law is efficiently learned, and the robustness is high. Based on initial model prediction precision and sensitivity information, samples are accurately supplemented in weak areas, samples are not increased blindly, investment is reduced, prediction blind areas are made up, errors are gradually reduced through iterative training closed-loop optimization, and finally the small sample AI proxy model meeting preset requirements is obtained.

The invention provides a hybrid level enhanced random algorithm based on double-loop optimization and a cross-platform implementation method thereof, and belongs to the technical field of modeling and parameter, and the method comprises the following steps: S1, initialization; s2, setting algorithm parameters; s3, executing internal circulation, and executing local search under a fixed threshold value; s4, judging constraint conditions; when there is no constraint condition, generating a candidate solution; s5, calculating a target function value; s6, judging updating of the matrix according to the target function value; s7, returning to an outer loop, and adjusting a threshold value Th according to the frequency for receiving the new design and the number of iterations; s8, after M iterations are completed, the acceptance rate and the improvement rate are calculated; s9, updating the threshold value Th; and S10, judging a condition for stopping iteration. According to the method, the problems that a general construction method is lacked, local optimum is easy to sink and cross-platform deployment is difficult to realize in a multi-factor mixing level test design are solved.

Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.

The invention relates to the technical field of integrated circuits, and provides a verification platform, a verification method, electronic equipment and a medium. The verification platform comprises: an application layer bus function level model comprising a customized interface for a to-be-tested design for interacting with the to-be-tested design, the to-be-tested design being a PCIe protocol docking and protocol compliance test suite, and the to-be-tested design being a PCIe protocol docking and protocol compliance test suite; the PCIe protocol docking and protocol compliance test suite supports a verification demand of a physical layer intellectual property core and a verification demand of protocol consistency of a PCIe controller and a physical layer subsystem level; and the to-be-tested design interacts with the application layer bus function level model through the customized interface. Thus, the integration and through-flow debugging cost of subsystem protocol consistency verification is reduced, the verification period of a docking test of PCIe subsystem protocol standardization is shortened, and the completeness of docking verification of a full quantization protocol of a PCIe subsystem and the platform reuse efficiency are improved.

The invention discloses a super system application method, system and terminal based on an open source gap system, and the method comprises the steps: analyzing the demands of a target application scene, determining the equipment integration demands, the data circulation demands and the management demands, and designing the architecture of super equipment; the development rule engine module is integrated into an open source gap system and provides a rule configuration interface for a user; developing a data fusion module, and performing an accuracy test and a performance test; designing an equipment cascade management module, integrating the equipment cascade management module into an open-source and wide-gap system, and providing a multi-level equipment management function; a rule engine module, a data fusion module and an equipment cascade management module are integrated into the super system, and function testing, performance testing and compatibility testing are conducted on the super system; and deploying the super system in an actual application environment, and adjusting the super system according to an actual operation condition and user feedback. According to the invention, the data processing efficiency is improved, the data integration capability is enhanced, and the equipment management is optimized.

The invention discloses a universal verification method of a coding and decoding module and a related device, and the method comprises the steps: obtaining different control parameters of a to-be-tested design and key message fields and key configuration information corresponding to each control parameter, and storing the different control parameters and the key message fields and the key configuration information in a queue, each control parameter corresponding to a coding scene or a decoding scene; in response to the verification request, a test message is generated based on the queue, and the test message comprises key message fields and key configuration information corresponding to one or more control parameters in the queue; and sending the test message to the to-be-tested design and the reference model, and comparing the output of the to-be-tested design with the output of the reference model to obtain a verification result. According to the method provided by the invention, the test messages meeting different scenes of the to-be-tested design can be generated, the problems existing in a random sequence are effectively avoided, and the verification efficiency and the completeness rate are improved; the method is high in universality, and the complexity of verification of the coding and decoding module is reduced.

The present invention relates to the technical field of aircraft test design, and in particular to an aircraft sequential test design method based on an expected probability box boundary improvement criterion, which specifically includes the following steps: S1, initial test design, obtaining a sample set that affects the output results in the aircraft test; S2, establishing a proxy model using a Gaussian process regression model based on information of a known sample set D; S3, based on the established proxy model, determining the next test sample point according to a sampling point criterion corresponding to the expected probability box boundary improvement criterion; S4: calculating the true response of the aircraft at the test sample point and updating the sample set; S5: judging whether the test stop criterion is met, and if so, outputting the final proxy model; if not, repeating the operations of S2-S5. The present invention quickly and effectively finds the maximum or minimum value of the objective function by selecting appropriate sampling points in the test design. This new optimization criterion has significant advantages, especially in finding the maximum value problem.

The invention discloses an SERDES verification method and device, and the method comprises the steps: obtaining a protocol type and a configuration mode supported by a to-be-tested SERDES, generating a first compiling simulation script according to the protocol type, and enabling the script to comprise the clock frequency, the data rate, the parameter configuration of a coding mode, the generation rule of simulation excitation, and a result output path; based on the test requirement and the protocol type, a test top layer file and a file list are determined, and the file list comprises paths of the to-be-tested design file and the test excitation file; calling a script, executing first compiling simulation, and generating a waveform file and a log file; switching to a second protocol type, updating the test top layer file and the file list, and generating a second compiling simulation script; executing secondary compiling simulation to generate a waveform file and a log file corresponding to the second protocol; the log file is analyzed, the bit error rate, the function coverage rate and the time sequence violation are counted, and a comprehensive test report is generated. The method can accelerate the verification speed and reduce the development time.

The invention relates to the technical field of software development, and discloses a code testing method and device, computer equipment and a storage medium. The code testing method comprises the following steps: determining test input information and a target test type through an obtained target test request; determining a to-be-tested code and a test scheme file according to the test input information, and preprocessing the to-be-tested code and the test scheme file to obtain a target knowledge graph corresponding to the target test request; searching a target test design task matched with the target test type from a preset test task list; determining a task cue word, a task analysis model and a task output template according to the target test design task, and obtaining a task output result according to the task cue word, the target knowledge graph, the task analysis model and the task output template; when it is confirmed that the task output result is the target test case, test processing on the to-be-tested code is executed according to the target test case, and a target test result is obtained. According to the invention, the interaction complexity is reduced, and the test efficiency and the test accuracy are improved.

The invention provides an RDMA queue management module verification system and method based on a UVM. The system comprises a test case base class, a to-be-tested design top layer and a plurality of instantiation interfaces, the test case base class is provided with a pre-constructed verification environment; the verification environment comprises a reference model assembly, a scoreboard assembly and an agent assembly; the proxy component is used for generating an excitation signal corresponding to the current test module and driving the excitation signal to a to-be-tested design top layer and the reference model component; the reference model assembly is used for generating an expected signal according to the received excitation signal and sending the expected signal to the scoreboard assembly; the scoreboard assembly is used for comparing the expected signal with an actual signal output by the design top layer to be tested to obtain a verification result corresponding to the current test module; the to-be-tested design top layer is used for generating a corresponding actual signal according to the received excitation signal and inputting the actual signal to the scoreboard assembly. The construction efficiency and flexibility of the verification environment are improved, and the detection capability is enhanced.

The embodiment of the invention provides a verification method and device, electronic equipment and a readable storage medium, and the method comprises the steps: configuring a test item in a first file, and setting a link address of the first file in a link script of a test program; the test program is used for providing a bottom layer operation environment for a test case of the test item; compiling the test program based on a compiling tool chain and the link script to obtain a binary file corresponding to the test program; performing mirror image packaging on the binary file and the first file to obtain a first mirror image file; and loading the first mirror image file in a simulation system, and driving a to-be-tested design to run the test program so as to load the first file from the link address and execute a test case corresponding to the test item. According to the embodiment of the invention, the compiling power consumption of the test program can be reduced, and the overall verification efficiency of the processor chip system can be improved.

A first set of features may be extracted from a first integrated circuit (IC) design. A trained machine learning (ML) model may predict a set of ranked test-case configurations for the first IC design based on the first set of features. A test-case configuration may correspond to a count of scan chain input and output ports and a scan chain length value.

The invention provides a method for simulating a logic system design, the logic system design comprises a to-be-tested design and a first C program associated with the to-be-tested design, and the method comprises the following steps: obtaining a plurality of operations of the first C program; reading operation positions of a plurality of operations of the C program in an executable file; determining memory addresses of the plurality of operations in a memory according to the operation positions; a callback function is set in the memory address and used for obtaining function parameters when the multiple operations are executed, and the function parameters comprise at least one of a destination index, a source index, a data register or a handle type of the multiple operations; and generating an operation log of the first C program according to the function parameters of the plurality of operations.

The invention discloses a test case generation method and device, a storage medium and electronic equipment, and the method is executed by a test case generation model, and comprises the steps: obtaining a case generation guide constructed for a to-be-tested application, according to a test design process in the use case generation guide, extracting a test demand point from a test demand of the to-be-tested application; determining a test verification point based on the test demand point, and determining a target test method in candidate test methods in the use case generation guide based on a verification type to which the test verification point belongs; and generating a test case for the to-be-tested application based on the target test method and the test verification point. By executing the technical scheme, the generation efficiency of the test case and the coverage rate of the test verification points are improved.

The invention provides a verification method and device for a to-be-tested design DUT, equipment and a storage medium. The method comprises the following steps: determining target excitation according to the sending times of directional excitation corresponding to each to-be-verified function; arbitrating each to-be-verified function by using an arbiter to obtain an arbitration result corresponding to the first target function; and generating the target excitation corresponding to the first target function according to the arbitration result corresponding to the first target function, and verifying the DUT according to the target excitation corresponding to the first target function. According to the method, sending of the directional excitation corresponding to the to-be-verified function is added on the basis of the random excitation, wrong verification or missed verification of some to-be-verified functions is avoided, and verification effectiveness and verification quality are improved.

The invention discloses a communication debugging method and device, electronic equipment and a storage medium, and relates to the technical field of communication, and the method comprises the steps: integrating a to-be-tested design and a transaction processor to a top layer module of a simulation environment, and mapping the top layer module to a hardware acceleration simulation platform; a simulation database corresponding to the top layer module is generated on the hardware acceleration simulation platform; loading the simulation database to a hardware acceleration simulation platform, and starting a runtime environment; calling an application program interface provided by the transaction processor through the test code to set communication parameters; starting simulation to realize communication debugging between the to-be-tested design and the transaction processor; wherein the transaction processor is used for realizing a communication link in a virtualization mode. According to the method and the device, the dependence on physical peripherals is eliminated, and efficient and flexible communication debugging is realized on the premise that actual hardware connection is not needed.

The embodiment of the invention provides an avionics equipment intelligent testability design system based on a Matlab-Simulink joint model, and relates to the technical field of avionics equipment testability. The testability design system comprises a demand analysis module, a dynamic model construction and management module, a testability scheme design module, an automatic test script generation and execution module, a result analysis and optimization module and a cloud report generation and sharing module. The modules cooperate together to realize high efficiency, automation and intelligentization of the test design and verification process of the avionics equipment.

The invention provides a method and system for building a flight control computer simulation test system, and belongs to the technical field of aircrafts, and the method comprises the steps: building a structured simulation test knowledge base of an aircraft; a flight control semi-physical simulation test environment and an intelligent agent for operating and sensing the flight control semi-physical simulation test environment are established, and the intelligent agent is formed through training of a structured simulation test knowledge base of the aircraft; building a sensing layer, a decision layer, a memory layer and an execution layer for the intelligent agent to form a flight control simulation intelligent agent; and physically connecting the flight control semi-physical simulation test environment with the flight control simulation agent to form a flight control computer simulation test system. According to the invention, the flight control simulation intelligent agent is used for carrying out test design, test execution control and result analysis on a flight control semi-physical simulation test environment, so that the purpose of autonomously completing a simulation test without relying on manpower is achieved, the influence of introduction of human errors is avoided, and the reliability of a simulation test result is improved.

The invention relates to the field of electrical digital data processing, and provides a roadbed filler and geocell setting optimization analysis method, which comprises the following steps: S1, carrying out joint simulation analysis on three factors to obtain different settlement displacement values under the joint action of the three factors; s2, the settlement displacement value is substituted into response analysis software, and a Box-Behnken response optimization method is used for analysis; s3, analyzing the primary and secondary effect relationship of the influence of the three factors on roadbed settlement according to a settlement regression analysis result obtained through response analysis; and S4, according to the regression equation model, analyzing the response curved surface diagram and the contour map, determining the influence of three factors of experimental design on roadbed settlement, and taking a settlement minimum value as an optimization analysis target to obtain an optimal prediction scheme. According to the method, a test design method based on three levels is designed through a Box-Behnken response optimization method, and through reasonable arrangement of test points, a plurality of factors and the interaction of the factors can be evaluated under the condition that the number of test times is small.

This invention relates to the field of chip verification technology, and more particularly to a random verification method, electronic device, and medium based on register arrays. S1: Set m=1, execute S2; S2: Send data to RA in the target register array. m and RB m Input the same random test stimulus; S3, RA m Predict the random write value, and set F m Updated to RA m Predicted random write values; S4, RB m Write random numbers based on the input random test stimulus; S5, read the currently stored data in the RTL instances of all registers in the chip under test design in random order and compare it with the corresponding reference value. If they are all the same, proceed to S6; otherwise, the verification fails and the process ends; S6, compare m and M. If m