137 results about "Test design" patented technology

The invention discloses a simulation test method and device, computer equipment and a storage medium, and relates to the technical field of semiconductors, and the method comprises the steps: carrying out the simulation test of a to-be-tested design, and carrying out the decrement counting of a work clock of the to-be-tested design based on a preset timer; detecting an output result of the to-be-tested design; and if the output result is not detected when the counting is finished, stopping the simulation test of the to-be-tested design. According to the method, whether the to-be-tested design has the abnormal state or not is judged by detecting the output condition of the to-be-tested design in real time, and simulation is automatically stopped if the abnormal condition exists. The overtime detection time does not need to be set, and the management of the test case is simplified, so that the simulation test efficiency is improved, the promotion of the verification task is accelerated, and the problem of easy suspension in the simulation test process is solved.

The invention discloses a post-pumping air tank robustness collaborative design method considering hydraulic parameter time-varying characteristics, which comprises the following steps: defining a hydraulic parameter uncertainty fluctuation interval of a water delivery system in a full life cycle, and setting a body structure decision variable range of a post-pumping air tank; performing combined sampling in the water conservancy parameter uncertainty fluctuation interval and the body structure decision variable range by using a test design method to generate an initial sample set; performing steady-state and transient-state coupling simulation on the initial sample set, constructing a constant-flow operation condition of the water delivery system by using a hydraulic equation, updating a water pump working point and pipeline pressure distribution, performing transient simulation by using a characteristic line method to obtain a hydraulic response index, and training to obtain a water hammer response agent model; constructing a robustness optimization objective function based on failure probability constraint; and performing global optimization on the target function by using an intelligent optimization algorithm, calling the water hammer response agent model to perform random simulation, evaluating a failure probability, and outputting a target design scheme.

The invention relates to the technical field of integrated circuit design and verification, and discloses a chip simulation verification acceleration method, device and equipment and a storage medium, and the method comprises the steps: obtaining simulation analysis of a tested design file and excitation, obtaining a corresponding simulation result, analyzing a module occupying the most simulation time and memory according to the simulation result, and obtaining a simulation result; the method comprises the following steps of: decomposing a simulation process of a whole chip into a plurality of simulation operation tasks by combining a design requirement and a function definition of the chip; distributing the disassembled operation tasks to a multi-core processor for block simulation; and setting a dynamic performance optimization option DPO, performing multiple tests to collect data, and generating a simulation verification result based on a simulation result and an original design expectation. According to the method, the to-be-tested design is disassembled for layered compiling simulation, and the DPO is set for dynamic performance optimization, so that the simulation speed is increased, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.

The invention provides a part lightweight design method based on a random forest model, and the method comprises the steps: defining a design variable and a response target, and generating a sample point through a test design sampling method; geometric modeling and updating, finite element preprocessing, solving calculation and result extraction are automatically completed through parameterized scripts, and a sample data set is formed; independently training a random forest regression model for each performance response by using the sample data set, and constructing a quality rapid calculation model; verifying the random forest agent model until all agent models meet preset precision requirements; on the basis of the proxy model, constructing an optimization problem, carrying out optimization solution by adopting a multi-objective optimization algorithm, and outputting a Pareto optimal solution set; and selecting a candidate design scheme from the Pareto optimal solution set, executing high-precision finite element simulation, comparing a prediction result and a simulation result of the proxy model, and if an error is within an acceptable range and all performances meet design requirements, determining a final lightweight design scheme.

The invention relates to the technical field of automobile software testing, and discloses a software test case automatic generation method and system based on a language AI large model, and the method comprises the steps: extracting a position path, a function name and a test design direction content from user input information, generating a configuration file through a preset Prompt template, and calling the AI large model to interpret the user intention. Function, performance and regulation analysis tasks are split, an AI large model is utilized to integrate information, test design analysis is carried out, classification and redundant content cutting are carried out, self-check evaluation is completed, a formatted Markdown test design file is generated and then converted into a mind map, an engineer checks the mind map, manual modification and optimization are carried out according to needs, and the method is simple and convenient. The modified mind map is converted into a Markdown file, a formatted test case file is generated, the difference of the Markdown file before and after modification is compared through an AI large model, a Prompt template is updated, according to the method, the test case can be efficiently generated, manpower dependence is reduced, and therefore the adaptability of the test case is guaranteed.

The invention provides a small sample AI proxy model construction method based on sensitivity analysis and supplementary sampling, and the method comprises the steps: carrying out the global sensitivity analysis through the automatic simulation process of parameterized parts of wind power equipment in combination with test design, and removing insensitive variables, thereby guaranteeing the accuracy and standardization of a sample, avoiding the invalid consumption of irrelevant variables, and achieving the automatic simulation of the parameterized parts of the wind power equipment. Latin hypercube sampling is adopted based on key variables, a core design area is uniformly covered, the number of initial simulation times is greatly reduced, the cost is controlled, the problem that the generalization ability is poor due to uneven small sample distribution is solved, a deep neural network regression model is trained through a training set, the strong nonlinear fitting ability of the deep neural network regression model adapts to a complex mapping relation, the core law is efficiently learned, and the robustness is high. Based on initial model prediction precision and sensitivity information, samples are accurately supplemented in weak areas, samples are not increased blindly, investment is reduced, prediction blind areas are made up, errors are gradually reduced through iterative training closed-loop optimization, and finally the small sample AI proxy model meeting preset requirements is obtained.

The invention provides a hybrid level enhanced random algorithm based on double-loop optimization and a cross-platform implementation method thereof, and belongs to the technical field of modeling and parameter, and the method comprises the following steps: S1, initialization; s2, setting algorithm parameters; s3, executing internal circulation, and executing local search under a fixed threshold value; s4, judging constraint conditions; when there is no constraint condition, generating a candidate solution; s5, calculating a target function value; s6, judging updating of the matrix according to the target function value; s7, returning to an outer loop, and adjusting a threshold value Th according to the frequency for receiving the new design and the number of iterations; s8, after M iterations are completed, the acceptance rate and the improvement rate are calculated; s9, updating the threshold value Th; and S10, judging a condition for stopping iteration. According to the method, the problems that a general construction method is lacked, local optimum is easy to sink and cross-platform deployment is difficult to realize in a multi-factor mixing level test design are solved.

The invention relates to the technical field of integrated circuits, and provides a verification platform, a verification method, electronic equipment and a medium. The verification platform comprises: an application layer bus function level model comprising a customized interface for a to-be-tested design for interacting with the to-be-tested design, the to-be-tested design being a PCIe protocol docking and protocol compliance test suite, and the to-be-tested design being a PCIe protocol docking and protocol compliance test suite; the PCIe protocol docking and protocol compliance test suite supports a verification demand of a physical layer intellectual property core and a verification demand of protocol consistency of a PCIe controller and a physical layer subsystem level; and the to-be-tested design interacts with the application layer bus function level model through the customized interface. Thus, the integration and through-flow debugging cost of subsystem protocol consistency verification is reduced, the verification period of a docking test of PCIe subsystem protocol standardization is shortened, and the completeness of docking verification of a full quantization protocol of a PCIe subsystem and the platform reuse efficiency are improved.

The invention discloses a universal verification method of a coding and decoding module and a related device, and the method comprises the steps: obtaining different control parameters of a to-be-tested design and key message fields and key configuration information corresponding to each control parameter, and storing the different control parameters and the key message fields and the key configuration information in a queue, each control parameter corresponding to a coding scene or a decoding scene; in response to the verification request, a test message is generated based on the queue, and the test message comprises key message fields and key configuration information corresponding to one or more control parameters in the queue; and sending the test message to the to-be-tested design and the reference model, and comparing the output of the to-be-tested design with the output of the reference model to obtain a verification result. According to the method provided by the invention, the test messages meeting different scenes of the to-be-tested design can be generated, the problems existing in a random sequence are effectively avoided, and the verification efficiency and the completeness rate are improved; the method is high in universality, and the complexity of verification of the coding and decoding module is reduced.

The present invention relates to the technical field of aircraft test design, and in particular to an aircraft sequential test design method based on an expected probability box boundary improvement criterion, which specifically includes the following steps: S1, initial test design, obtaining a sample set that affects the output results in the aircraft test; S2, establishing a proxy model using a Gaussian process regression model based on information of a known sample set D; S3, based on the established proxy model, determining the next test sample point according to a sampling point criterion corresponding to the expected probability box boundary improvement criterion; S4: calculating the true response of the aircraft at the test sample point and updating the sample set; S5: judging whether the test stop criterion is met, and if so, outputting the final proxy model; if not, repeating the operations of S2-S5. The present invention quickly and effectively finds the maximum or minimum value of the objective function by selecting appropriate sampling points in the test design. This new optimization criterion has significant advantages, especially in finding the maximum value problem.

The invention provides an RDMA queue management module verification system and method based on a UVM. The system comprises a test case base class, a to-be-tested design top layer and a plurality of instantiation interfaces, the test case base class is provided with a pre-constructed verification environment; the verification environment comprises a reference model assembly, a scoreboard assembly and an agent assembly; the proxy component is used for generating an excitation signal corresponding to the current test module and driving the excitation signal to a to-be-tested design top layer and the reference model component; the reference model assembly is used for generating an expected signal according to the received excitation signal and sending the expected signal to the scoreboard assembly; the scoreboard assembly is used for comparing the expected signal with an actual signal output by the design top layer to be tested to obtain a verification result corresponding to the current test module; the to-be-tested design top layer is used for generating a corresponding actual signal according to the received excitation signal and inputting the actual signal to the scoreboard assembly. The construction efficiency and flexibility of the verification environment are improved, and the detection capability is enhanced.

The invention discloses a test case generation method and device, a storage medium and electronic equipment, and the method is executed by a test case generation model, and comprises the steps: obtaining a case generation guide constructed for a to-be-tested application, according to a test design process in the use case generation guide, extracting a test demand point from a test demand of the to-be-tested application; determining a test verification point based on the test demand point, and determining a target test method in candidate test methods in the use case generation guide based on a verification type to which the test verification point belongs; and generating a test case for the to-be-tested application based on the target test method and the test verification point. By executing the technical scheme, the generation efficiency of the test case and the coverage rate of the test verification points are improved.

The invention discloses a communication debugging method and device, electronic equipment and a storage medium, and relates to the technical field of communication, and the method comprises the steps: integrating a to-be-tested design and a transaction processor to a top layer module of a simulation environment, and mapping the top layer module to a hardware acceleration simulation platform; a simulation database corresponding to the top layer module is generated on the hardware acceleration simulation platform; loading the simulation database to a hardware acceleration simulation platform, and starting a runtime environment; calling an application program interface provided by the transaction processor through the test code to set communication parameters; starting simulation to realize communication debugging between the to-be-tested design and the transaction processor; wherein the transaction processor is used for realizing a communication link in a virtualization mode. According to the method and the device, the dependence on physical peripherals is eliminated, and efficient and flexible communication debugging is realized on the premise that actual hardware connection is not needed.

This invention relates to the field of chip verification technology, and more particularly to a random verification method, electronic device, and medium based on register arrays. S1: Set m=1, execute S2; S2: Send data to RA in the target register array. m and RB m Input the same random test stimulus; S3, RA m Predict the random write value, and set F m Updated to RA m Predicted random write values; S4, RB m Write random numbers based on the input random test stimulus; S5, read the currently stored data in the RTL instances of all registers in the chip under test design in random order and compare it with the corresponding reference value. If they are all the same, proceed to S6; otherwise, the verification fails and the process ends; S6, compare m and M. If m

The invention relates to the technical field of test design, in particular to a key factor mining-based accommodating and arranging condition optimization method, medium and equipment, which are characterized in that accommodating and arranging conditions are generated by analyzing a target text, an initial simulation queue is constructed in combination with database retrieval, and baseline feature distribution is analyzed, so that representative research crowds can be obtained without real object recruitment; the test cost is reduced; a panoramic object feature matrix is constructed by integrating multi-dimensional data, the limitation of a single feature is broken through, and comprehensive data support is provided for key factor mining; the contribution degree of each characteristic variable to the preset key outcome is analyzed based on the matrix, and the key characteristic variables are positioned, so that the experience driving is changed into the data driving, and the scientificity and the pertinence of the accommodating and arranging condition design are improved; the accommodating and arranging conditions are dynamically adjusted through the closed-loop optimization process, it is ensured that the target accommodating and arranging condition set gives consideration to queue representativeness, feature pertinence and distribution rationality, and the design scientificity and success rate of clinical tests are improved.

The invention discloses a data processing model training and FCBGA packaging structure material matching method with a cover. According to the specific implementation scheme, a three-dimensional finite element model of a target packaging structure is constructed based on geometric parameters and material parameters of the target packaging structure; with the material parameters as design variables, inputting M groups of material parameter combinations generated through target test design based on the material parameters into the three-dimensional finite element model to obtain a data set; and extracting part of data from the data set based on the simulation test task as a training data set, and training the to-be-trained model based on the training data set to obtain a data processing model. According to the technical scheme, mechanical property analysis can be carried out on different materials according to the simulation result, so that the efficiency of evaluating the reliability of the packaging structure is improved, and the trial and error cost is reduced.

An information processing device according to the present invention is for generating a prompt for causing a language model to perform test design for an application, said information processing device comprising a prompt generation unit that reads out test-related information, which pertains to a test of the application, from an information storage unit storing the test-related information, and that uses the test-related information to generate the prompt.

The application provides a CMG (control moment gyro) failure test design method based on Gaussian process regression, which is suitable for test design of CMG working characteristics in a multi-stress coupling environment. The method reflects the mapping relationship between test factors and test indexes by using a Gaussian process regression model, establishes a prediction model based on simulation data, constructs an utility function, expands a training set in a sequential manner, updates the prediction model until the accuracy requirement is met. All simulation sample points are subjected to cluster analysis (clustered into at least two categories), and then part of the sample points in each category are randomly selected for testing, so that the CMG working characteristics are verified, and efficient test verification of the CMG working characteristics can be realized.

The embodiment of the invention provides a document generation method and device. According to the method, the test item can be hierarchically split through mind map node arrangement provided by the editing window, so that a tester can more clearly control the test coverage range, the risk of case omission is reduced, and the document generation precision is improved. Based on the document template and the target mind map, a test design document and a test case document are generated, and a demand tracking table is generated in the test design document. Due to the fact that the test design document and the test case document are from the same target mind map, the problem of information splitting of traditional scattered documents is avoided in the mode, the test design, the test requirements and the test cases have strong relation, and efficient tracking is facilitated.

The invention provides a fire fighting truck boom design method and device, electronic equipment and a storage medium. The method comprises the following steps: establishing a multidisciplinary joint simulation model; setting an initial design variable set; generating multiple groups of first design variable combinations based on a preset test design method; comparing each group of first design variable combinations with an allowable error range of a corresponding to-be-selected parameter in a to-be-selected parameter library, and screening out multiple groups of second design variable combinations; inputting each group of second design variable combinations into a simulation model, simulating hydraulic parameter change through a hydraulic system simulation module, calculating boom dynamic response through a mechanical dynamics simulation module, and obtaining boom linear velocity fluctuation amplitude of each group of second design variable combinations; according to the method, the shaking conditions of the boom under different working conditions and different design variables can be obtained without actual tests, the optimal parameters are determined, a theoretical basis is provided for model selection and design of the boom of the fire fighting truck, the development cost of the fire fighting truck is saved, and the development period is shortened.

This invention relates to a simulation test method for grouting of prestressed concrete bridge ducts, characterized by the following specific test steps: S1: Test design; S2: Equipment and material preparation; S3: Test commencement. This method addresses the problem that common duct grouting construction techniques, processes, and requirements cannot meet the needs of new grouting materials and equipment, such as "grouting from the lowest point." Some construction techniques have theoretical flaws, such as "flushing the duct before grouting and blowing away accumulated water with high-pressure air," and some lack reliable theoretical and practical basis. Therefore, it is necessary to study the influencing factors of duct grouting construction techniques based on current grouting materials, summarize the main factors affecting duct grouting quality, and propose an operable grouting process method.

The invention discloses a function test method and device, electronic equipment and a storage medium. The method comprises the steps of obtaining a to-be-optimized test case set from a test case library according to optimization content; according to the optimization content, determining an equivalence class updating type and an associated equivalence class of input and output items related to updating in the to-be-optimized test case set; determining a corresponding test case optimization scene according to the equivalence class update type and the associated equivalence class, and updating a to-be-optimized test case set according to the test case optimization scene to obtain an updated test case set; and controlling the updated test case set to execute a function test task. By adopting the technical scheme of the embodiment of the invention, specific operation steps are given in links of demand analysis, test case set selection, test case set maintenance, test case set execution and the like, the integrity is realized, and the scientificity, sufficiency and effectiveness of function test design and execution are improved.

The invention provides a USB measurement and control system collaborative verification platform building method based on the combination of System Verilog and a C language, and relates to the technical field of FPGA testing, the method is based on a Cadence IES simulation environment to build a verification platform of a layered tree topology architecture, the verification platform is independent of a tested design project file, a three-level system structure is adopted, and the verification platform is provided with a three-level architecture; the rtl design layer is used for storing a source code file of a to-be-tested USB measurement and control system baseband processing FPGA (Field Programmable Gate Array) described by adopting a register transmission level; and the tb test platform layer adopts a modular design and comprises a dutif interface definition module, a dutrap design packaging module, a tb test control module and a tbtop top layer integration module. According to the USB measurement and control system collaborative verification platform building method based on the combination of the System Verilog and the C language, intelligent generation of a verification environment is achieved through an automatic script, and the configuration complexity is remarkably reduced; and a parameterized configuration mechanism is adopted, so that different types of USB measurement and control systems can be quickly adapted, and excellent adaptability is shown.

The application relates to the field of software engineering and discloses a natural language driven GUI test rehearsal and test script generation method based on an LLM, which comprises the following steps: S1: test operation design: a test personnel and a planning agent realize human-machine cyclic interaction, and convert a high-level test case described in natural language into a low-level and standardized test operation description; wherein the planning agent adopts a hybrid architecture based on retrieval enhancement generation, the test personnel reviews, adjusts and feeds back the test operation description, and the feedback information is stored in a context memory module of the planning agent as prior knowledge; S2: test automation rehearsal: an operation agent takes the test operation description generated in S1 as input. Through human-machine cyclic interaction between the planning agent and the test personnel, automatic conversion of a natural language test case into a standardized test operation is realized, so that a test personnel without a programming background can also participate in automatic test design.

The invention discloses a production line simulation test object automatic creation and data integration system and method, and belongs to the technical field of industrial simulation, and the system comprises a unified data center platform, a data interface adaptation layer, a simulation object construction engine, a test management and execution engine, and a data acquisition and optimization engine. The method comprises the following steps: automatically analyzing input data according to a predefined meta-model template, and instantiating the input data into a specific simulation object; automatically docking and converting multi-source data through an adapter mode, and injecting the multi-source data into corresponding object attributes; test design, operation monitoring, data acquisition and verification optimization are integrally completed; the simulation modeling efficiency and accuracy can be greatly improved, the dependence on professional engineers is reduced, and rapid simulation analysis and optimization decision support of a production system are realized.

The invention discloses a poor sample sensor data expansion method based on a mechanical consistency mechanism, and belongs to the technical field of digital twinning. The method comprises the following steps: firstly, in a simulation analysis stage, establishing a real structure parameterized simulation model, and obtaining a real structure simulation response data set; secondly, in a ground test design stage, designing an equivalent ground test model and a loading scheme; thirdly, in the ground test development stage, ground test measuring points are arranged, and a ground test data set is obtained; fourthly, in the in-orbit and flight stages, collecting in-orbit and flight actual measurement data in real time, and obtaining an actual measurement sensor data set; 5, a data expansion stage: mapping the ground test data set into on-orbit and flight sensor data to obtain an expanded sensor data set; and finally, carrying out correlation evaluation and trimming on the expanded sensor data. According to the method, the problem that the equipment structure monitoring capability is insufficient due to the fact that the number of structure sensors is sparse and the space and ground states are different can be solved, and data expansion for digital twin high-precision modeling is achieved.

Embodiments of the present application provide a chip test method, a test platform and equipment, the method comprising: obtaining a simulation verification mode, the simulation verification mode comprising: Virtio module level verification and PCIe-to-Virtio subsystem level verification; compiling corresponding DUT code and verification environment code according to the simulation verification mode; performing simulation verification by using test cases, a Host side Virtio driver simulating a test scene set according to the test cases, calling a corresponding register adapter, and verifying different simulation verification modes based on the same test cases. In the embodiments of the present application, automatic adaptation of a to-be-tested design DUT and a verification environment instantiation is realized, and when Virtio module level verification and PCIe-to-Virtio subsystem level verification are performed, the test cases can be fully reused, thereby accelerating chip verification convergence and shortening the verification period.

The embodiment of the invention provides a universal verification component, a verification platform and a related method and equipment, and the universal verification component is applied to verification of a to-be-tested design compatible with an instruction set and comprises an instruction verification component and a micro instruction verification component, the instruction verification component is used for receiving an instruction sequence, generating an instruction decoding microinstruction entry sequence based on the instruction sequence, and providing the instruction decoding microinstruction entry sequence for the microinstruction verification component; the instruction sequence is generated based on an instruction set compatible with a to-be-tested design; the microinstruction verification assembly is used for receiving the instruction decoding microinstruction entry sequence and the test case microinstruction entry sequence to form a mixed microinstruction sequence, and generating test excitation based on the mixed microinstruction sequence; the test case microinstruction entry sequence is generated based on the test case; the test case is defined through the verification scene. According to the universal verification assembly provided by the embodiment of the invention, the coverage rate of each instruction in the verification process of the to-be-tested design compatible with the instruction set is improved.

The application relates to a V-belt life optimization design method based on a particle swarm algorithm, which comprises the following steps: constructing a life calculation model of a rubber V-belt; adopting a uniform test design method to take the tensile strength, reference force elongation, hardness and elastic modulus of the V-belt as sample inputs, and dividing a training set, a verification set and a test set; obtaining a life prediction value by using a pre-established life calculation model; taking the maximum value of the life of the V-belt as an objective function, the tensile strength, reference force elongation, hardness and elastic modulus of the V-belt as to-be-optimized parameters, and the slip rate and tension force failure threshold of the dynamic operation of the V-belt as constraint conditions. Compared with traditional optimization of the volume and size of the whole belt transmission system and simple physical calculation optimization of the life, the application has better global search capability and faster convergence speed for multi-parameter optimization, and has obvious practical value and broad application prospect.

A simulation failure identification and physical acceleration fusion-based MEMS sensor accelerated life test method comprises the following steps: aiming at environmental stress information of an MEMS sensor in a predetermined task process, identifying a failure form and a weak part by using structure simulation, and carrying out simulation evaluation on candidate acceleration stress working conditions constructed around the weak part; according to a preset life, a reliability requirement and a test resource constraint, selecting a combination of a stress level, test time and a sample number from the candidate working conditions to form an accelerated life test design scheme of the MEMS sensor; according to the method, the test period can be shortened on the premise that the test representativeness and accuracy are guaranteed, the test cost is reduced, and the effectiveness and universality of the reliability test design of the MEMS sensor are improved.